1 /* 2 * OMAP2plus display device setup / initialization. 3 * 4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 5 * Senthilvadivu Guruswamy 6 * Sumit Semwal 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 13 * kind, whether express or implied; without even the implied warranty 14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/string.h> 19 #include <linux/kernel.h> 20 #include <linux/init.h> 21 #include <linux/platform_device.h> 22 #include <linux/io.h> 23 #include <linux/clk.h> 24 #include <linux/err.h> 25 #include <linux/delay.h> 26 27 #include <video/omapdss.h> 28 #include "omap_hwmod.h" 29 #include "omap_device.h" 30 #include "omap-pm.h" 31 #include "common.h" 32 33 #include "soc.h" 34 #include "iomap.h" 35 #include "control.h" 36 #include "display.h" 37 #include "prm.h" 38 39 #define DISPC_CONTROL 0x0040 40 #define DISPC_CONTROL2 0x0238 41 #define DISPC_CONTROL3 0x0848 42 #define DISPC_IRQSTATUS 0x0018 43 44 #define DSS_SYSCONFIG 0x10 45 #define DSS_SYSSTATUS 0x14 46 #define DSS_CONTROL 0x40 47 #define DSS_SDI_CONTROL 0x44 48 #define DSS_PLL_CONTROL 0x48 49 50 #define LCD_EN_MASK (0x1 << 0) 51 #define DIGIT_EN_MASK (0x1 << 1) 52 53 #define FRAMEDONE_IRQ_SHIFT 0 54 #define EVSYNC_EVEN_IRQ_SHIFT 2 55 #define EVSYNC_ODD_IRQ_SHIFT 3 56 #define FRAMEDONE2_IRQ_SHIFT 22 57 #define FRAMEDONE3_IRQ_SHIFT 30 58 #define FRAMEDONETV_IRQ_SHIFT 24 59 60 /* 61 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC 62 * reset before deciding that something has gone wrong 63 */ 64 #define FRAMEDONE_IRQ_TIMEOUT 100 65 66 static struct platform_device omap_display_device = { 67 .name = "omapdss", 68 .id = -1, 69 .dev = { 70 .platform_data = NULL, 71 }, 72 }; 73 74 struct omap_dss_hwmod_data { 75 const char *oh_name; 76 const char *dev_name; 77 const int id; 78 }; 79 80 static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = { 81 { "dss_core", "omapdss_dss", -1 }, 82 { "dss_dispc", "omapdss_dispc", -1 }, 83 { "dss_rfbi", "omapdss_rfbi", -1 }, 84 { "dss_venc", "omapdss_venc", -1 }, 85 }; 86 87 static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = { 88 { "dss_core", "omapdss_dss", -1 }, 89 { "dss_dispc", "omapdss_dispc", -1 }, 90 { "dss_rfbi", "omapdss_rfbi", -1 }, 91 { "dss_venc", "omapdss_venc", -1 }, 92 { "dss_dsi1", "omapdss_dsi", 0 }, 93 }; 94 95 static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = { 96 { "dss_core", "omapdss_dss", -1 }, 97 { "dss_dispc", "omapdss_dispc", -1 }, 98 { "dss_rfbi", "omapdss_rfbi", -1 }, 99 { "dss_dsi1", "omapdss_dsi", 0 }, 100 { "dss_dsi2", "omapdss_dsi", 1 }, 101 { "dss_hdmi", "omapdss_hdmi", -1 }, 102 }; 103 104 static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask) 105 { 106 return 0; 107 } 108 109 static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask) 110 { 111 } 112 113 static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput) 114 { 115 return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput); 116 } 117 118 static struct platform_device *create_dss_pdev(const char *pdev_name, 119 int pdev_id, const char *oh_name, void *pdata, int pdata_len, 120 struct platform_device *parent) 121 { 122 struct platform_device *pdev; 123 struct omap_device *od; 124 struct omap_hwmod *ohs[1]; 125 struct omap_hwmod *oh; 126 int r; 127 128 oh = omap_hwmod_lookup(oh_name); 129 if (!oh) { 130 pr_err("Could not look up %s\n", oh_name); 131 r = -ENODEV; 132 goto err; 133 } 134 135 pdev = platform_device_alloc(pdev_name, pdev_id); 136 if (!pdev) { 137 pr_err("Could not create pdev for %s\n", pdev_name); 138 r = -ENOMEM; 139 goto err; 140 } 141 142 if (parent != NULL) 143 pdev->dev.parent = &parent->dev; 144 145 if (pdev->id != -1) 146 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id); 147 else 148 dev_set_name(&pdev->dev, "%s", pdev->name); 149 150 ohs[0] = oh; 151 od = omap_device_alloc(pdev, ohs, 1); 152 if (IS_ERR(od)) { 153 pr_err("Could not alloc omap_device for %s\n", pdev_name); 154 r = -ENOMEM; 155 goto err; 156 } 157 158 r = platform_device_add_data(pdev, pdata, pdata_len); 159 if (r) { 160 pr_err("Could not set pdata for %s\n", pdev_name); 161 goto err; 162 } 163 164 r = omap_device_register(pdev); 165 if (r) { 166 pr_err("Could not register omap_device for %s\n", pdev_name); 167 goto err; 168 } 169 170 return pdev; 171 172 err: 173 return ERR_PTR(r); 174 } 175 176 static struct platform_device *create_simple_dss_pdev(const char *pdev_name, 177 int pdev_id, void *pdata, int pdata_len, 178 struct platform_device *parent) 179 { 180 struct platform_device *pdev; 181 int r; 182 183 pdev = platform_device_alloc(pdev_name, pdev_id); 184 if (!pdev) { 185 pr_err("Could not create pdev for %s\n", pdev_name); 186 r = -ENOMEM; 187 goto err; 188 } 189 190 if (parent != NULL) 191 pdev->dev.parent = &parent->dev; 192 193 if (pdev->id != -1) 194 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id); 195 else 196 dev_set_name(&pdev->dev, "%s", pdev->name); 197 198 r = platform_device_add_data(pdev, pdata, pdata_len); 199 if (r) { 200 pr_err("Could not set pdata for %s\n", pdev_name); 201 goto err; 202 } 203 204 r = platform_device_add(pdev); 205 if (r) { 206 pr_err("Could not register platform_device for %s\n", pdev_name); 207 goto err; 208 } 209 210 return pdev; 211 212 err: 213 return ERR_PTR(r); 214 } 215 216 static enum omapdss_version __init omap_display_get_version(void) 217 { 218 if (cpu_is_omap24xx()) 219 return OMAPDSS_VER_OMAP24xx; 220 else if (cpu_is_omap3630()) 221 return OMAPDSS_VER_OMAP3630; 222 else if (cpu_is_omap34xx()) { 223 if (soc_is_am35xx()) { 224 return OMAPDSS_VER_AM35xx; 225 } else { 226 if (omap_rev() < OMAP3430_REV_ES3_0) 227 return OMAPDSS_VER_OMAP34xx_ES1; 228 else 229 return OMAPDSS_VER_OMAP34xx_ES3; 230 } 231 } else if (omap_rev() == OMAP4430_REV_ES1_0) 232 return OMAPDSS_VER_OMAP4430_ES1; 233 else if (omap_rev() == OMAP4430_REV_ES2_0 || 234 omap_rev() == OMAP4430_REV_ES2_1 || 235 omap_rev() == OMAP4430_REV_ES2_2) 236 return OMAPDSS_VER_OMAP4430_ES2; 237 else if (cpu_is_omap44xx()) 238 return OMAPDSS_VER_OMAP4; 239 else if (soc_is_omap54xx()) 240 return OMAPDSS_VER_OMAP5; 241 else 242 return OMAPDSS_VER_UNKNOWN; 243 } 244 245 int __init omap_display_init(struct omap_dss_board_info *board_data) 246 { 247 int r = 0; 248 struct platform_device *pdev; 249 int i, oh_count; 250 const struct omap_dss_hwmod_data *curr_dss_hwmod; 251 struct platform_device *dss_pdev; 252 enum omapdss_version ver; 253 254 /* create omapdss device */ 255 256 ver = omap_display_get_version(); 257 258 if (ver == OMAPDSS_VER_UNKNOWN) { 259 pr_err("DSS not supported on this SoC\n"); 260 return -ENODEV; 261 } 262 263 board_data->version = ver; 264 board_data->dsi_enable_pads = omap_dsi_enable_pads; 265 board_data->dsi_disable_pads = omap_dsi_disable_pads; 266 board_data->get_context_loss_count = omap_pm_get_dev_context_loss_count; 267 board_data->set_min_bus_tput = omap_dss_set_min_bus_tput; 268 269 omap_display_device.dev.platform_data = board_data; 270 271 r = platform_device_register(&omap_display_device); 272 if (r < 0) { 273 pr_err("Unable to register omapdss device\n"); 274 return r; 275 } 276 277 /* create devices for dss hwmods */ 278 279 if (cpu_is_omap24xx()) { 280 curr_dss_hwmod = omap2_dss_hwmod_data; 281 oh_count = ARRAY_SIZE(omap2_dss_hwmod_data); 282 } else if (cpu_is_omap34xx()) { 283 curr_dss_hwmod = omap3_dss_hwmod_data; 284 oh_count = ARRAY_SIZE(omap3_dss_hwmod_data); 285 } else { 286 curr_dss_hwmod = omap4_dss_hwmod_data; 287 oh_count = ARRAY_SIZE(omap4_dss_hwmod_data); 288 } 289 290 /* 291 * First create the pdev for dss_core, which is used as a parent device 292 * by the other dss pdevs. Note: dss_core has to be the first item in 293 * the hwmod list. 294 */ 295 dss_pdev = create_dss_pdev(curr_dss_hwmod[0].dev_name, 296 curr_dss_hwmod[0].id, 297 curr_dss_hwmod[0].oh_name, 298 board_data, sizeof(*board_data), 299 NULL); 300 301 if (IS_ERR(dss_pdev)) { 302 pr_err("Could not build omap_device for %s\n", 303 curr_dss_hwmod[0].oh_name); 304 305 return PTR_ERR(dss_pdev); 306 } 307 308 for (i = 1; i < oh_count; i++) { 309 pdev = create_dss_pdev(curr_dss_hwmod[i].dev_name, 310 curr_dss_hwmod[i].id, 311 curr_dss_hwmod[i].oh_name, 312 board_data, sizeof(*board_data), 313 dss_pdev); 314 315 if (IS_ERR(pdev)) { 316 pr_err("Could not build omap_device for %s\n", 317 curr_dss_hwmod[i].oh_name); 318 319 return PTR_ERR(pdev); 320 } 321 } 322 323 /* Create devices for DPI and SDI */ 324 325 pdev = create_simple_dss_pdev("omapdss_dpi", 0, 326 board_data, sizeof(*board_data), dss_pdev); 327 if (IS_ERR(pdev)) { 328 pr_err("Could not build platform_device for omapdss_dpi\n"); 329 return PTR_ERR(pdev); 330 } 331 332 if (cpu_is_omap34xx()) { 333 pdev = create_simple_dss_pdev("omapdss_sdi", 0, 334 board_data, sizeof(*board_data), dss_pdev); 335 if (IS_ERR(pdev)) { 336 pr_err("Could not build platform_device for omapdss_sdi\n"); 337 return PTR_ERR(pdev); 338 } 339 } 340 341 /* create DRM device */ 342 r = omap_init_drm(); 343 if (r < 0) { 344 pr_err("Unable to register omapdrm device\n"); 345 return r; 346 } 347 348 /* create vrfb device */ 349 r = omap_init_vrfb(); 350 if (r < 0) { 351 pr_err("Unable to register omapvrfb device\n"); 352 return r; 353 } 354 355 /* create FB device */ 356 r = omap_init_fb(); 357 if (r < 0) { 358 pr_err("Unable to register omapfb device\n"); 359 return r; 360 } 361 362 /* create V4L2 display device */ 363 r = omap_init_vout(); 364 if (r < 0) { 365 pr_err("Unable to register omap_vout device\n"); 366 return r; 367 } 368 369 return 0; 370 } 371 372 static void dispc_disable_outputs(void) 373 { 374 u32 v, irq_mask = 0; 375 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false; 376 int i; 377 struct omap_dss_dispc_dev_attr *da; 378 struct omap_hwmod *oh; 379 380 oh = omap_hwmod_lookup("dss_dispc"); 381 if (!oh) { 382 WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n"); 383 return; 384 } 385 386 if (!oh->dev_attr) { 387 pr_err("display: could not disable outputs during reset due to missing dev_attr\n"); 388 return; 389 } 390 391 da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr; 392 393 /* store value of LCDENABLE and DIGITENABLE bits */ 394 v = omap_hwmod_read(oh, DISPC_CONTROL); 395 lcd_en = v & LCD_EN_MASK; 396 digit_en = v & DIGIT_EN_MASK; 397 398 /* store value of LCDENABLE for LCD2 */ 399 if (da->manager_count > 2) { 400 v = omap_hwmod_read(oh, DISPC_CONTROL2); 401 lcd2_en = v & LCD_EN_MASK; 402 } 403 404 /* store value of LCDENABLE for LCD3 */ 405 if (da->manager_count > 3) { 406 v = omap_hwmod_read(oh, DISPC_CONTROL3); 407 lcd3_en = v & LCD_EN_MASK; 408 } 409 410 if (!(lcd_en | digit_en | lcd2_en | lcd3_en)) 411 return; /* no managers currently enabled */ 412 413 /* 414 * If any manager was enabled, we need to disable it before 415 * DSS clocks are disabled or DISPC module is reset 416 */ 417 if (lcd_en) 418 irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT; 419 420 if (digit_en) { 421 if (da->has_framedonetv_irq) { 422 irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT; 423 } else { 424 irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT | 425 1 << EVSYNC_ODD_IRQ_SHIFT; 426 } 427 } 428 429 if (lcd2_en) 430 irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT; 431 if (lcd3_en) 432 irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT; 433 434 /* 435 * clear any previous FRAMEDONE, FRAMEDONETV, 436 * EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts 437 */ 438 omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS); 439 440 /* disable LCD and TV managers */ 441 v = omap_hwmod_read(oh, DISPC_CONTROL); 442 v &= ~(LCD_EN_MASK | DIGIT_EN_MASK); 443 omap_hwmod_write(v, oh, DISPC_CONTROL); 444 445 /* disable LCD2 manager */ 446 if (da->manager_count > 2) { 447 v = omap_hwmod_read(oh, DISPC_CONTROL2); 448 v &= ~LCD_EN_MASK; 449 omap_hwmod_write(v, oh, DISPC_CONTROL2); 450 } 451 452 /* disable LCD3 manager */ 453 if (da->manager_count > 3) { 454 v = omap_hwmod_read(oh, DISPC_CONTROL3); 455 v &= ~LCD_EN_MASK; 456 omap_hwmod_write(v, oh, DISPC_CONTROL3); 457 } 458 459 i = 0; 460 while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) != 461 irq_mask) { 462 i++; 463 if (i > FRAMEDONE_IRQ_TIMEOUT) { 464 pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n"); 465 break; 466 } 467 mdelay(1); 468 } 469 } 470 471 int omap_dss_reset(struct omap_hwmod *oh) 472 { 473 struct omap_hwmod_opt_clk *oc; 474 int c = 0; 475 int i, r; 476 477 if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) { 478 pr_err("dss_core: hwmod data doesn't contain reset data\n"); 479 return -EINVAL; 480 } 481 482 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) 483 if (oc->_clk) 484 clk_prepare_enable(oc->_clk); 485 486 dispc_disable_outputs(); 487 488 /* clear SDI registers */ 489 if (cpu_is_omap3430()) { 490 omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL); 491 omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL); 492 } 493 494 /* 495 * clear DSS_CONTROL register to switch DSS clock sources to 496 * PRCM clock, if any 497 */ 498 omap_hwmod_write(0x0, oh, DSS_CONTROL); 499 500 omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs) 501 & SYSS_RESETDONE_MASK), 502 MAX_MODULE_SOFTRESET_WAIT, c); 503 504 if (c == MAX_MODULE_SOFTRESET_WAIT) 505 pr_warning("dss_core: waiting for reset to finish failed\n"); 506 else 507 pr_debug("dss_core: softreset done\n"); 508 509 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) 510 if (oc->_clk) 511 clk_disable_unprepare(oc->_clk); 512 513 r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; 514 515 return r; 516 } 517