1 /* 2 * OMAP2plus display device setup / initialization. 3 * 4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 5 * Senthilvadivu Guruswamy 6 * Sumit Semwal 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 13 * kind, whether express or implied; without even the implied warranty 14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/string.h> 19 #include <linux/kernel.h> 20 #include <linux/init.h> 21 #include <linux/platform_device.h> 22 #include <linux/io.h> 23 #include <linux/clk.h> 24 #include <linux/err.h> 25 #include <linux/delay.h> 26 #include <linux/of.h> 27 #include <linux/of_platform.h> 28 #include <linux/slab.h> 29 #include <linux/mfd/syscon.h> 30 #include <linux/regmap.h> 31 32 #include <linux/platform_data/omapdss.h> 33 #include "omap_hwmod.h" 34 #include "omap_device.h" 35 #include "omap-pm.h" 36 #include "common.h" 37 38 #include "soc.h" 39 #include "iomap.h" 40 #include "control.h" 41 #include "display.h" 42 #include "prm.h" 43 44 #define DISPC_CONTROL 0x0040 45 #define DISPC_CONTROL2 0x0238 46 #define DISPC_CONTROL3 0x0848 47 #define DISPC_IRQSTATUS 0x0018 48 49 #define DSS_CONTROL 0x40 50 #define DSS_SDI_CONTROL 0x44 51 #define DSS_PLL_CONTROL 0x48 52 53 #define LCD_EN_MASK (0x1 << 0) 54 #define DIGIT_EN_MASK (0x1 << 1) 55 56 #define FRAMEDONE_IRQ_SHIFT 0 57 #define EVSYNC_EVEN_IRQ_SHIFT 2 58 #define EVSYNC_ODD_IRQ_SHIFT 3 59 #define FRAMEDONE2_IRQ_SHIFT 22 60 #define FRAMEDONE3_IRQ_SHIFT 30 61 #define FRAMEDONETV_IRQ_SHIFT 24 62 63 /* 64 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC 65 * reset before deciding that something has gone wrong 66 */ 67 #define FRAMEDONE_IRQ_TIMEOUT 100 68 69 #if defined(CONFIG_FB_OMAP2) 70 static struct platform_device omap_display_device = { 71 .name = "omapdss", 72 .id = -1, 73 .dev = { 74 .platform_data = NULL, 75 }, 76 }; 77 78 #define OMAP4_DSIPHY_SYSCON_OFFSET 0x78 79 80 static struct regmap *omap4_dsi_mux_syscon; 81 82 static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes) 83 { 84 u32 enable_mask, enable_shift; 85 u32 pipd_mask, pipd_shift; 86 u32 reg; 87 88 if (dsi_id == 0) { 89 enable_mask = OMAP4_DSI1_LANEENABLE_MASK; 90 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT; 91 pipd_mask = OMAP4_DSI1_PIPD_MASK; 92 pipd_shift = OMAP4_DSI1_PIPD_SHIFT; 93 } else if (dsi_id == 1) { 94 enable_mask = OMAP4_DSI2_LANEENABLE_MASK; 95 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT; 96 pipd_mask = OMAP4_DSI2_PIPD_MASK; 97 pipd_shift = OMAP4_DSI2_PIPD_SHIFT; 98 } else { 99 return -ENODEV; 100 } 101 102 regmap_read(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, ®); 103 104 reg &= ~enable_mask; 105 reg &= ~pipd_mask; 106 107 reg |= (lanes << enable_shift) & enable_mask; 108 reg |= (lanes << pipd_shift) & pipd_mask; 109 110 regmap_write(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, reg); 111 112 return 0; 113 } 114 115 static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask) 116 { 117 if (cpu_is_omap44xx()) 118 return omap4_dsi_mux_pads(dsi_id, lane_mask); 119 120 return 0; 121 } 122 123 static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask) 124 { 125 if (cpu_is_omap44xx()) 126 omap4_dsi_mux_pads(dsi_id, 0); 127 } 128 129 static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput) 130 { 131 return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput); 132 } 133 134 static enum omapdss_version __init omap_display_get_version(void) 135 { 136 if (cpu_is_omap24xx()) 137 return OMAPDSS_VER_OMAP24xx; 138 else if (cpu_is_omap3630()) 139 return OMAPDSS_VER_OMAP3630; 140 else if (cpu_is_omap34xx()) { 141 if (soc_is_am35xx()) { 142 return OMAPDSS_VER_AM35xx; 143 } else { 144 if (omap_rev() < OMAP3430_REV_ES3_0) 145 return OMAPDSS_VER_OMAP34xx_ES1; 146 else 147 return OMAPDSS_VER_OMAP34xx_ES3; 148 } 149 } else if (omap_rev() == OMAP4430_REV_ES1_0) 150 return OMAPDSS_VER_OMAP4430_ES1; 151 else if (omap_rev() == OMAP4430_REV_ES2_0 || 152 omap_rev() == OMAP4430_REV_ES2_1 || 153 omap_rev() == OMAP4430_REV_ES2_2) 154 return OMAPDSS_VER_OMAP4430_ES2; 155 else if (cpu_is_omap44xx()) 156 return OMAPDSS_VER_OMAP4; 157 else if (soc_is_omap54xx()) 158 return OMAPDSS_VER_OMAP5; 159 else if (soc_is_am43xx()) 160 return OMAPDSS_VER_AM43xx; 161 else if (soc_is_dra7xx()) 162 return OMAPDSS_VER_DRA7xx; 163 else 164 return OMAPDSS_VER_UNKNOWN; 165 } 166 167 static int __init omapdss_init_fbdev(void) 168 { 169 static struct omap_dss_board_info board_data = { 170 .dsi_enable_pads = omap_dsi_enable_pads, 171 .dsi_disable_pads = omap_dsi_disable_pads, 172 .set_min_bus_tput = omap_dss_set_min_bus_tput, 173 }; 174 struct device_node *node; 175 int r; 176 177 board_data.version = omap_display_get_version(); 178 if (board_data.version == OMAPDSS_VER_UNKNOWN) { 179 pr_err("DSS not supported on this SoC\n"); 180 return -ENODEV; 181 } 182 183 omap_display_device.dev.platform_data = &board_data; 184 185 r = platform_device_register(&omap_display_device); 186 if (r < 0) { 187 pr_err("Unable to register omapdss device\n"); 188 return r; 189 } 190 191 /* create vrfb device */ 192 r = omap_init_vrfb(); 193 if (r < 0) { 194 pr_err("Unable to register omapvrfb device\n"); 195 return r; 196 } 197 198 /* create FB device */ 199 r = omap_init_fb(); 200 if (r < 0) { 201 pr_err("Unable to register omapfb device\n"); 202 return r; 203 } 204 205 /* create V4L2 display device */ 206 r = omap_init_vout(); 207 if (r < 0) { 208 pr_err("Unable to register omap_vout device\n"); 209 return r; 210 } 211 212 /* add DSI info for omap4 */ 213 node = of_find_node_by_name(NULL, "omap4_padconf_global"); 214 if (node) 215 omap4_dsi_mux_syscon = syscon_node_to_regmap(node); 216 217 return 0; 218 } 219 #else 220 static inline int omapdss_init_fbdev(void) 221 { 222 return 0; 223 } 224 #endif /* CONFIG_FB_OMAP2 */ 225 226 static void dispc_disable_outputs(void) 227 { 228 u32 v, irq_mask = 0; 229 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false; 230 int i; 231 struct omap_dss_dispc_dev_attr *da; 232 struct omap_hwmod *oh; 233 234 oh = omap_hwmod_lookup("dss_dispc"); 235 if (!oh) { 236 WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n"); 237 return; 238 } 239 240 if (!oh->dev_attr) { 241 pr_err("display: could not disable outputs during reset due to missing dev_attr\n"); 242 return; 243 } 244 245 da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr; 246 247 /* store value of LCDENABLE and DIGITENABLE bits */ 248 v = omap_hwmod_read(oh, DISPC_CONTROL); 249 lcd_en = v & LCD_EN_MASK; 250 digit_en = v & DIGIT_EN_MASK; 251 252 /* store value of LCDENABLE for LCD2 */ 253 if (da->manager_count > 2) { 254 v = omap_hwmod_read(oh, DISPC_CONTROL2); 255 lcd2_en = v & LCD_EN_MASK; 256 } 257 258 /* store value of LCDENABLE for LCD3 */ 259 if (da->manager_count > 3) { 260 v = omap_hwmod_read(oh, DISPC_CONTROL3); 261 lcd3_en = v & LCD_EN_MASK; 262 } 263 264 if (!(lcd_en | digit_en | lcd2_en | lcd3_en)) 265 return; /* no managers currently enabled */ 266 267 /* 268 * If any manager was enabled, we need to disable it before 269 * DSS clocks are disabled or DISPC module is reset 270 */ 271 if (lcd_en) 272 irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT; 273 274 if (digit_en) { 275 if (da->has_framedonetv_irq) { 276 irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT; 277 } else { 278 irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT | 279 1 << EVSYNC_ODD_IRQ_SHIFT; 280 } 281 } 282 283 if (lcd2_en) 284 irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT; 285 if (lcd3_en) 286 irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT; 287 288 /* 289 * clear any previous FRAMEDONE, FRAMEDONETV, 290 * EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts 291 */ 292 omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS); 293 294 /* disable LCD and TV managers */ 295 v = omap_hwmod_read(oh, DISPC_CONTROL); 296 v &= ~(LCD_EN_MASK | DIGIT_EN_MASK); 297 omap_hwmod_write(v, oh, DISPC_CONTROL); 298 299 /* disable LCD2 manager */ 300 if (da->manager_count > 2) { 301 v = omap_hwmod_read(oh, DISPC_CONTROL2); 302 v &= ~LCD_EN_MASK; 303 omap_hwmod_write(v, oh, DISPC_CONTROL2); 304 } 305 306 /* disable LCD3 manager */ 307 if (da->manager_count > 3) { 308 v = omap_hwmod_read(oh, DISPC_CONTROL3); 309 v &= ~LCD_EN_MASK; 310 omap_hwmod_write(v, oh, DISPC_CONTROL3); 311 } 312 313 i = 0; 314 while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) != 315 irq_mask) { 316 i++; 317 if (i > FRAMEDONE_IRQ_TIMEOUT) { 318 pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n"); 319 break; 320 } 321 mdelay(1); 322 } 323 } 324 325 int omap_dss_reset(struct omap_hwmod *oh) 326 { 327 struct omap_hwmod_opt_clk *oc; 328 int c = 0; 329 int i, r; 330 331 if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) { 332 pr_err("dss_core: hwmod data doesn't contain reset data\n"); 333 return -EINVAL; 334 } 335 336 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) 337 if (oc->_clk) 338 clk_prepare_enable(oc->_clk); 339 340 dispc_disable_outputs(); 341 342 /* clear SDI registers */ 343 if (cpu_is_omap3430()) { 344 omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL); 345 omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL); 346 } 347 348 /* 349 * clear DSS_CONTROL register to switch DSS clock sources to 350 * PRCM clock, if any 351 */ 352 omap_hwmod_write(0x0, oh, DSS_CONTROL); 353 354 omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs) 355 & SYSS_RESETDONE_MASK), 356 MAX_MODULE_SOFTRESET_WAIT, c); 357 358 if (c == MAX_MODULE_SOFTRESET_WAIT) 359 pr_warn("dss_core: waiting for reset to finish failed\n"); 360 else 361 pr_debug("dss_core: softreset done\n"); 362 363 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) 364 if (oc->_clk) 365 clk_disable_unprepare(oc->_clk); 366 367 r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; 368 369 return r; 370 } 371 372 static const char * const omapdss_compat_names[] __initconst = { 373 "ti,omap2-dss", 374 "ti,omap3-dss", 375 "ti,omap4-dss", 376 "ti,omap5-dss", 377 "ti,dra7-dss", 378 }; 379 380 static struct device_node * __init omapdss_find_dss_of_node(void) 381 { 382 struct device_node *node; 383 int i; 384 385 for (i = 0; i < ARRAY_SIZE(omapdss_compat_names); ++i) { 386 node = of_find_compatible_node(NULL, NULL, 387 omapdss_compat_names[i]); 388 if (node) 389 return node; 390 } 391 392 return NULL; 393 } 394 395 int __init omapdss_init_of(void) 396 { 397 int r; 398 struct device_node *node; 399 struct platform_device *pdev; 400 401 /* only create dss helper devices if dss is enabled in the .dts */ 402 403 node = omapdss_find_dss_of_node(); 404 if (!node) 405 return 0; 406 407 if (!of_device_is_available(node)) 408 return 0; 409 410 pdev = of_find_device_by_node(node); 411 412 if (!pdev) { 413 pr_err("Unable to find DSS platform device\n"); 414 return -ENODEV; 415 } 416 417 r = of_platform_populate(node, NULL, NULL, &pdev->dev); 418 if (r) { 419 pr_err("Unable to populate DSS submodule devices\n"); 420 return r; 421 } 422 423 return omapdss_init_fbdev(); 424 } 425