1 /* 2 * OMAP2plus display device setup / initialization. 3 * 4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 5 * Senthilvadivu Guruswamy 6 * Sumit Semwal 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 13 * kind, whether express or implied; without even the implied warranty 14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/string.h> 19 #include <linux/kernel.h> 20 #include <linux/init.h> 21 #include <linux/platform_device.h> 22 #include <linux/io.h> 23 #include <linux/clk.h> 24 #include <linux/err.h> 25 #include <linux/delay.h> 26 #include <linux/of.h> 27 #include <linux/of_platform.h> 28 #include <linux/slab.h> 29 30 #include <video/omapdss.h> 31 #include "omap_hwmod.h" 32 #include "omap_device.h" 33 #include "omap-pm.h" 34 #include "common.h" 35 36 #include "soc.h" 37 #include "iomap.h" 38 #include "control.h" 39 #include "display.h" 40 #include "prm.h" 41 42 #define DISPC_CONTROL 0x0040 43 #define DISPC_CONTROL2 0x0238 44 #define DISPC_CONTROL3 0x0848 45 #define DISPC_IRQSTATUS 0x0018 46 47 #define DSS_SYSCONFIG 0x10 48 #define DSS_SYSSTATUS 0x14 49 #define DSS_CONTROL 0x40 50 #define DSS_SDI_CONTROL 0x44 51 #define DSS_PLL_CONTROL 0x48 52 53 #define LCD_EN_MASK (0x1 << 0) 54 #define DIGIT_EN_MASK (0x1 << 1) 55 56 #define FRAMEDONE_IRQ_SHIFT 0 57 #define EVSYNC_EVEN_IRQ_SHIFT 2 58 #define EVSYNC_ODD_IRQ_SHIFT 3 59 #define FRAMEDONE2_IRQ_SHIFT 22 60 #define FRAMEDONE3_IRQ_SHIFT 30 61 #define FRAMEDONETV_IRQ_SHIFT 24 62 63 /* 64 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC 65 * reset before deciding that something has gone wrong 66 */ 67 #define FRAMEDONE_IRQ_TIMEOUT 100 68 69 static struct platform_device omap_display_device = { 70 .name = "omapdss", 71 .id = -1, 72 .dev = { 73 .platform_data = NULL, 74 }, 75 }; 76 77 struct omap_dss_hwmod_data { 78 const char *oh_name; 79 const char *dev_name; 80 const int id; 81 }; 82 83 static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = { 84 { "dss_core", "omapdss_dss", -1 }, 85 { "dss_dispc", "omapdss_dispc", -1 }, 86 { "dss_rfbi", "omapdss_rfbi", -1 }, 87 { "dss_venc", "omapdss_venc", -1 }, 88 }; 89 90 static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = { 91 { "dss_core", "omapdss_dss", -1 }, 92 { "dss_dispc", "omapdss_dispc", -1 }, 93 { "dss_rfbi", "omapdss_rfbi", -1 }, 94 { "dss_venc", "omapdss_venc", -1 }, 95 { "dss_dsi1", "omapdss_dsi", 0 }, 96 }; 97 98 static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = { 99 { "dss_core", "omapdss_dss", -1 }, 100 { "dss_dispc", "omapdss_dispc", -1 }, 101 { "dss_rfbi", "omapdss_rfbi", -1 }, 102 { "dss_dsi1", "omapdss_dsi", 0 }, 103 { "dss_dsi2", "omapdss_dsi", 1 }, 104 { "dss_hdmi", "omapdss_hdmi", -1 }, 105 }; 106 107 static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes) 108 { 109 u32 enable_mask, enable_shift; 110 u32 pipd_mask, pipd_shift; 111 u32 reg; 112 113 if (dsi_id == 0) { 114 enable_mask = OMAP4_DSI1_LANEENABLE_MASK; 115 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT; 116 pipd_mask = OMAP4_DSI1_PIPD_MASK; 117 pipd_shift = OMAP4_DSI1_PIPD_SHIFT; 118 } else if (dsi_id == 1) { 119 enable_mask = OMAP4_DSI2_LANEENABLE_MASK; 120 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT; 121 pipd_mask = OMAP4_DSI2_PIPD_MASK; 122 pipd_shift = OMAP4_DSI2_PIPD_SHIFT; 123 } else { 124 return -ENODEV; 125 } 126 127 reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY); 128 129 reg &= ~enable_mask; 130 reg &= ~pipd_mask; 131 132 reg |= (lanes << enable_shift) & enable_mask; 133 reg |= (lanes << pipd_shift) & pipd_mask; 134 135 omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY); 136 137 return 0; 138 } 139 140 static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask) 141 { 142 if (cpu_is_omap44xx()) 143 return omap4_dsi_mux_pads(dsi_id, lane_mask); 144 145 return 0; 146 } 147 148 static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask) 149 { 150 if (cpu_is_omap44xx()) 151 omap4_dsi_mux_pads(dsi_id, 0); 152 } 153 154 static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput) 155 { 156 return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput); 157 } 158 159 static struct platform_device *create_dss_pdev(const char *pdev_name, 160 int pdev_id, const char *oh_name, void *pdata, int pdata_len, 161 struct platform_device *parent) 162 { 163 struct platform_device *pdev; 164 struct omap_device *od; 165 struct omap_hwmod *ohs[1]; 166 struct omap_hwmod *oh; 167 int r; 168 169 oh = omap_hwmod_lookup(oh_name); 170 if (!oh) { 171 pr_err("Could not look up %s\n", oh_name); 172 r = -ENODEV; 173 goto err; 174 } 175 176 pdev = platform_device_alloc(pdev_name, pdev_id); 177 if (!pdev) { 178 pr_err("Could not create pdev for %s\n", pdev_name); 179 r = -ENOMEM; 180 goto err; 181 } 182 183 if (parent != NULL) 184 pdev->dev.parent = &parent->dev; 185 186 if (pdev->id != -1) 187 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id); 188 else 189 dev_set_name(&pdev->dev, "%s", pdev->name); 190 191 ohs[0] = oh; 192 od = omap_device_alloc(pdev, ohs, 1); 193 if (IS_ERR(od)) { 194 pr_err("Could not alloc omap_device for %s\n", pdev_name); 195 r = -ENOMEM; 196 goto err; 197 } 198 199 r = platform_device_add_data(pdev, pdata, pdata_len); 200 if (r) { 201 pr_err("Could not set pdata for %s\n", pdev_name); 202 goto err; 203 } 204 205 r = omap_device_register(pdev); 206 if (r) { 207 pr_err("Could not register omap_device for %s\n", pdev_name); 208 goto err; 209 } 210 211 return pdev; 212 213 err: 214 return ERR_PTR(r); 215 } 216 217 static struct platform_device *create_simple_dss_pdev(const char *pdev_name, 218 int pdev_id, void *pdata, int pdata_len, 219 struct platform_device *parent) 220 { 221 struct platform_device *pdev; 222 int r; 223 224 pdev = platform_device_alloc(pdev_name, pdev_id); 225 if (!pdev) { 226 pr_err("Could not create pdev for %s\n", pdev_name); 227 r = -ENOMEM; 228 goto err; 229 } 230 231 if (parent != NULL) 232 pdev->dev.parent = &parent->dev; 233 234 if (pdev->id != -1) 235 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id); 236 else 237 dev_set_name(&pdev->dev, "%s", pdev->name); 238 239 r = platform_device_add_data(pdev, pdata, pdata_len); 240 if (r) { 241 pr_err("Could not set pdata for %s\n", pdev_name); 242 goto err; 243 } 244 245 r = platform_device_add(pdev); 246 if (r) { 247 pr_err("Could not register platform_device for %s\n", pdev_name); 248 goto err; 249 } 250 251 return pdev; 252 253 err: 254 return ERR_PTR(r); 255 } 256 257 static enum omapdss_version __init omap_display_get_version(void) 258 { 259 if (cpu_is_omap24xx()) 260 return OMAPDSS_VER_OMAP24xx; 261 else if (cpu_is_omap3630()) 262 return OMAPDSS_VER_OMAP3630; 263 else if (cpu_is_omap34xx()) { 264 if (soc_is_am35xx()) { 265 return OMAPDSS_VER_AM35xx; 266 } else { 267 if (omap_rev() < OMAP3430_REV_ES3_0) 268 return OMAPDSS_VER_OMAP34xx_ES1; 269 else 270 return OMAPDSS_VER_OMAP34xx_ES3; 271 } 272 } else if (omap_rev() == OMAP4430_REV_ES1_0) 273 return OMAPDSS_VER_OMAP4430_ES1; 274 else if (omap_rev() == OMAP4430_REV_ES2_0 || 275 omap_rev() == OMAP4430_REV_ES2_1 || 276 omap_rev() == OMAP4430_REV_ES2_2) 277 return OMAPDSS_VER_OMAP4430_ES2; 278 else if (cpu_is_omap44xx()) 279 return OMAPDSS_VER_OMAP4; 280 else if (soc_is_omap54xx()) 281 return OMAPDSS_VER_OMAP5; 282 else 283 return OMAPDSS_VER_UNKNOWN; 284 } 285 286 int __init omap_display_init(struct omap_dss_board_info *board_data) 287 { 288 int r = 0; 289 struct platform_device *pdev; 290 int i, oh_count; 291 const struct omap_dss_hwmod_data *curr_dss_hwmod; 292 struct platform_device *dss_pdev; 293 enum omapdss_version ver; 294 295 /* create omapdss device */ 296 297 ver = omap_display_get_version(); 298 299 if (ver == OMAPDSS_VER_UNKNOWN) { 300 pr_err("DSS not supported on this SoC\n"); 301 return -ENODEV; 302 } 303 304 board_data->version = ver; 305 board_data->dsi_enable_pads = omap_dsi_enable_pads; 306 board_data->dsi_disable_pads = omap_dsi_disable_pads; 307 board_data->set_min_bus_tput = omap_dss_set_min_bus_tput; 308 309 omap_display_device.dev.platform_data = board_data; 310 311 r = platform_device_register(&omap_display_device); 312 if (r < 0) { 313 pr_err("Unable to register omapdss device\n"); 314 return r; 315 } 316 317 /* create devices for dss hwmods */ 318 319 if (cpu_is_omap24xx()) { 320 curr_dss_hwmod = omap2_dss_hwmod_data; 321 oh_count = ARRAY_SIZE(omap2_dss_hwmod_data); 322 } else if (cpu_is_omap34xx()) { 323 curr_dss_hwmod = omap3_dss_hwmod_data; 324 oh_count = ARRAY_SIZE(omap3_dss_hwmod_data); 325 } else { 326 curr_dss_hwmod = omap4_dss_hwmod_data; 327 oh_count = ARRAY_SIZE(omap4_dss_hwmod_data); 328 } 329 330 /* 331 * First create the pdev for dss_core, which is used as a parent device 332 * by the other dss pdevs. Note: dss_core has to be the first item in 333 * the hwmod list. 334 */ 335 dss_pdev = create_dss_pdev(curr_dss_hwmod[0].dev_name, 336 curr_dss_hwmod[0].id, 337 curr_dss_hwmod[0].oh_name, 338 board_data, sizeof(*board_data), 339 NULL); 340 341 if (IS_ERR(dss_pdev)) { 342 pr_err("Could not build omap_device for %s\n", 343 curr_dss_hwmod[0].oh_name); 344 345 return PTR_ERR(dss_pdev); 346 } 347 348 for (i = 1; i < oh_count; i++) { 349 pdev = create_dss_pdev(curr_dss_hwmod[i].dev_name, 350 curr_dss_hwmod[i].id, 351 curr_dss_hwmod[i].oh_name, 352 board_data, sizeof(*board_data), 353 dss_pdev); 354 355 if (IS_ERR(pdev)) { 356 pr_err("Could not build omap_device for %s\n", 357 curr_dss_hwmod[i].oh_name); 358 359 return PTR_ERR(pdev); 360 } 361 } 362 363 /* Create devices for DPI and SDI */ 364 365 pdev = create_simple_dss_pdev("omapdss_dpi", 0, 366 board_data, sizeof(*board_data), dss_pdev); 367 if (IS_ERR(pdev)) { 368 pr_err("Could not build platform_device for omapdss_dpi\n"); 369 return PTR_ERR(pdev); 370 } 371 372 if (cpu_is_omap34xx()) { 373 pdev = create_simple_dss_pdev("omapdss_sdi", 0, 374 board_data, sizeof(*board_data), dss_pdev); 375 if (IS_ERR(pdev)) { 376 pr_err("Could not build platform_device for omapdss_sdi\n"); 377 return PTR_ERR(pdev); 378 } 379 } 380 381 /* create DRM device */ 382 r = omap_init_drm(); 383 if (r < 0) { 384 pr_err("Unable to register omapdrm device\n"); 385 return r; 386 } 387 388 /* create vrfb device */ 389 r = omap_init_vrfb(); 390 if (r < 0) { 391 pr_err("Unable to register omapvrfb device\n"); 392 return r; 393 } 394 395 /* create FB device */ 396 r = omap_init_fb(); 397 if (r < 0) { 398 pr_err("Unable to register omapfb device\n"); 399 return r; 400 } 401 402 /* create V4L2 display device */ 403 r = omap_init_vout(); 404 if (r < 0) { 405 pr_err("Unable to register omap_vout device\n"); 406 return r; 407 } 408 409 return 0; 410 } 411 412 static void dispc_disable_outputs(void) 413 { 414 u32 v, irq_mask = 0; 415 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false; 416 int i; 417 struct omap_dss_dispc_dev_attr *da; 418 struct omap_hwmod *oh; 419 420 oh = omap_hwmod_lookup("dss_dispc"); 421 if (!oh) { 422 WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n"); 423 return; 424 } 425 426 if (!oh->dev_attr) { 427 pr_err("display: could not disable outputs during reset due to missing dev_attr\n"); 428 return; 429 } 430 431 da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr; 432 433 /* store value of LCDENABLE and DIGITENABLE bits */ 434 v = omap_hwmod_read(oh, DISPC_CONTROL); 435 lcd_en = v & LCD_EN_MASK; 436 digit_en = v & DIGIT_EN_MASK; 437 438 /* store value of LCDENABLE for LCD2 */ 439 if (da->manager_count > 2) { 440 v = omap_hwmod_read(oh, DISPC_CONTROL2); 441 lcd2_en = v & LCD_EN_MASK; 442 } 443 444 /* store value of LCDENABLE for LCD3 */ 445 if (da->manager_count > 3) { 446 v = omap_hwmod_read(oh, DISPC_CONTROL3); 447 lcd3_en = v & LCD_EN_MASK; 448 } 449 450 if (!(lcd_en | digit_en | lcd2_en | lcd3_en)) 451 return; /* no managers currently enabled */ 452 453 /* 454 * If any manager was enabled, we need to disable it before 455 * DSS clocks are disabled or DISPC module is reset 456 */ 457 if (lcd_en) 458 irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT; 459 460 if (digit_en) { 461 if (da->has_framedonetv_irq) { 462 irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT; 463 } else { 464 irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT | 465 1 << EVSYNC_ODD_IRQ_SHIFT; 466 } 467 } 468 469 if (lcd2_en) 470 irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT; 471 if (lcd3_en) 472 irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT; 473 474 /* 475 * clear any previous FRAMEDONE, FRAMEDONETV, 476 * EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts 477 */ 478 omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS); 479 480 /* disable LCD and TV managers */ 481 v = omap_hwmod_read(oh, DISPC_CONTROL); 482 v &= ~(LCD_EN_MASK | DIGIT_EN_MASK); 483 omap_hwmod_write(v, oh, DISPC_CONTROL); 484 485 /* disable LCD2 manager */ 486 if (da->manager_count > 2) { 487 v = omap_hwmod_read(oh, DISPC_CONTROL2); 488 v &= ~LCD_EN_MASK; 489 omap_hwmod_write(v, oh, DISPC_CONTROL2); 490 } 491 492 /* disable LCD3 manager */ 493 if (da->manager_count > 3) { 494 v = omap_hwmod_read(oh, DISPC_CONTROL3); 495 v &= ~LCD_EN_MASK; 496 omap_hwmod_write(v, oh, DISPC_CONTROL3); 497 } 498 499 i = 0; 500 while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) != 501 irq_mask) { 502 i++; 503 if (i > FRAMEDONE_IRQ_TIMEOUT) { 504 pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n"); 505 break; 506 } 507 mdelay(1); 508 } 509 } 510 511 int omap_dss_reset(struct omap_hwmod *oh) 512 { 513 struct omap_hwmod_opt_clk *oc; 514 int c = 0; 515 int i, r; 516 517 if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) { 518 pr_err("dss_core: hwmod data doesn't contain reset data\n"); 519 return -EINVAL; 520 } 521 522 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) 523 if (oc->_clk) 524 clk_prepare_enable(oc->_clk); 525 526 dispc_disable_outputs(); 527 528 /* clear SDI registers */ 529 if (cpu_is_omap3430()) { 530 omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL); 531 omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL); 532 } 533 534 /* 535 * clear DSS_CONTROL register to switch DSS clock sources to 536 * PRCM clock, if any 537 */ 538 omap_hwmod_write(0x0, oh, DSS_CONTROL); 539 540 omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs) 541 & SYSS_RESETDONE_MASK), 542 MAX_MODULE_SOFTRESET_WAIT, c); 543 544 if (c == MAX_MODULE_SOFTRESET_WAIT) 545 pr_warning("dss_core: waiting for reset to finish failed\n"); 546 else 547 pr_debug("dss_core: softreset done\n"); 548 549 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) 550 if (oc->_clk) 551 clk_disable_unprepare(oc->_clk); 552 553 r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; 554 555 return r; 556 } 557 558 /* list of 'compatible' nodes to convert to omapdss specific */ 559 static const char * const dss_compat_conv_list[] __initconst = { 560 "composite-connector", 561 "dvi-connector", 562 "hdmi-connector", 563 "panel-dpi", 564 "panel-dsi-cm", 565 "sony,acx565akm", 566 "svideo-connector", 567 "ti,tfp410", 568 "ti,tpd12s015", 569 }; 570 571 /* prepend compatible string with "omapdss," */ 572 static __init void omapdss_omapify_node(struct device_node *node, 573 const char *compat) 574 { 575 char *new_compat; 576 struct property *prop; 577 578 new_compat = kasprintf(GFP_KERNEL, "omapdss,%s", compat); 579 580 prop = kzalloc(sizeof(*prop), GFP_KERNEL); 581 582 if (!prop) { 583 pr_err("omapdss_omapify_node: kzalloc failed\n"); 584 return; 585 } 586 587 prop->name = "compatible"; 588 prop->value = new_compat; 589 prop->length = strlen(new_compat) + 1; 590 591 of_update_property(node, prop); 592 } 593 594 /* 595 * As omapdss panel drivers are omapdss specific, but we want to define the 596 * DT-data in generic manner, we convert the compatible strings of the panel 597 * nodes from "panel-foo" to "omapdss,panel-foo". This way we can have both 598 * correct DT data and omapdss specific drivers. 599 * 600 * When we get generic panel drivers to the kernel, this will be removed. 601 */ 602 void __init omapdss_early_init_of(void) 603 { 604 int i; 605 606 for (i = 0; i < ARRAY_SIZE(dss_compat_conv_list); ++i) { 607 const char *compat = dss_compat_conv_list[i]; 608 struct device_node *node = NULL; 609 610 while ((node = of_find_compatible_node(node, NULL, compat))) { 611 if (!of_device_is_available(node)) 612 continue; 613 614 omapdss_omapify_node(node, compat); 615 } 616 } 617 } 618 619 struct device_node * __init omapdss_find_dss_of_node(void) 620 { 621 struct device_node *node; 622 623 node = of_find_compatible_node(NULL, NULL, "ti,omap2-dss"); 624 if (node) 625 return node; 626 627 node = of_find_compatible_node(NULL, NULL, "ti,omap3-dss"); 628 if (node) 629 return node; 630 631 node = of_find_compatible_node(NULL, NULL, "ti,omap4-dss"); 632 if (node) 633 return node; 634 635 return NULL; 636 } 637 638 int __init omapdss_init_of(void) 639 { 640 int r; 641 enum omapdss_version ver; 642 struct device_node *node; 643 struct platform_device *pdev; 644 645 static struct omap_dss_board_info board_data = { 646 .dsi_enable_pads = omap_dsi_enable_pads, 647 .dsi_disable_pads = omap_dsi_disable_pads, 648 .set_min_bus_tput = omap_dss_set_min_bus_tput, 649 }; 650 651 /* only create dss helper devices if dss is enabled in the .dts */ 652 653 node = omapdss_find_dss_of_node(); 654 if (!node) 655 return 0; 656 657 if (!of_device_is_available(node)) 658 return 0; 659 660 ver = omap_display_get_version(); 661 662 if (ver == OMAPDSS_VER_UNKNOWN) { 663 pr_err("DSS not supported on this SoC\n"); 664 return -ENODEV; 665 } 666 667 pdev = of_find_device_by_node(node); 668 669 if (!pdev) { 670 pr_err("Unable to find DSS platform device\n"); 671 return -ENODEV; 672 } 673 674 r = of_platform_populate(node, NULL, NULL, &pdev->dev); 675 if (r) { 676 pr_err("Unable to populate DSS submodule devices\n"); 677 return r; 678 } 679 680 board_data.version = ver; 681 682 omap_display_device.dev.platform_data = &board_data; 683 684 r = platform_device_register(&omap_display_device); 685 if (r < 0) { 686 pr_err("Unable to register omapdss device\n"); 687 return r; 688 } 689 690 /* create DRM device */ 691 r = omap_init_drm(); 692 if (r < 0) { 693 pr_err("Unable to register omapdrm device\n"); 694 return r; 695 } 696 697 /* create vrfb device */ 698 r = omap_init_vrfb(); 699 if (r < 0) { 700 pr_err("Unable to register omapvrfb device\n"); 701 return r; 702 } 703 704 /* create FB device */ 705 r = omap_init_fb(); 706 if (r < 0) { 707 pr_err("Unable to register omapfb device\n"); 708 return r; 709 } 710 711 /* create V4L2 display device */ 712 r = omap_init_vout(); 713 if (r < 0) { 714 pr_err("Unable to register omap_vout device\n"); 715 return r; 716 } 717 718 return 0; 719 } 720