xref: /openbmc/linux/arch/arm/mach-omap2/control.c (revision d7a3d85e)
1 /*
2  * OMAP2/3 System Control Module register access
3  *
4  * Copyright (C) 2007, 2012 Texas Instruments, Inc.
5  * Copyright (C) 2007 Nokia Corporation
6  *
7  * Written by Paul Walmsley
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  */
13 #undef DEBUG
14 
15 #include <linux/kernel.h>
16 #include <linux/io.h>
17 #include <linux/of_address.h>
18 #include <linux/regmap.h>
19 #include <linux/mfd/syscon.h>
20 
21 #include "soc.h"
22 #include "iomap.h"
23 #include "common.h"
24 #include "cm-regbits-34xx.h"
25 #include "prm-regbits-34xx.h"
26 #include "prm3xxx.h"
27 #include "cm3xxx.h"
28 #include "sdrc.h"
29 #include "pm.h"
30 #include "control.h"
31 #include "clock.h"
32 
33 /* Used by omap3_ctrl_save_padconf() */
34 #define START_PADCONF_SAVE		0x2
35 #define PADCONF_SAVE_DONE		0x1
36 
37 static void __iomem *omap2_ctrl_base;
38 static s16 omap2_ctrl_offset;
39 static struct regmap *omap2_ctrl_syscon;
40 
41 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
42 struct omap3_scratchpad {
43 	u32 boot_config_ptr;
44 	u32 public_restore_ptr;
45 	u32 secure_ram_restore_ptr;
46 	u32 sdrc_module_semaphore;
47 	u32 prcm_block_offset;
48 	u32 sdrc_block_offset;
49 };
50 
51 struct omap3_scratchpad_prcm_block {
52 	u32 prm_contents[2];
53 	u32 cm_contents[11];
54 	u32 prcm_block_size;
55 };
56 
57 struct omap3_scratchpad_sdrc_block {
58 	u16 sysconfig;
59 	u16 cs_cfg;
60 	u16 sharing;
61 	u16 err_type;
62 	u32 dll_a_ctrl;
63 	u32 dll_b_ctrl;
64 	u32 power;
65 	u32 cs_0;
66 	u32 mcfg_0;
67 	u16 mr_0;
68 	u16 emr_1_0;
69 	u16 emr_2_0;
70 	u16 emr_3_0;
71 	u32 actim_ctrla_0;
72 	u32 actim_ctrlb_0;
73 	u32 rfr_ctrl_0;
74 	u32 cs_1;
75 	u32 mcfg_1;
76 	u16 mr_1;
77 	u16 emr_1_1;
78 	u16 emr_2_1;
79 	u16 emr_3_1;
80 	u32 actim_ctrla_1;
81 	u32 actim_ctrlb_1;
82 	u32 rfr_ctrl_1;
83 	u16 dcdl_1_ctrl;
84 	u16 dcdl_2_ctrl;
85 	u32 flags;
86 	u32 block_size;
87 };
88 
89 void *omap3_secure_ram_storage;
90 
91 /*
92  * This is used to store ARM registers in SDRAM before attempting
93  * an MPU OFF. The save and restore happens from the SRAM sleep code.
94  * The address is stored in scratchpad, so that it can be used
95  * during the restore path.
96  */
97 u32 omap3_arm_context[128];
98 
99 struct omap3_control_regs {
100 	u32 sysconfig;
101 	u32 devconf0;
102 	u32 mem_dftrw0;
103 	u32 mem_dftrw1;
104 	u32 msuspendmux_0;
105 	u32 msuspendmux_1;
106 	u32 msuspendmux_2;
107 	u32 msuspendmux_3;
108 	u32 msuspendmux_4;
109 	u32 msuspendmux_5;
110 	u32 sec_ctrl;
111 	u32 devconf1;
112 	u32 csirxfe;
113 	u32 iva2_bootaddr;
114 	u32 iva2_bootmod;
115 	u32 debobs_0;
116 	u32 debobs_1;
117 	u32 debobs_2;
118 	u32 debobs_3;
119 	u32 debobs_4;
120 	u32 debobs_5;
121 	u32 debobs_6;
122 	u32 debobs_7;
123 	u32 debobs_8;
124 	u32 prog_io0;
125 	u32 prog_io1;
126 	u32 dss_dpll_spreading;
127 	u32 core_dpll_spreading;
128 	u32 per_dpll_spreading;
129 	u32 usbhost_dpll_spreading;
130 	u32 pbias_lite;
131 	u32 temp_sensor;
132 	u32 sramldo4;
133 	u32 sramldo5;
134 	u32 csi;
135 	u32 padconf_sys_nirq;
136 };
137 
138 static struct omap3_control_regs control_context;
139 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
140 
141 void __init omap2_set_globals_control(void __iomem *ctrl)
142 {
143 	omap2_ctrl_base = ctrl;
144 }
145 
146 u8 omap_ctrl_readb(u16 offset)
147 {
148 	u32 val;
149 	u8 byte_offset = offset & 0x3;
150 
151 	val = omap_ctrl_readl(offset);
152 
153 	return (val >> (byte_offset * 8)) & 0xff;
154 }
155 
156 u16 omap_ctrl_readw(u16 offset)
157 {
158 	u32 val;
159 	u16 byte_offset = offset & 0x2;
160 
161 	val = omap_ctrl_readl(offset);
162 
163 	return (val >> (byte_offset * 8)) & 0xffff;
164 }
165 
166 u32 omap_ctrl_readl(u16 offset)
167 {
168 	u32 val;
169 
170 	offset &= 0xfffc;
171 	if (!omap2_ctrl_syscon)
172 		val = readl_relaxed(omap2_ctrl_base + offset);
173 	else
174 		regmap_read(omap2_ctrl_syscon, omap2_ctrl_offset + offset,
175 			    &val);
176 
177 	return val;
178 }
179 
180 void omap_ctrl_writeb(u8 val, u16 offset)
181 {
182 	u32 tmp;
183 	u8 byte_offset = offset & 0x3;
184 
185 	tmp = omap_ctrl_readl(offset);
186 
187 	tmp &= 0xffffffff ^ (0xff << (byte_offset * 8));
188 	tmp |= val << (byte_offset * 8);
189 
190 	omap_ctrl_writel(tmp, offset);
191 }
192 
193 void omap_ctrl_writew(u16 val, u16 offset)
194 {
195 	u32 tmp;
196 	u8 byte_offset = offset & 0x2;
197 
198 	tmp = omap_ctrl_readl(offset);
199 
200 	tmp &= 0xffffffff ^ (0xffff << (byte_offset * 8));
201 	tmp |= val << (byte_offset * 8);
202 
203 	omap_ctrl_writel(tmp, offset);
204 }
205 
206 void omap_ctrl_writel(u32 val, u16 offset)
207 {
208 	offset &= 0xfffc;
209 	if (!omap2_ctrl_syscon)
210 		writel_relaxed(val, omap2_ctrl_base + offset);
211 	else
212 		regmap_write(omap2_ctrl_syscon, omap2_ctrl_offset + offset,
213 			     val);
214 }
215 
216 #ifdef CONFIG_ARCH_OMAP3
217 
218 /**
219  * omap3_ctrl_write_boot_mode - set scratchpad boot mode for the next boot
220  * @bootmode: 8-bit value to pass to some boot code
221  *
222  * Set the bootmode in the scratchpad RAM.  This is used after the
223  * system restarts.  Not sure what actually uses this - it may be the
224  * bootloader, rather than the boot ROM - contrary to the preserved
225  * comment below.  No return value.
226  */
227 void omap3_ctrl_write_boot_mode(u8 bootmode)
228 {
229 	u32 l;
230 
231 	l = ('B' << 24) | ('M' << 16) | bootmode;
232 
233 	/*
234 	 * Reserve the first word in scratchpad for communicating
235 	 * with the boot ROM. A pointer to a data structure
236 	 * describing the boot process can be stored there,
237 	 * cf. OMAP34xx TRM, Initialization / Software Booting
238 	 * Configuration.
239 	 *
240 	 * XXX This should use some omap_ctrl_writel()-type function
241 	 */
242 	writel_relaxed(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4));
243 }
244 
245 #endif
246 
247 /**
248  * omap_ctrl_write_dsp_boot_addr - set boot address for a remote processor
249  * @bootaddr: physical address of the boot loader
250  *
251  * Set boot address for the boot loader of a supported processor
252  * when a power ON sequence occurs.
253  */
254 void omap_ctrl_write_dsp_boot_addr(u32 bootaddr)
255 {
256 	u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTADDR :
257 		     cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTADDR :
258 		     cpu_is_omap44xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
259 		     soc_is_omap54xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
260 		     0;
261 
262 	if (!offset) {
263 		pr_err("%s: unsupported omap type\n", __func__);
264 		return;
265 	}
266 
267 	omap_ctrl_writel(bootaddr, offset);
268 }
269 
270 /**
271  * omap_ctrl_write_dsp_boot_mode - set boot mode for a remote processor
272  * @bootmode: 8-bit value to pass to some boot code
273  *
274  * Sets boot mode for the boot loader of a supported processor
275  * when a power ON sequence occurs.
276  */
277 void omap_ctrl_write_dsp_boot_mode(u8 bootmode)
278 {
279 	u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTMOD :
280 		     cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTMOD :
281 		     0;
282 
283 	if (!offset) {
284 		pr_err("%s: unsupported omap type\n", __func__);
285 		return;
286 	}
287 
288 	omap_ctrl_writel(bootmode, offset);
289 }
290 
291 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
292 /*
293  * Clears the scratchpad contents in case of cold boot-
294  * called during bootup
295  */
296 void omap3_clear_scratchpad_contents(void)
297 {
298 	u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
299 	void __iomem *v_addr;
300 	u32 offset = 0;
301 
302 	v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
303 	if (omap3xxx_prm_clear_global_cold_reset()) {
304 		for ( ; offset <= max_offset; offset += 0x4)
305 			writel_relaxed(0x0, (v_addr + offset));
306 	}
307 }
308 
309 /* Populate the scratchpad structure with restore structure */
310 void omap3_save_scratchpad_contents(void)
311 {
312 	void  __iomem *scratchpad_address;
313 	u32 arm_context_addr;
314 	struct omap3_scratchpad scratchpad_contents;
315 	struct omap3_scratchpad_prcm_block prcm_block_contents;
316 	struct omap3_scratchpad_sdrc_block sdrc_block_contents;
317 
318 	/*
319 	 * Populate the Scratchpad contents
320 	 *
321 	 * The "get_*restore_pointer" functions are used to provide a
322 	 * physical restore address where the ROM code jumps while waking
323 	 * up from MPU OFF/OSWR state.
324 	 * The restore pointer is stored into the scratchpad.
325 	 */
326 	scratchpad_contents.boot_config_ptr = 0x0;
327 	if (cpu_is_omap3630())
328 		scratchpad_contents.public_restore_ptr =
329 			virt_to_phys(omap3_restore_3630);
330 	else if (omap_rev() != OMAP3430_REV_ES3_0 &&
331 					omap_rev() != OMAP3430_REV_ES3_1 &&
332 					omap_rev() != OMAP3430_REV_ES3_1_2)
333 		scratchpad_contents.public_restore_ptr =
334 			virt_to_phys(omap3_restore);
335 	else
336 		scratchpad_contents.public_restore_ptr =
337 			virt_to_phys(omap3_restore_es3);
338 
339 	if (omap_type() == OMAP2_DEVICE_TYPE_GP)
340 		scratchpad_contents.secure_ram_restore_ptr = 0x0;
341 	else
342 		scratchpad_contents.secure_ram_restore_ptr =
343 			(u32) __pa(omap3_secure_ram_storage);
344 	scratchpad_contents.sdrc_module_semaphore = 0x0;
345 	scratchpad_contents.prcm_block_offset = 0x2C;
346 	scratchpad_contents.sdrc_block_offset = 0x64;
347 
348 	/* Populate the PRCM block contents */
349 	omap3_prm_save_scratchpad_contents(prcm_block_contents.prm_contents);
350 	omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents);
351 
352 	prcm_block_contents.prcm_block_size = 0x0;
353 
354 	/* Populate the SDRC block contents */
355 	sdrc_block_contents.sysconfig =
356 			(sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF);
357 	sdrc_block_contents.cs_cfg =
358 			(sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF);
359 	sdrc_block_contents.sharing =
360 			(sdrc_read_reg(SDRC_SHARING) & 0xFFFF);
361 	sdrc_block_contents.err_type =
362 			(sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF);
363 	sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL);
364 	sdrc_block_contents.dll_b_ctrl = 0x0;
365 	/*
366 	 * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should
367 	 * be programed to issue automatic self refresh on timeout
368 	 * of AUTO_CNT = 1 prior to any transition to OFF mode.
369 	 */
370 	if ((omap_type() != OMAP2_DEVICE_TYPE_GP)
371 			&& (omap_rev() >= OMAP3430_REV_ES3_0))
372 		sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) &
373 				~(SDRC_POWER_AUTOCOUNT_MASK|
374 				SDRC_POWER_CLKCTRL_MASK)) |
375 				(1 << SDRC_POWER_AUTOCOUNT_SHIFT) |
376 				SDRC_SELF_REFRESH_ON_AUTOCOUNT;
377 	else
378 		sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER);
379 
380 	sdrc_block_contents.cs_0 = 0x0;
381 	sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0);
382 	sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF);
383 	sdrc_block_contents.emr_1_0 = 0x0;
384 	sdrc_block_contents.emr_2_0 = 0x0;
385 	sdrc_block_contents.emr_3_0 = 0x0;
386 	sdrc_block_contents.actim_ctrla_0 =
387 			sdrc_read_reg(SDRC_ACTIM_CTRL_A_0);
388 	sdrc_block_contents.actim_ctrlb_0 =
389 			sdrc_read_reg(SDRC_ACTIM_CTRL_B_0);
390 	sdrc_block_contents.rfr_ctrl_0 =
391 			sdrc_read_reg(SDRC_RFR_CTRL_0);
392 	sdrc_block_contents.cs_1 = 0x0;
393 	sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1);
394 	sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF;
395 	sdrc_block_contents.emr_1_1 = 0x0;
396 	sdrc_block_contents.emr_2_1 = 0x0;
397 	sdrc_block_contents.emr_3_1 = 0x0;
398 	sdrc_block_contents.actim_ctrla_1 =
399 			sdrc_read_reg(SDRC_ACTIM_CTRL_A_1);
400 	sdrc_block_contents.actim_ctrlb_1 =
401 			sdrc_read_reg(SDRC_ACTIM_CTRL_B_1);
402 	sdrc_block_contents.rfr_ctrl_1 =
403 			sdrc_read_reg(SDRC_RFR_CTRL_1);
404 	sdrc_block_contents.dcdl_1_ctrl = 0x0;
405 	sdrc_block_contents.dcdl_2_ctrl = 0x0;
406 	sdrc_block_contents.flags = 0x0;
407 	sdrc_block_contents.block_size = 0x0;
408 
409 	arm_context_addr = virt_to_phys(omap3_arm_context);
410 
411 	/* Copy all the contents to the scratchpad location */
412 	scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
413 	memcpy_toio(scratchpad_address, &scratchpad_contents,
414 		 sizeof(scratchpad_contents));
415 	/* Scratchpad contents being 32 bits, a divide by 4 done here */
416 	memcpy_toio(scratchpad_address +
417 		scratchpad_contents.prcm_block_offset,
418 		&prcm_block_contents, sizeof(prcm_block_contents));
419 	memcpy_toio(scratchpad_address +
420 		scratchpad_contents.sdrc_block_offset,
421 		&sdrc_block_contents, sizeof(sdrc_block_contents));
422 	/*
423 	 * Copies the address of the location in SDRAM where ARM
424 	 * registers get saved during a MPU OFF transition.
425 	 */
426 	memcpy_toio(scratchpad_address +
427 		scratchpad_contents.sdrc_block_offset +
428 		sizeof(sdrc_block_contents), &arm_context_addr, 4);
429 }
430 
431 void omap3_control_save_context(void)
432 {
433 	control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG);
434 	control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
435 	control_context.mem_dftrw0 =
436 			omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0);
437 	control_context.mem_dftrw1 =
438 			omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1);
439 	control_context.msuspendmux_0 =
440 			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0);
441 	control_context.msuspendmux_1 =
442 			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1);
443 	control_context.msuspendmux_2 =
444 			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2);
445 	control_context.msuspendmux_3 =
446 			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3);
447 	control_context.msuspendmux_4 =
448 			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4);
449 	control_context.msuspendmux_5 =
450 			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5);
451 	control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL);
452 	control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);
453 	control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE);
454 	control_context.iva2_bootaddr =
455 			omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR);
456 	control_context.iva2_bootmod =
457 			omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD);
458 	control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0));
459 	control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1));
460 	control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2));
461 	control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3));
462 	control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4));
463 	control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5));
464 	control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6));
465 	control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7));
466 	control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8));
467 	control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0);
468 	control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
469 	control_context.dss_dpll_spreading =
470 			omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING);
471 	control_context.core_dpll_spreading =
472 			omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING);
473 	control_context.per_dpll_spreading =
474 			omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING);
475 	control_context.usbhost_dpll_spreading =
476 		omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
477 	control_context.pbias_lite =
478 			omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE);
479 	control_context.temp_sensor =
480 			omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR);
481 	control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4);
482 	control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5);
483 	control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI);
484 	control_context.padconf_sys_nirq =
485 		omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
486 }
487 
488 void omap3_control_restore_context(void)
489 {
490 	omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG);
491 	omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0);
492 	omap_ctrl_writel(control_context.mem_dftrw0,
493 					OMAP343X_CONTROL_MEM_DFTRW0);
494 	omap_ctrl_writel(control_context.mem_dftrw1,
495 					OMAP343X_CONTROL_MEM_DFTRW1);
496 	omap_ctrl_writel(control_context.msuspendmux_0,
497 					OMAP2_CONTROL_MSUSPENDMUX_0);
498 	omap_ctrl_writel(control_context.msuspendmux_1,
499 					OMAP2_CONTROL_MSUSPENDMUX_1);
500 	omap_ctrl_writel(control_context.msuspendmux_2,
501 					OMAP2_CONTROL_MSUSPENDMUX_2);
502 	omap_ctrl_writel(control_context.msuspendmux_3,
503 					OMAP2_CONTROL_MSUSPENDMUX_3);
504 	omap_ctrl_writel(control_context.msuspendmux_4,
505 					OMAP2_CONTROL_MSUSPENDMUX_4);
506 	omap_ctrl_writel(control_context.msuspendmux_5,
507 					OMAP2_CONTROL_MSUSPENDMUX_5);
508 	omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL);
509 	omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1);
510 	omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE);
511 	omap_ctrl_writel(control_context.iva2_bootaddr,
512 					OMAP343X_CONTROL_IVA2_BOOTADDR);
513 	omap_ctrl_writel(control_context.iva2_bootmod,
514 					OMAP343X_CONTROL_IVA2_BOOTMOD);
515 	omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0));
516 	omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1));
517 	omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2));
518 	omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3));
519 	omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4));
520 	omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5));
521 	omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6));
522 	omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7));
523 	omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8));
524 	omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0);
525 	omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1);
526 	omap_ctrl_writel(control_context.dss_dpll_spreading,
527 					OMAP343X_CONTROL_DSS_DPLL_SPREADING);
528 	omap_ctrl_writel(control_context.core_dpll_spreading,
529 					OMAP343X_CONTROL_CORE_DPLL_SPREADING);
530 	omap_ctrl_writel(control_context.per_dpll_spreading,
531 					OMAP343X_CONTROL_PER_DPLL_SPREADING);
532 	omap_ctrl_writel(control_context.usbhost_dpll_spreading,
533 				OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
534 	omap_ctrl_writel(control_context.pbias_lite,
535 					OMAP343X_CONTROL_PBIAS_LITE);
536 	omap_ctrl_writel(control_context.temp_sensor,
537 					OMAP343X_CONTROL_TEMP_SENSOR);
538 	omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4);
539 	omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5);
540 	omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
541 	omap_ctrl_writel(control_context.padconf_sys_nirq,
542 			 OMAP343X_CONTROL_PADCONF_SYSNIRQ);
543 }
544 
545 void omap3630_ctrl_disable_rta(void)
546 {
547 	if (!cpu_is_omap3630())
548 		return;
549 	omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL);
550 }
551 
552 /**
553  * omap3_ctrl_save_padconf - save padconf registers to scratchpad RAM
554  *
555  * Tell the SCM to start saving the padconf registers, then wait for
556  * the process to complete.  Returns 0 unconditionally, although it
557  * should also eventually be able to return -ETIMEDOUT, if the save
558  * does not complete.
559  *
560  * XXX This function is missing a timeout.  What should it be?
561  */
562 int omap3_ctrl_save_padconf(void)
563 {
564 	u32 cpo;
565 
566 	/* Save the padconf registers */
567 	cpo = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
568 	cpo |= START_PADCONF_SAVE;
569 	omap_ctrl_writel(cpo, OMAP343X_CONTROL_PADCONF_OFF);
570 
571 	/* wait for the save to complete */
572 	while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
573 		 & PADCONF_SAVE_DONE))
574 		udelay(1);
575 
576 	return 0;
577 }
578 
579 /**
580  * omap3_ctrl_set_iva_bootmode_idle - sets the IVA2 bootmode to idle
581  *
582  * Sets the bootmode for IVA2 to idle. This is needed by the PM code to
583  * force disable IVA2 so that it does not prevent any low-power states.
584  */
585 static void __init omap3_ctrl_set_iva_bootmode_idle(void)
586 {
587 	omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
588 			 OMAP343X_CONTROL_IVA2_BOOTMOD);
589 }
590 
591 /**
592  * omap3_ctrl_setup_d2d_padconf - setup stacked modem pads for idle
593  *
594  * Sets up the pads controlling the stacked modem in such way that the
595  * device can enter idle.
596  */
597 static void __init omap3_ctrl_setup_d2d_padconf(void)
598 {
599 	u16 mask, padconf;
600 
601 	/*
602 	 * In a stand alone OMAP3430 where there is not a stacked
603 	 * modem for the D2D Idle Ack and D2D MStandby must be pulled
604 	 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
605 	 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up.
606 	 */
607 	mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
608 	padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
609 	padconf |= mask;
610 	omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
611 
612 	padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
613 	padconf |= mask;
614 	omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
615 }
616 
617 /**
618  * omap3_ctrl_init - does static initializations for control module
619  *
620  * Initializes system control module. This sets up the sysconfig autoidle,
621  * and sets up modem and iva2 so that they can be idled properly.
622  */
623 void __init omap3_ctrl_init(void)
624 {
625 	omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
626 
627 	omap3_ctrl_set_iva_bootmode_idle();
628 
629 	omap3_ctrl_setup_d2d_padconf();
630 }
631 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
632 
633 struct control_init_data {
634 	int index;
635 	s16 offset;
636 };
637 
638 static struct control_init_data ctrl_data = {
639 	.index = TI_CLKM_CTRL,
640 };
641 
642 static const struct control_init_data omap2_ctrl_data = {
643 	.index = TI_CLKM_CTRL,
644 	.offset = -OMAP2_CONTROL_GENERAL,
645 };
646 
647 static const struct of_device_id omap_scrm_dt_match_table[] = {
648 	{ .compatible = "ti,am3-scm", .data = &ctrl_data },
649 	{ .compatible = "ti,am4-scm", .data = &ctrl_data },
650 	{ .compatible = "ti,omap2-scm", .data = &omap2_ctrl_data },
651 	{ .compatible = "ti,omap3-scm", .data = &omap2_ctrl_data },
652 	{ .compatible = "ti,dm816-scrm", .data = &ctrl_data },
653 	{ .compatible = "ti,omap4-scm-core", .data = &ctrl_data },
654 	{ .compatible = "ti,omap5-scm-core", .data = &ctrl_data },
655 	{ .compatible = "ti,dra7-scm-core", .data = &ctrl_data },
656 	{ }
657 };
658 
659 /**
660  * omap2_control_base_init - initialize iomappings for the control driver
661  *
662  * Detects and initializes the iomappings for the control driver, based
663  * on the DT data. Returns 0 in success, negative error value
664  * otherwise.
665  */
666 int __init omap2_control_base_init(void)
667 {
668 	struct device_node *np;
669 	const struct of_device_id *match;
670 	struct control_init_data *data;
671 
672 	for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) {
673 		data = (struct control_init_data *)match->data;
674 
675 		omap2_ctrl_base = of_iomap(np, 0);
676 		if (!omap2_ctrl_base)
677 			return -ENOMEM;
678 
679 		omap2_ctrl_offset = data->offset;
680 	}
681 
682 	return 0;
683 }
684 
685 /**
686  * omap_control_init - low level init for the control driver
687  *
688  * Initializes the low level clock infrastructure for control driver.
689  * Returns 0 in success, negative error value in failure.
690  */
691 int __init omap_control_init(void)
692 {
693 	struct device_node *np, *scm_conf;
694 	const struct of_device_id *match;
695 	const struct omap_prcm_init_data *data;
696 	int ret;
697 	struct regmap *syscon;
698 
699 	for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) {
700 		data = match->data;
701 
702 		/*
703 		 * Check if we have scm_conf node, if yes, use this to
704 		 * access clock registers.
705 		 */
706 		scm_conf = of_get_child_by_name(np, "scm_conf");
707 
708 		if (scm_conf) {
709 			syscon = syscon_node_to_regmap(scm_conf);
710 
711 			if (IS_ERR(syscon))
712 				return PTR_ERR(syscon);
713 
714 			omap2_ctrl_syscon = syscon;
715 
716 			if (of_get_child_by_name(scm_conf, "clocks")) {
717 				ret = omap2_clk_provider_init(scm_conf,
718 							      data->index,
719 							      syscon, NULL);
720 				if (ret)
721 					return ret;
722 			}
723 
724 			iounmap(omap2_ctrl_base);
725 			omap2_ctrl_base = NULL;
726 		} else {
727 			/* No scm_conf found, direct access */
728 			ret = omap2_clk_provider_init(np, data->index, NULL,
729 						      omap2_ctrl_base);
730 			if (ret)
731 				return ret;
732 		}
733 	}
734 
735 	return 0;
736 }
737 
738 /**
739  * omap3_control_legacy_iomap_init - legacy iomap init for clock providers
740  *
741  * Legacy iomap init for clock provider. Needed only by legacy boot mode,
742  * where the base addresses are not parsed from DT, but still required
743  * by the clock driver to be setup properly.
744  */
745 void __init omap3_control_legacy_iomap_init(void)
746 {
747 	omap2_clk_legacy_provider_init(TI_CLKM_SCRM, omap2_ctrl_base);
748 }
749