1 /* 2 * OMAP2/3 System Control Module register access 3 * 4 * Copyright (C) 2007 Texas Instruments, Inc. 5 * Copyright (C) 2007 Nokia Corporation 6 * 7 * Written by Paul Walmsley 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 #undef DEBUG 14 15 #include <linux/kernel.h> 16 #include <linux/io.h> 17 18 #include <plat/common.h> 19 #include <plat/sdrc.h> 20 21 #include "cm-regbits-34xx.h" 22 #include "prm-regbits-34xx.h" 23 #include "cm.h" 24 #include "prm.h" 25 #include "sdrc.h" 26 #include "pm.h" 27 #include "control.h" 28 29 static void __iomem *omap2_ctrl_base; 30 static void __iomem *omap4_ctrl_pad_base; 31 32 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 33 struct omap3_scratchpad { 34 u32 boot_config_ptr; 35 u32 public_restore_ptr; 36 u32 secure_ram_restore_ptr; 37 u32 sdrc_module_semaphore; 38 u32 prcm_block_offset; 39 u32 sdrc_block_offset; 40 }; 41 42 struct omap3_scratchpad_prcm_block { 43 u32 prm_clksrc_ctrl; 44 u32 prm_clksel; 45 u32 cm_clksel_core; 46 u32 cm_clksel_wkup; 47 u32 cm_clken_pll; 48 u32 cm_autoidle_pll; 49 u32 cm_clksel1_pll; 50 u32 cm_clksel2_pll; 51 u32 cm_clksel3_pll; 52 u32 cm_clken_pll_mpu; 53 u32 cm_autoidle_pll_mpu; 54 u32 cm_clksel1_pll_mpu; 55 u32 cm_clksel2_pll_mpu; 56 u32 prcm_block_size; 57 }; 58 59 struct omap3_scratchpad_sdrc_block { 60 u16 sysconfig; 61 u16 cs_cfg; 62 u16 sharing; 63 u16 err_type; 64 u32 dll_a_ctrl; 65 u32 dll_b_ctrl; 66 u32 power; 67 u32 cs_0; 68 u32 mcfg_0; 69 u16 mr_0; 70 u16 emr_1_0; 71 u16 emr_2_0; 72 u16 emr_3_0; 73 u32 actim_ctrla_0; 74 u32 actim_ctrlb_0; 75 u32 rfr_ctrl_0; 76 u32 cs_1; 77 u32 mcfg_1; 78 u16 mr_1; 79 u16 emr_1_1; 80 u16 emr_2_1; 81 u16 emr_3_1; 82 u32 actim_ctrla_1; 83 u32 actim_ctrlb_1; 84 u32 rfr_ctrl_1; 85 u16 dcdl_1_ctrl; 86 u16 dcdl_2_ctrl; 87 u32 flags; 88 u32 block_size; 89 }; 90 91 void *omap3_secure_ram_storage; 92 93 /* 94 * This is used to store ARM registers in SDRAM before attempting 95 * an MPU OFF. The save and restore happens from the SRAM sleep code. 96 * The address is stored in scratchpad, so that it can be used 97 * during the restore path. 98 */ 99 u32 omap3_arm_context[128]; 100 101 struct omap3_control_regs { 102 u32 sysconfig; 103 u32 devconf0; 104 u32 mem_dftrw0; 105 u32 mem_dftrw1; 106 u32 msuspendmux_0; 107 u32 msuspendmux_1; 108 u32 msuspendmux_2; 109 u32 msuspendmux_3; 110 u32 msuspendmux_4; 111 u32 msuspendmux_5; 112 u32 sec_ctrl; 113 u32 devconf1; 114 u32 csirxfe; 115 u32 iva2_bootaddr; 116 u32 iva2_bootmod; 117 u32 debobs_0; 118 u32 debobs_1; 119 u32 debobs_2; 120 u32 debobs_3; 121 u32 debobs_4; 122 u32 debobs_5; 123 u32 debobs_6; 124 u32 debobs_7; 125 u32 debobs_8; 126 u32 prog_io0; 127 u32 prog_io1; 128 u32 dss_dpll_spreading; 129 u32 core_dpll_spreading; 130 u32 per_dpll_spreading; 131 u32 usbhost_dpll_spreading; 132 u32 pbias_lite; 133 u32 temp_sensor; 134 u32 sramldo4; 135 u32 sramldo5; 136 u32 csi; 137 }; 138 139 static struct omap3_control_regs control_context; 140 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ 141 142 #define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg)) 143 #define OMAP4_CTRL_PAD_REGADDR(reg) (omap4_ctrl_pad_base + (reg)) 144 145 void __init omap2_set_globals_control(struct omap_globals *omap2_globals) 146 { 147 /* Static mapping, never released */ 148 if (omap2_globals->ctrl) { 149 omap2_ctrl_base = ioremap(omap2_globals->ctrl, SZ_4K); 150 WARN_ON(!omap2_ctrl_base); 151 } 152 153 /* Static mapping, never released */ 154 if (omap2_globals->ctrl_pad) { 155 omap4_ctrl_pad_base = ioremap(omap2_globals->ctrl_pad, SZ_4K); 156 WARN_ON(!omap4_ctrl_pad_base); 157 } 158 } 159 160 void __iomem *omap_ctrl_base_get(void) 161 { 162 return omap2_ctrl_base; 163 } 164 165 u8 omap_ctrl_readb(u16 offset) 166 { 167 return __raw_readb(OMAP_CTRL_REGADDR(offset)); 168 } 169 170 u16 omap_ctrl_readw(u16 offset) 171 { 172 return __raw_readw(OMAP_CTRL_REGADDR(offset)); 173 } 174 175 u32 omap_ctrl_readl(u16 offset) 176 { 177 return __raw_readl(OMAP_CTRL_REGADDR(offset)); 178 } 179 180 void omap_ctrl_writeb(u8 val, u16 offset) 181 { 182 __raw_writeb(val, OMAP_CTRL_REGADDR(offset)); 183 } 184 185 void omap_ctrl_writew(u16 val, u16 offset) 186 { 187 __raw_writew(val, OMAP_CTRL_REGADDR(offset)); 188 } 189 190 void omap_ctrl_writel(u32 val, u16 offset) 191 { 192 __raw_writel(val, OMAP_CTRL_REGADDR(offset)); 193 } 194 195 /* 196 * On OMAP4 control pad are not addressable from control 197 * core base. So the common omap_ctrl_read/write APIs breaks 198 * Hence export separate APIs to manage the omap4 pad control 199 * registers. This APIs will work only for OMAP4 200 */ 201 202 u32 omap4_ctrl_pad_readl(u16 offset) 203 { 204 return __raw_readl(OMAP4_CTRL_PAD_REGADDR(offset)); 205 } 206 207 void omap4_ctrl_pad_writel(u32 val, u16 offset) 208 { 209 __raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset)); 210 } 211 212 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 213 /* 214 * Clears the scratchpad contents in case of cold boot- 215 * called during bootup 216 */ 217 void omap3_clear_scratchpad_contents(void) 218 { 219 u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET; 220 void __iomem *v_addr; 221 u32 offset = 0; 222 v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM); 223 if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) & 224 OMAP3430_GLOBAL_COLD_RST_MASK) { 225 for ( ; offset <= max_offset; offset += 0x4) 226 __raw_writel(0x0, (v_addr + offset)); 227 prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK, 228 OMAP3430_GR_MOD, 229 OMAP3_PRM_RSTST_OFFSET); 230 } 231 } 232 233 /* Populate the scratchpad structure with restore structure */ 234 void omap3_save_scratchpad_contents(void) 235 { 236 void __iomem *scratchpad_address; 237 u32 arm_context_addr; 238 struct omap3_scratchpad scratchpad_contents; 239 struct omap3_scratchpad_prcm_block prcm_block_contents; 240 struct omap3_scratchpad_sdrc_block sdrc_block_contents; 241 242 /* Populate the Scratchpad contents */ 243 scratchpad_contents.boot_config_ptr = 0x0; 244 if (omap_rev() != OMAP3430_REV_ES3_0 && 245 omap_rev() != OMAP3430_REV_ES3_1) 246 scratchpad_contents.public_restore_ptr = 247 virt_to_phys(get_restore_pointer()); 248 else 249 scratchpad_contents.public_restore_ptr = 250 virt_to_phys(get_es3_restore_pointer()); 251 if (omap_type() == OMAP2_DEVICE_TYPE_GP) 252 scratchpad_contents.secure_ram_restore_ptr = 0x0; 253 else 254 scratchpad_contents.secure_ram_restore_ptr = 255 (u32) __pa(omap3_secure_ram_storage); 256 scratchpad_contents.sdrc_module_semaphore = 0x0; 257 scratchpad_contents.prcm_block_offset = 0x2C; 258 scratchpad_contents.sdrc_block_offset = 0x64; 259 260 /* Populate the PRCM block contents */ 261 prcm_block_contents.prm_clksrc_ctrl = prm_read_mod_reg(OMAP3430_GR_MOD, 262 OMAP3_PRM_CLKSRC_CTRL_OFFSET); 263 prcm_block_contents.prm_clksel = prm_read_mod_reg(OMAP3430_CCR_MOD, 264 OMAP3_PRM_CLKSEL_OFFSET); 265 prcm_block_contents.cm_clksel_core = 266 cm_read_mod_reg(CORE_MOD, CM_CLKSEL); 267 prcm_block_contents.cm_clksel_wkup = 268 cm_read_mod_reg(WKUP_MOD, CM_CLKSEL); 269 prcm_block_contents.cm_clken_pll = 270 cm_read_mod_reg(PLL_MOD, CM_CLKEN); 271 prcm_block_contents.cm_autoidle_pll = 272 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL); 273 prcm_block_contents.cm_clksel1_pll = 274 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL); 275 prcm_block_contents.cm_clksel2_pll = 276 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL); 277 prcm_block_contents.cm_clksel3_pll = 278 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3); 279 prcm_block_contents.cm_clken_pll_mpu = 280 cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL); 281 prcm_block_contents.cm_autoidle_pll_mpu = 282 cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL); 283 prcm_block_contents.cm_clksel1_pll_mpu = 284 cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL); 285 prcm_block_contents.cm_clksel2_pll_mpu = 286 cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL); 287 prcm_block_contents.prcm_block_size = 0x0; 288 289 /* Populate the SDRC block contents */ 290 sdrc_block_contents.sysconfig = 291 (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF); 292 sdrc_block_contents.cs_cfg = 293 (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF); 294 sdrc_block_contents.sharing = 295 (sdrc_read_reg(SDRC_SHARING) & 0xFFFF); 296 sdrc_block_contents.err_type = 297 (sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF); 298 sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL); 299 sdrc_block_contents.dll_b_ctrl = 0x0; 300 /* 301 * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should 302 * be programed to issue automatic self refresh on timeout 303 * of AUTO_CNT = 1 prior to any transition to OFF mode. 304 */ 305 if ((omap_type() != OMAP2_DEVICE_TYPE_GP) 306 && (omap_rev() >= OMAP3430_REV_ES3_0)) 307 sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) & 308 ~(SDRC_POWER_AUTOCOUNT_MASK| 309 SDRC_POWER_CLKCTRL_MASK)) | 310 (1 << SDRC_POWER_AUTOCOUNT_SHIFT) | 311 SDRC_SELF_REFRESH_ON_AUTOCOUNT; 312 else 313 sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER); 314 315 sdrc_block_contents.cs_0 = 0x0; 316 sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0); 317 sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF); 318 sdrc_block_contents.emr_1_0 = 0x0; 319 sdrc_block_contents.emr_2_0 = 0x0; 320 sdrc_block_contents.emr_3_0 = 0x0; 321 sdrc_block_contents.actim_ctrla_0 = 322 sdrc_read_reg(SDRC_ACTIM_CTRL_A_0); 323 sdrc_block_contents.actim_ctrlb_0 = 324 sdrc_read_reg(SDRC_ACTIM_CTRL_B_0); 325 sdrc_block_contents.rfr_ctrl_0 = 326 sdrc_read_reg(SDRC_RFR_CTRL_0); 327 sdrc_block_contents.cs_1 = 0x0; 328 sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1); 329 sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF; 330 sdrc_block_contents.emr_1_1 = 0x0; 331 sdrc_block_contents.emr_2_1 = 0x0; 332 sdrc_block_contents.emr_3_1 = 0x0; 333 sdrc_block_contents.actim_ctrla_1 = 334 sdrc_read_reg(SDRC_ACTIM_CTRL_A_1); 335 sdrc_block_contents.actim_ctrlb_1 = 336 sdrc_read_reg(SDRC_ACTIM_CTRL_B_1); 337 sdrc_block_contents.rfr_ctrl_1 = 338 sdrc_read_reg(SDRC_RFR_CTRL_1); 339 sdrc_block_contents.dcdl_1_ctrl = 0x0; 340 sdrc_block_contents.dcdl_2_ctrl = 0x0; 341 sdrc_block_contents.flags = 0x0; 342 sdrc_block_contents.block_size = 0x0; 343 344 arm_context_addr = virt_to_phys(omap3_arm_context); 345 346 /* Copy all the contents to the scratchpad location */ 347 scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD); 348 memcpy_toio(scratchpad_address, &scratchpad_contents, 349 sizeof(scratchpad_contents)); 350 /* Scratchpad contents being 32 bits, a divide by 4 done here */ 351 memcpy_toio(scratchpad_address + 352 scratchpad_contents.prcm_block_offset, 353 &prcm_block_contents, sizeof(prcm_block_contents)); 354 memcpy_toio(scratchpad_address + 355 scratchpad_contents.sdrc_block_offset, 356 &sdrc_block_contents, sizeof(sdrc_block_contents)); 357 /* 358 * Copies the address of the location in SDRAM where ARM 359 * registers get saved during a MPU OFF transition. 360 */ 361 memcpy_toio(scratchpad_address + 362 scratchpad_contents.sdrc_block_offset + 363 sizeof(sdrc_block_contents), &arm_context_addr, 4); 364 } 365 366 void omap3_control_save_context(void) 367 { 368 control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG); 369 control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); 370 control_context.mem_dftrw0 = 371 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0); 372 control_context.mem_dftrw1 = 373 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1); 374 control_context.msuspendmux_0 = 375 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0); 376 control_context.msuspendmux_1 = 377 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1); 378 control_context.msuspendmux_2 = 379 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2); 380 control_context.msuspendmux_3 = 381 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3); 382 control_context.msuspendmux_4 = 383 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4); 384 control_context.msuspendmux_5 = 385 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5); 386 control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL); 387 control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1); 388 control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE); 389 control_context.iva2_bootaddr = 390 omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR); 391 control_context.iva2_bootmod = 392 omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD); 393 control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0)); 394 control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1)); 395 control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2)); 396 control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3)); 397 control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4)); 398 control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5)); 399 control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6)); 400 control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7)); 401 control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8)); 402 control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0); 403 control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1); 404 control_context.dss_dpll_spreading = 405 omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING); 406 control_context.core_dpll_spreading = 407 omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING); 408 control_context.per_dpll_spreading = 409 omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING); 410 control_context.usbhost_dpll_spreading = 411 omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING); 412 control_context.pbias_lite = 413 omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE); 414 control_context.temp_sensor = 415 omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR); 416 control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4); 417 control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5); 418 control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI); 419 return; 420 } 421 422 void omap3_control_restore_context(void) 423 { 424 omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG); 425 omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0); 426 omap_ctrl_writel(control_context.mem_dftrw0, 427 OMAP343X_CONTROL_MEM_DFTRW0); 428 omap_ctrl_writel(control_context.mem_dftrw1, 429 OMAP343X_CONTROL_MEM_DFTRW1); 430 omap_ctrl_writel(control_context.msuspendmux_0, 431 OMAP2_CONTROL_MSUSPENDMUX_0); 432 omap_ctrl_writel(control_context.msuspendmux_1, 433 OMAP2_CONTROL_MSUSPENDMUX_1); 434 omap_ctrl_writel(control_context.msuspendmux_2, 435 OMAP2_CONTROL_MSUSPENDMUX_2); 436 omap_ctrl_writel(control_context.msuspendmux_3, 437 OMAP2_CONTROL_MSUSPENDMUX_3); 438 omap_ctrl_writel(control_context.msuspendmux_4, 439 OMAP2_CONTROL_MSUSPENDMUX_4); 440 omap_ctrl_writel(control_context.msuspendmux_5, 441 OMAP2_CONTROL_MSUSPENDMUX_5); 442 omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL); 443 omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1); 444 omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE); 445 omap_ctrl_writel(control_context.iva2_bootaddr, 446 OMAP343X_CONTROL_IVA2_BOOTADDR); 447 omap_ctrl_writel(control_context.iva2_bootmod, 448 OMAP343X_CONTROL_IVA2_BOOTMOD); 449 omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0)); 450 omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1)); 451 omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2)); 452 omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3)); 453 omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4)); 454 omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5)); 455 omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6)); 456 omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7)); 457 omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8)); 458 omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0); 459 omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1); 460 omap_ctrl_writel(control_context.dss_dpll_spreading, 461 OMAP343X_CONTROL_DSS_DPLL_SPREADING); 462 omap_ctrl_writel(control_context.core_dpll_spreading, 463 OMAP343X_CONTROL_CORE_DPLL_SPREADING); 464 omap_ctrl_writel(control_context.per_dpll_spreading, 465 OMAP343X_CONTROL_PER_DPLL_SPREADING); 466 omap_ctrl_writel(control_context.usbhost_dpll_spreading, 467 OMAP343X_CONTROL_USBHOST_DPLL_SPREADING); 468 omap_ctrl_writel(control_context.pbias_lite, 469 OMAP343X_CONTROL_PBIAS_LITE); 470 omap_ctrl_writel(control_context.temp_sensor, 471 OMAP343X_CONTROL_TEMP_SENSOR); 472 omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4); 473 omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5); 474 omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI); 475 return; 476 } 477 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ 478