1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * OMAP2/3 System Control Module register access 4 * 5 * Copyright (C) 2007, 2012 Texas Instruments, Inc. 6 * Copyright (C) 2007 Nokia Corporation 7 * 8 * Written by Paul Walmsley 9 */ 10 #undef DEBUG 11 12 #include <linux/kernel.h> 13 #include <linux/io.h> 14 #include <linux/of_address.h> 15 #include <linux/regmap.h> 16 #include <linux/mfd/syscon.h> 17 #include <linux/cpu_pm.h> 18 19 #include "soc.h" 20 #include "iomap.h" 21 #include "common.h" 22 #include "cm-regbits-34xx.h" 23 #include "prm-regbits-34xx.h" 24 #include "prm3xxx.h" 25 #include "cm3xxx.h" 26 #include "sdrc.h" 27 #include "pm.h" 28 #include "control.h" 29 #include "clock.h" 30 31 /* Used by omap3_ctrl_save_padconf() */ 32 #define START_PADCONF_SAVE 0x2 33 #define PADCONF_SAVE_DONE 0x1 34 35 static void __iomem *omap2_ctrl_base; 36 static s16 omap2_ctrl_offset; 37 38 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 39 struct omap3_scratchpad { 40 u32 boot_config_ptr; 41 u32 public_restore_ptr; 42 u32 secure_ram_restore_ptr; 43 u32 sdrc_module_semaphore; 44 u32 prcm_block_offset; 45 u32 sdrc_block_offset; 46 }; 47 48 struct omap3_scratchpad_prcm_block { 49 u32 prm_contents[2]; 50 u32 cm_contents[11]; 51 u32 prcm_block_size; 52 }; 53 54 struct omap3_scratchpad_sdrc_block { 55 u16 sysconfig; 56 u16 cs_cfg; 57 u16 sharing; 58 u16 err_type; 59 u32 dll_a_ctrl; 60 u32 dll_b_ctrl; 61 u32 power; 62 u32 cs_0; 63 u32 mcfg_0; 64 u16 mr_0; 65 u16 emr_1_0; 66 u16 emr_2_0; 67 u16 emr_3_0; 68 u32 actim_ctrla_0; 69 u32 actim_ctrlb_0; 70 u32 rfr_ctrl_0; 71 u32 cs_1; 72 u32 mcfg_1; 73 u16 mr_1; 74 u16 emr_1_1; 75 u16 emr_2_1; 76 u16 emr_3_1; 77 u32 actim_ctrla_1; 78 u32 actim_ctrlb_1; 79 u32 rfr_ctrl_1; 80 u16 dcdl_1_ctrl; 81 u16 dcdl_2_ctrl; 82 u32 flags; 83 u32 block_size; 84 }; 85 86 void *omap3_secure_ram_storage; 87 88 /* 89 * This is used to store ARM registers in SDRAM before attempting 90 * an MPU OFF. The save and restore happens from the SRAM sleep code. 91 * The address is stored in scratchpad, so that it can be used 92 * during the restore path. 93 */ 94 u32 omap3_arm_context[128]; 95 96 struct omap3_control_regs { 97 u32 sysconfig; 98 u32 devconf0; 99 u32 mem_dftrw0; 100 u32 mem_dftrw1; 101 u32 msuspendmux_0; 102 u32 msuspendmux_1; 103 u32 msuspendmux_2; 104 u32 msuspendmux_3; 105 u32 msuspendmux_4; 106 u32 msuspendmux_5; 107 u32 sec_ctrl; 108 u32 devconf1; 109 u32 csirxfe; 110 u32 iva2_bootaddr; 111 u32 iva2_bootmod; 112 u32 wkup_ctrl; 113 u32 debobs_0; 114 u32 debobs_1; 115 u32 debobs_2; 116 u32 debobs_3; 117 u32 debobs_4; 118 u32 debobs_5; 119 u32 debobs_6; 120 u32 debobs_7; 121 u32 debobs_8; 122 u32 prog_io0; 123 u32 prog_io1; 124 u32 dss_dpll_spreading; 125 u32 core_dpll_spreading; 126 u32 per_dpll_spreading; 127 u32 usbhost_dpll_spreading; 128 u32 pbias_lite; 129 u32 temp_sensor; 130 u32 sramldo4; 131 u32 sramldo5; 132 u32 csi; 133 u32 padconf_sys_nirq; 134 }; 135 136 static struct omap3_control_regs control_context; 137 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ 138 139 void __init omap2_set_globals_control(void __iomem *ctrl) 140 { 141 omap2_ctrl_base = ctrl; 142 } 143 144 u8 omap_ctrl_readb(u16 offset) 145 { 146 u32 val; 147 u8 byte_offset = offset & 0x3; 148 149 val = omap_ctrl_readl(offset); 150 151 return (val >> (byte_offset * 8)) & 0xff; 152 } 153 154 u16 omap_ctrl_readw(u16 offset) 155 { 156 u32 val; 157 u16 byte_offset = offset & 0x2; 158 159 val = omap_ctrl_readl(offset); 160 161 return (val >> (byte_offset * 8)) & 0xffff; 162 } 163 164 u32 omap_ctrl_readl(u16 offset) 165 { 166 offset &= 0xfffc; 167 168 return readl_relaxed(omap2_ctrl_base + offset); 169 } 170 171 void omap_ctrl_writeb(u8 val, u16 offset) 172 { 173 u32 tmp; 174 u8 byte_offset = offset & 0x3; 175 176 tmp = omap_ctrl_readl(offset); 177 178 tmp &= 0xffffffff ^ (0xff << (byte_offset * 8)); 179 tmp |= val << (byte_offset * 8); 180 181 omap_ctrl_writel(tmp, offset); 182 } 183 184 void omap_ctrl_writew(u16 val, u16 offset) 185 { 186 u32 tmp; 187 u8 byte_offset = offset & 0x2; 188 189 tmp = omap_ctrl_readl(offset); 190 191 tmp &= 0xffffffff ^ (0xffff << (byte_offset * 8)); 192 tmp |= val << (byte_offset * 8); 193 194 omap_ctrl_writel(tmp, offset); 195 } 196 197 void omap_ctrl_writel(u32 val, u16 offset) 198 { 199 offset &= 0xfffc; 200 writel_relaxed(val, omap2_ctrl_base + offset); 201 } 202 203 #ifdef CONFIG_ARCH_OMAP3 204 205 /** 206 * omap3_ctrl_write_boot_mode - set scratchpad boot mode for the next boot 207 * @bootmode: 8-bit value to pass to some boot code 208 * 209 * Set the bootmode in the scratchpad RAM. This is used after the 210 * system restarts. Not sure what actually uses this - it may be the 211 * bootloader, rather than the boot ROM - contrary to the preserved 212 * comment below. No return value. 213 */ 214 void omap3_ctrl_write_boot_mode(u8 bootmode) 215 { 216 u32 l; 217 218 l = ('B' << 24) | ('M' << 16) | bootmode; 219 220 /* 221 * Reserve the first word in scratchpad for communicating 222 * with the boot ROM. A pointer to a data structure 223 * describing the boot process can be stored there, 224 * cf. OMAP34xx TRM, Initialization / Software Booting 225 * Configuration. 226 * 227 * XXX This should use some omap_ctrl_writel()-type function 228 */ 229 writel_relaxed(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4)); 230 } 231 232 #endif 233 234 /** 235 * omap_ctrl_write_dsp_boot_addr - set boot address for a remote processor 236 * @bootaddr: physical address of the boot loader 237 * 238 * Set boot address for the boot loader of a supported processor 239 * when a power ON sequence occurs. 240 */ 241 void omap_ctrl_write_dsp_boot_addr(u32 bootaddr) 242 { 243 u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTADDR : 244 cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTADDR : 245 cpu_is_omap44xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR : 246 soc_is_omap54xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR : 247 0; 248 249 if (!offset) { 250 pr_err("%s: unsupported omap type\n", __func__); 251 return; 252 } 253 254 omap_ctrl_writel(bootaddr, offset); 255 } 256 257 /** 258 * omap_ctrl_write_dsp_boot_mode - set boot mode for a remote processor 259 * @bootmode: 8-bit value to pass to some boot code 260 * 261 * Sets boot mode for the boot loader of a supported processor 262 * when a power ON sequence occurs. 263 */ 264 void omap_ctrl_write_dsp_boot_mode(u8 bootmode) 265 { 266 u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTMOD : 267 cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTMOD : 268 0; 269 270 if (!offset) { 271 pr_err("%s: unsupported omap type\n", __func__); 272 return; 273 } 274 275 omap_ctrl_writel(bootmode, offset); 276 } 277 278 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 279 /* 280 * Clears the scratchpad contents in case of cold boot- 281 * called during bootup 282 */ 283 void omap3_clear_scratchpad_contents(void) 284 { 285 u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET; 286 void __iomem *v_addr; 287 u32 offset = 0; 288 289 v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM); 290 if (omap3xxx_prm_clear_global_cold_reset()) { 291 for ( ; offset <= max_offset; offset += 0x4) 292 writel_relaxed(0x0, (v_addr + offset)); 293 } 294 } 295 296 /* Populate the scratchpad structure with restore structure */ 297 void omap3_save_scratchpad_contents(void) 298 { 299 void __iomem *scratchpad_address; 300 u32 arm_context_addr; 301 struct omap3_scratchpad scratchpad_contents; 302 struct omap3_scratchpad_prcm_block prcm_block_contents; 303 struct omap3_scratchpad_sdrc_block sdrc_block_contents; 304 305 /* 306 * Populate the Scratchpad contents 307 * 308 * The "get_*restore_pointer" functions are used to provide a 309 * physical restore address where the ROM code jumps while waking 310 * up from MPU OFF/OSWR state. 311 * The restore pointer is stored into the scratchpad. 312 */ 313 scratchpad_contents.boot_config_ptr = 0x0; 314 if (cpu_is_omap3630()) 315 scratchpad_contents.public_restore_ptr = 316 __pa_symbol(omap3_restore_3630); 317 else if (omap_rev() != OMAP3430_REV_ES3_0 && 318 omap_rev() != OMAP3430_REV_ES3_1 && 319 omap_rev() != OMAP3430_REV_ES3_1_2) 320 scratchpad_contents.public_restore_ptr = 321 __pa_symbol(omap3_restore); 322 else 323 scratchpad_contents.public_restore_ptr = 324 __pa_symbol(omap3_restore_es3); 325 326 if (omap_type() == OMAP2_DEVICE_TYPE_GP) 327 scratchpad_contents.secure_ram_restore_ptr = 0x0; 328 else 329 scratchpad_contents.secure_ram_restore_ptr = 330 (u32) __pa(omap3_secure_ram_storage); 331 scratchpad_contents.sdrc_module_semaphore = 0x0; 332 scratchpad_contents.prcm_block_offset = 0x2C; 333 scratchpad_contents.sdrc_block_offset = 0x64; 334 335 /* Populate the PRCM block contents */ 336 omap3_prm_save_scratchpad_contents(prcm_block_contents.prm_contents); 337 omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents); 338 339 prcm_block_contents.prcm_block_size = 0x0; 340 341 /* Populate the SDRC block contents */ 342 sdrc_block_contents.sysconfig = 343 (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF); 344 sdrc_block_contents.cs_cfg = 345 (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF); 346 sdrc_block_contents.sharing = 347 (sdrc_read_reg(SDRC_SHARING) & 0xFFFF); 348 sdrc_block_contents.err_type = 349 (sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF); 350 sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL); 351 sdrc_block_contents.dll_b_ctrl = 0x0; 352 /* 353 * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should 354 * be programed to issue automatic self refresh on timeout 355 * of AUTO_CNT = 1 prior to any transition to OFF mode. 356 */ 357 if ((omap_type() != OMAP2_DEVICE_TYPE_GP) 358 && (omap_rev() >= OMAP3430_REV_ES3_0)) 359 sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) & 360 ~(SDRC_POWER_AUTOCOUNT_MASK| 361 SDRC_POWER_CLKCTRL_MASK)) | 362 (1 << SDRC_POWER_AUTOCOUNT_SHIFT) | 363 SDRC_SELF_REFRESH_ON_AUTOCOUNT; 364 else 365 sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER); 366 367 sdrc_block_contents.cs_0 = 0x0; 368 sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0); 369 sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF); 370 sdrc_block_contents.emr_1_0 = 0x0; 371 sdrc_block_contents.emr_2_0 = 0x0; 372 sdrc_block_contents.emr_3_0 = 0x0; 373 sdrc_block_contents.actim_ctrla_0 = 374 sdrc_read_reg(SDRC_ACTIM_CTRL_A_0); 375 sdrc_block_contents.actim_ctrlb_0 = 376 sdrc_read_reg(SDRC_ACTIM_CTRL_B_0); 377 sdrc_block_contents.rfr_ctrl_0 = 378 sdrc_read_reg(SDRC_RFR_CTRL_0); 379 sdrc_block_contents.cs_1 = 0x0; 380 sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1); 381 sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF; 382 sdrc_block_contents.emr_1_1 = 0x0; 383 sdrc_block_contents.emr_2_1 = 0x0; 384 sdrc_block_contents.emr_3_1 = 0x0; 385 sdrc_block_contents.actim_ctrla_1 = 386 sdrc_read_reg(SDRC_ACTIM_CTRL_A_1); 387 sdrc_block_contents.actim_ctrlb_1 = 388 sdrc_read_reg(SDRC_ACTIM_CTRL_B_1); 389 sdrc_block_contents.rfr_ctrl_1 = 390 sdrc_read_reg(SDRC_RFR_CTRL_1); 391 sdrc_block_contents.dcdl_1_ctrl = 0x0; 392 sdrc_block_contents.dcdl_2_ctrl = 0x0; 393 sdrc_block_contents.flags = 0x0; 394 sdrc_block_contents.block_size = 0x0; 395 396 arm_context_addr = __pa_symbol(omap3_arm_context); 397 398 /* Copy all the contents to the scratchpad location */ 399 scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD); 400 memcpy_toio(scratchpad_address, &scratchpad_contents, 401 sizeof(scratchpad_contents)); 402 /* Scratchpad contents being 32 bits, a divide by 4 done here */ 403 memcpy_toio(scratchpad_address + 404 scratchpad_contents.prcm_block_offset, 405 &prcm_block_contents, sizeof(prcm_block_contents)); 406 memcpy_toio(scratchpad_address + 407 scratchpad_contents.sdrc_block_offset, 408 &sdrc_block_contents, sizeof(sdrc_block_contents)); 409 /* 410 * Copies the address of the location in SDRAM where ARM 411 * registers get saved during a MPU OFF transition. 412 */ 413 memcpy_toio(scratchpad_address + 414 scratchpad_contents.sdrc_block_offset + 415 sizeof(sdrc_block_contents), &arm_context_addr, 4); 416 } 417 418 void omap3_control_save_context(void) 419 { 420 control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG); 421 control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); 422 control_context.mem_dftrw0 = 423 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0); 424 control_context.mem_dftrw1 = 425 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1); 426 control_context.msuspendmux_0 = 427 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0); 428 control_context.msuspendmux_1 = 429 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1); 430 control_context.msuspendmux_2 = 431 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2); 432 control_context.msuspendmux_3 = 433 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3); 434 control_context.msuspendmux_4 = 435 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4); 436 control_context.msuspendmux_5 = 437 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5); 438 control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL); 439 control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1); 440 control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE); 441 control_context.iva2_bootaddr = 442 omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR); 443 control_context.iva2_bootmod = 444 omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD); 445 control_context.wkup_ctrl = omap_ctrl_readl(OMAP34XX_CONTROL_WKUP_CTRL); 446 control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0)); 447 control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1)); 448 control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2)); 449 control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3)); 450 control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4)); 451 control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5)); 452 control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6)); 453 control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7)); 454 control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8)); 455 control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0); 456 control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1); 457 control_context.dss_dpll_spreading = 458 omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING); 459 control_context.core_dpll_spreading = 460 omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING); 461 control_context.per_dpll_spreading = 462 omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING); 463 control_context.usbhost_dpll_spreading = 464 omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING); 465 control_context.pbias_lite = 466 omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE); 467 control_context.temp_sensor = 468 omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR); 469 control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4); 470 control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5); 471 control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI); 472 control_context.padconf_sys_nirq = 473 omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ); 474 } 475 476 void omap3_control_restore_context(void) 477 { 478 omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG); 479 omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0); 480 omap_ctrl_writel(control_context.mem_dftrw0, 481 OMAP343X_CONTROL_MEM_DFTRW0); 482 omap_ctrl_writel(control_context.mem_dftrw1, 483 OMAP343X_CONTROL_MEM_DFTRW1); 484 omap_ctrl_writel(control_context.msuspendmux_0, 485 OMAP2_CONTROL_MSUSPENDMUX_0); 486 omap_ctrl_writel(control_context.msuspendmux_1, 487 OMAP2_CONTROL_MSUSPENDMUX_1); 488 omap_ctrl_writel(control_context.msuspendmux_2, 489 OMAP2_CONTROL_MSUSPENDMUX_2); 490 omap_ctrl_writel(control_context.msuspendmux_3, 491 OMAP2_CONTROL_MSUSPENDMUX_3); 492 omap_ctrl_writel(control_context.msuspendmux_4, 493 OMAP2_CONTROL_MSUSPENDMUX_4); 494 omap_ctrl_writel(control_context.msuspendmux_5, 495 OMAP2_CONTROL_MSUSPENDMUX_5); 496 omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL); 497 omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1); 498 omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE); 499 omap_ctrl_writel(control_context.iva2_bootaddr, 500 OMAP343X_CONTROL_IVA2_BOOTADDR); 501 omap_ctrl_writel(control_context.iva2_bootmod, 502 OMAP343X_CONTROL_IVA2_BOOTMOD); 503 omap_ctrl_writel(control_context.wkup_ctrl, OMAP34XX_CONTROL_WKUP_CTRL); 504 omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0)); 505 omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1)); 506 omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2)); 507 omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3)); 508 omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4)); 509 omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5)); 510 omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6)); 511 omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7)); 512 omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8)); 513 omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0); 514 omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1); 515 omap_ctrl_writel(control_context.dss_dpll_spreading, 516 OMAP343X_CONTROL_DSS_DPLL_SPREADING); 517 omap_ctrl_writel(control_context.core_dpll_spreading, 518 OMAP343X_CONTROL_CORE_DPLL_SPREADING); 519 omap_ctrl_writel(control_context.per_dpll_spreading, 520 OMAP343X_CONTROL_PER_DPLL_SPREADING); 521 omap_ctrl_writel(control_context.usbhost_dpll_spreading, 522 OMAP343X_CONTROL_USBHOST_DPLL_SPREADING); 523 omap_ctrl_writel(control_context.pbias_lite, 524 OMAP343X_CONTROL_PBIAS_LITE); 525 omap_ctrl_writel(control_context.temp_sensor, 526 OMAP343X_CONTROL_TEMP_SENSOR); 527 omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4); 528 omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5); 529 omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI); 530 omap_ctrl_writel(control_context.padconf_sys_nirq, 531 OMAP343X_CONTROL_PADCONF_SYSNIRQ); 532 } 533 534 void omap3630_ctrl_disable_rta(void) 535 { 536 if (!cpu_is_omap3630()) 537 return; 538 omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL); 539 } 540 541 /** 542 * omap3_ctrl_save_padconf - save padconf registers to scratchpad RAM 543 * 544 * Tell the SCM to start saving the padconf registers, then wait for 545 * the process to complete. Returns 0 unconditionally, although it 546 * should also eventually be able to return -ETIMEDOUT, if the save 547 * does not complete. 548 * 549 * XXX This function is missing a timeout. What should it be? 550 */ 551 int omap3_ctrl_save_padconf(void) 552 { 553 u32 cpo; 554 555 /* Save the padconf registers */ 556 cpo = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF); 557 cpo |= START_PADCONF_SAVE; 558 omap_ctrl_writel(cpo, OMAP343X_CONTROL_PADCONF_OFF); 559 560 /* wait for the save to complete */ 561 while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS) 562 & PADCONF_SAVE_DONE)) 563 udelay(1); 564 565 return 0; 566 } 567 568 /** 569 * omap3_ctrl_set_iva_bootmode_idle - sets the IVA2 bootmode to idle 570 * 571 * Sets the bootmode for IVA2 to idle. This is needed by the PM code to 572 * force disable IVA2 so that it does not prevent any low-power states. 573 */ 574 static void __init omap3_ctrl_set_iva_bootmode_idle(void) 575 { 576 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, 577 OMAP343X_CONTROL_IVA2_BOOTMOD); 578 } 579 580 /** 581 * omap3_ctrl_setup_d2d_padconf - setup stacked modem pads for idle 582 * 583 * Sets up the pads controlling the stacked modem in such way that the 584 * device can enter idle. 585 */ 586 static void __init omap3_ctrl_setup_d2d_padconf(void) 587 { 588 u16 mask, padconf; 589 590 /* 591 * In a stand alone OMAP3430 where there is not a stacked 592 * modem for the D2D Idle Ack and D2D MStandby must be pulled 593 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and 594 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. 595 */ 596 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ 597 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); 598 padconf |= mask; 599 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); 600 601 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); 602 padconf |= mask; 603 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); 604 } 605 606 /** 607 * omap3_ctrl_init - does static initializations for control module 608 * 609 * Initializes system control module. This sets up the sysconfig autoidle, 610 * and sets up modem and iva2 so that they can be idled properly. 611 */ 612 void __init omap3_ctrl_init(void) 613 { 614 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); 615 616 omap3_ctrl_set_iva_bootmode_idle(); 617 618 omap3_ctrl_setup_d2d_padconf(); 619 } 620 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ 621 622 static unsigned long am43xx_control_reg_offsets[] = { 623 AM33XX_CONTROL_SYSCONFIG_OFFSET, 624 AM33XX_CONTROL_STATUS_OFFSET, 625 AM43XX_CONTROL_MPU_L2_CTRL_OFFSET, 626 AM33XX_CONTROL_CORE_SLDO_CTRL_OFFSET, 627 AM33XX_CONTROL_MPU_SLDO_CTRL_OFFSET, 628 AM33XX_CONTROL_CLK32KDIVRATIO_CTRL_OFFSET, 629 AM33XX_CONTROL_BANDGAP_CTRL_OFFSET, 630 AM33XX_CONTROL_BANDGAP_TRIM_OFFSET, 631 AM33XX_CONTROL_PLL_CLKINPULOW_CTRL_OFFSET, 632 AM33XX_CONTROL_MOSC_CTRL_OFFSET, 633 AM33XX_CONTROL_DEEPSLEEP_CTRL_OFFSET, 634 AM43XX_CONTROL_DISPLAY_PLL_SEL_OFFSET, 635 AM33XX_CONTROL_INIT_PRIORITY_0_OFFSET, 636 AM33XX_CONTROL_INIT_PRIORITY_1_OFFSET, 637 AM33XX_CONTROL_TPTC_CFG_OFFSET, 638 AM33XX_CONTROL_USB_CTRL0_OFFSET, 639 AM33XX_CONTROL_USB_CTRL1_OFFSET, 640 AM43XX_CONTROL_USB_CTRL2_OFFSET, 641 AM43XX_CONTROL_GMII_SEL_OFFSET, 642 AM43XX_CONTROL_MPUSS_CTRL_OFFSET, 643 AM43XX_CONTROL_TIMER_CASCADE_CTRL_OFFSET, 644 AM43XX_CONTROL_PWMSS_CTRL_OFFSET, 645 AM33XX_CONTROL_MREQPRIO_0_OFFSET, 646 AM33XX_CONTROL_MREQPRIO_1_OFFSET, 647 AM33XX_CONTROL_HW_EVENT_SEL_GRP1_OFFSET, 648 AM33XX_CONTROL_HW_EVENT_SEL_GRP2_OFFSET, 649 AM33XX_CONTROL_HW_EVENT_SEL_GRP3_OFFSET, 650 AM33XX_CONTROL_HW_EVENT_SEL_GRP4_OFFSET, 651 AM33XX_CONTROL_SMRT_CTRL_OFFSET, 652 AM33XX_CONTROL_MPUSS_HW_DEBUG_SEL_OFFSET, 653 AM43XX_CONTROL_CQDETECT_STS_OFFSET, 654 AM43XX_CONTROL_CQDETECT_STS2_OFFSET, 655 AM43XX_CONTROL_VTP_CTRL_OFFSET, 656 AM33XX_CONTROL_VREF_CTRL_OFFSET, 657 AM33XX_CONTROL_TPCC_EVT_MUX_0_3_OFFSET, 658 AM33XX_CONTROL_TPCC_EVT_MUX_4_7_OFFSET, 659 AM33XX_CONTROL_TPCC_EVT_MUX_8_11_OFFSET, 660 AM33XX_CONTROL_TPCC_EVT_MUX_12_15_OFFSET, 661 AM33XX_CONTROL_TPCC_EVT_MUX_16_19_OFFSET, 662 AM33XX_CONTROL_TPCC_EVT_MUX_20_23_OFFSET, 663 AM33XX_CONTROL_TPCC_EVT_MUX_24_27_OFFSET, 664 AM33XX_CONTROL_TPCC_EVT_MUX_28_31_OFFSET, 665 AM33XX_CONTROL_TPCC_EVT_MUX_32_35_OFFSET, 666 AM33XX_CONTROL_TPCC_EVT_MUX_36_39_OFFSET, 667 AM33XX_CONTROL_TPCC_EVT_MUX_40_43_OFFSET, 668 AM33XX_CONTROL_TPCC_EVT_MUX_44_47_OFFSET, 669 AM33XX_CONTROL_TPCC_EVT_MUX_48_51_OFFSET, 670 AM33XX_CONTROL_TPCC_EVT_MUX_52_55_OFFSET, 671 AM33XX_CONTROL_TPCC_EVT_MUX_56_59_OFFSET, 672 AM33XX_CONTROL_TPCC_EVT_MUX_60_63_OFFSET, 673 AM33XX_CONTROL_TIMER_EVT_CAPT_OFFSET, 674 AM33XX_CONTROL_ECAP_EVT_CAPT_OFFSET, 675 AM33XX_CONTROL_ADC_EVT_CAPT_OFFSET, 676 AM43XX_CONTROL_ADC1_EVT_CAPT_OFFSET, 677 AM33XX_CONTROL_RESET_ISO_OFFSET, 678 }; 679 680 static u32 am33xx_control_vals[ARRAY_SIZE(am43xx_control_reg_offsets)]; 681 682 /** 683 * am43xx_control_save_context - Save the wakeup domain registers 684 * 685 * Save the wkup domain registers 686 */ 687 static void am43xx_control_save_context(void) 688 { 689 int i; 690 691 for (i = 0; i < ARRAY_SIZE(am43xx_control_reg_offsets); i++) 692 am33xx_control_vals[i] = 693 omap_ctrl_readl(am43xx_control_reg_offsets[i]); 694 } 695 696 /** 697 * am43xx_control_restore_context - Restore the wakeup domain registers 698 * 699 * Restore the wkup domain registers 700 */ 701 static void am43xx_control_restore_context(void) 702 { 703 int i; 704 705 for (i = 0; i < ARRAY_SIZE(am43xx_control_reg_offsets); i++) 706 omap_ctrl_writel(am33xx_control_vals[i], 707 am43xx_control_reg_offsets[i]); 708 } 709 710 static int cpu_notifier(struct notifier_block *nb, unsigned long cmd, void *v) 711 { 712 switch (cmd) { 713 case CPU_CLUSTER_PM_ENTER: 714 if (enable_off_mode) 715 am43xx_control_save_context(); 716 break; 717 case CPU_CLUSTER_PM_EXIT: 718 if (enable_off_mode) 719 am43xx_control_restore_context(); 720 break; 721 } 722 723 return NOTIFY_OK; 724 } 725 726 struct control_init_data { 727 int index; 728 void __iomem *mem; 729 s16 offset; 730 }; 731 732 static struct control_init_data ctrl_data = { 733 .index = TI_CLKM_CTRL, 734 }; 735 736 static const struct control_init_data omap2_ctrl_data = { 737 .index = TI_CLKM_CTRL, 738 .offset = -OMAP2_CONTROL_GENERAL, 739 }; 740 741 static const struct control_init_data ctrl_aux_data = { 742 .index = TI_CLKM_CTRL_AUX, 743 }; 744 745 static const struct of_device_id omap_scrm_dt_match_table[] = { 746 { .compatible = "ti,am3-scm", .data = &ctrl_data }, 747 { .compatible = "ti,am4-scm", .data = &ctrl_data }, 748 { .compatible = "ti,omap2-scm", .data = &omap2_ctrl_data }, 749 { .compatible = "ti,omap3-scm", .data = &omap2_ctrl_data }, 750 { .compatible = "ti,dm814-scm", .data = &ctrl_data }, 751 { .compatible = "ti,dm816-scrm", .data = &ctrl_data }, 752 { .compatible = "ti,omap4-scm-core", .data = &ctrl_data }, 753 { .compatible = "ti,omap5-scm-core", .data = &ctrl_data }, 754 { .compatible = "ti,omap5-scm-wkup-pad-conf", .data = &ctrl_aux_data }, 755 { .compatible = "ti,dra7-scm-core", .data = &ctrl_data }, 756 { } 757 }; 758 759 /** 760 * omap2_control_base_init - initialize iomappings for the control driver 761 * 762 * Detects and initializes the iomappings for the control driver, based 763 * on the DT data. Returns 0 in success, negative error value 764 * otherwise. 765 */ 766 int __init omap2_control_base_init(void) 767 { 768 struct device_node *np; 769 const struct of_device_id *match; 770 struct control_init_data *data; 771 void __iomem *mem; 772 773 for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) { 774 data = (struct control_init_data *)match->data; 775 776 mem = of_iomap(np, 0); 777 if (!mem) 778 return -ENOMEM; 779 780 if (data->index == TI_CLKM_CTRL) { 781 omap2_ctrl_base = mem; 782 omap2_ctrl_offset = data->offset; 783 } 784 785 data->mem = mem; 786 } 787 788 return 0; 789 } 790 791 /** 792 * omap_control_init - low level init for the control driver 793 * 794 * Initializes the low level clock infrastructure for control driver. 795 * Returns 0 in success, negative error value in failure. 796 */ 797 int __init omap_control_init(void) 798 { 799 struct device_node *np, *scm_conf; 800 const struct of_device_id *match; 801 const struct omap_prcm_init_data *data; 802 int ret; 803 struct regmap *syscon; 804 static struct notifier_block nb; 805 806 for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) { 807 data = match->data; 808 809 /* 810 * Check if we have scm_conf node, if yes, use this to 811 * access clock registers. 812 */ 813 scm_conf = of_get_child_by_name(np, "scm_conf"); 814 815 if (scm_conf) { 816 syscon = syscon_node_to_regmap(scm_conf); 817 818 if (IS_ERR(syscon)) 819 return PTR_ERR(syscon); 820 821 if (of_get_child_by_name(scm_conf, "clocks")) { 822 ret = omap2_clk_provider_init(scm_conf, 823 data->index, 824 syscon, NULL); 825 if (ret) 826 return ret; 827 } 828 } else { 829 /* No scm_conf found, direct access */ 830 ret = omap2_clk_provider_init(np, data->index, NULL, 831 data->mem); 832 if (ret) 833 return ret; 834 } 835 } 836 837 /* Only AM43XX can lose ctrl registers context during rtc-ddr suspend */ 838 if (soc_is_am43xx()) { 839 nb.notifier_call = cpu_notifier; 840 cpu_pm_register_notifier(&nb); 841 } 842 843 return 0; 844 } 845 846 /** 847 * omap3_control_legacy_iomap_init - legacy iomap init for clock providers 848 * 849 * Legacy iomap init for clock provider. Needed only by legacy boot mode, 850 * where the base addresses are not parsed from DT, but still required 851 * by the clock driver to be setup properly. 852 */ 853 void __init omap3_control_legacy_iomap_init(void) 854 { 855 omap2_clk_legacy_provider_init(TI_CLKM_SCRM, omap2_ctrl_base); 856 } 857