xref: /openbmc/linux/arch/arm/mach-omap2/control.c (revision b6dcefde)
1 /*
2  * OMAP2/3 System Control Module register access
3  *
4  * Copyright (C) 2007 Texas Instruments, Inc.
5  * Copyright (C) 2007 Nokia Corporation
6  *
7  * Written by Paul Walmsley
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  */
13 #undef DEBUG
14 
15 #include <linux/kernel.h>
16 #include <linux/io.h>
17 
18 #include <plat/common.h>
19 #include <plat/control.h>
20 #include <plat/sdrc.h>
21 #include "cm-regbits-34xx.h"
22 #include "prm-regbits-34xx.h"
23 #include "cm.h"
24 #include "prm.h"
25 #include "sdrc.h"
26 
27 static void __iomem *omap2_ctrl_base;
28 
29 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
30 struct omap3_scratchpad {
31 	u32 boot_config_ptr;
32 	u32 public_restore_ptr;
33 	u32 secure_ram_restore_ptr;
34 	u32 sdrc_module_semaphore;
35 	u32 prcm_block_offset;
36 	u32 sdrc_block_offset;
37 };
38 
39 struct omap3_scratchpad_prcm_block {
40 	u32 prm_clksrc_ctrl;
41 	u32 prm_clksel;
42 	u32 cm_clksel_core;
43 	u32 cm_clksel_wkup;
44 	u32 cm_clken_pll;
45 	u32 cm_autoidle_pll;
46 	u32 cm_clksel1_pll;
47 	u32 cm_clksel2_pll;
48 	u32 cm_clksel3_pll;
49 	u32 cm_clken_pll_mpu;
50 	u32 cm_autoidle_pll_mpu;
51 	u32 cm_clksel1_pll_mpu;
52 	u32 cm_clksel2_pll_mpu;
53 	u32 prcm_block_size;
54 };
55 
56 struct omap3_scratchpad_sdrc_block {
57 	u16 sysconfig;
58 	u16 cs_cfg;
59 	u16 sharing;
60 	u16 err_type;
61 	u32 dll_a_ctrl;
62 	u32 dll_b_ctrl;
63 	u32 power;
64 	u32 cs_0;
65 	u32 mcfg_0;
66 	u16 mr_0;
67 	u16 emr_1_0;
68 	u16 emr_2_0;
69 	u16 emr_3_0;
70 	u32 actim_ctrla_0;
71 	u32 actim_ctrlb_0;
72 	u32 rfr_ctrl_0;
73 	u32 cs_1;
74 	u32 mcfg_1;
75 	u16 mr_1;
76 	u16 emr_1_1;
77 	u16 emr_2_1;
78 	u16 emr_3_1;
79 	u32 actim_ctrla_1;
80 	u32 actim_ctrlb_1;
81 	u32 rfr_ctrl_1;
82 	u16 dcdl_1_ctrl;
83 	u16 dcdl_2_ctrl;
84 	u32 flags;
85 	u32 block_size;
86 };
87 
88 void *omap3_secure_ram_storage;
89 
90 /*
91  * This is used to store ARM registers in SDRAM before attempting
92  * an MPU OFF. The save and restore happens from the SRAM sleep code.
93  * The address is stored in scratchpad, so that it can be used
94  * during the restore path.
95  */
96 u32 omap3_arm_context[128];
97 
98 struct omap3_control_regs {
99 	u32 sysconfig;
100 	u32 devconf0;
101 	u32 mem_dftrw0;
102 	u32 mem_dftrw1;
103 	u32 msuspendmux_0;
104 	u32 msuspendmux_1;
105 	u32 msuspendmux_2;
106 	u32 msuspendmux_3;
107 	u32 msuspendmux_4;
108 	u32 msuspendmux_5;
109 	u32 sec_ctrl;
110 	u32 devconf1;
111 	u32 csirxfe;
112 	u32 iva2_bootaddr;
113 	u32 iva2_bootmod;
114 	u32 debobs_0;
115 	u32 debobs_1;
116 	u32 debobs_2;
117 	u32 debobs_3;
118 	u32 debobs_4;
119 	u32 debobs_5;
120 	u32 debobs_6;
121 	u32 debobs_7;
122 	u32 debobs_8;
123 	u32 prog_io0;
124 	u32 prog_io1;
125 	u32 dss_dpll_spreading;
126 	u32 core_dpll_spreading;
127 	u32 per_dpll_spreading;
128 	u32 usbhost_dpll_spreading;
129 	u32 pbias_lite;
130 	u32 temp_sensor;
131 	u32 sramldo4;
132 	u32 sramldo5;
133 	u32 csi;
134 };
135 
136 static struct omap3_control_regs control_context;
137 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
138 
139 #define OMAP_CTRL_REGADDR(reg)		(omap2_ctrl_base + (reg))
140 
141 void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
142 {
143 	omap2_ctrl_base = omap2_globals->ctrl;
144 }
145 
146 void __iomem *omap_ctrl_base_get(void)
147 {
148 	return omap2_ctrl_base;
149 }
150 
151 u8 omap_ctrl_readb(u16 offset)
152 {
153 	return __raw_readb(OMAP_CTRL_REGADDR(offset));
154 }
155 
156 u16 omap_ctrl_readw(u16 offset)
157 {
158 	return __raw_readw(OMAP_CTRL_REGADDR(offset));
159 }
160 
161 u32 omap_ctrl_readl(u16 offset)
162 {
163 	return __raw_readl(OMAP_CTRL_REGADDR(offset));
164 }
165 
166 void omap_ctrl_writeb(u8 val, u16 offset)
167 {
168 	__raw_writeb(val, OMAP_CTRL_REGADDR(offset));
169 }
170 
171 void omap_ctrl_writew(u16 val, u16 offset)
172 {
173 	__raw_writew(val, OMAP_CTRL_REGADDR(offset));
174 }
175 
176 void omap_ctrl_writel(u32 val, u16 offset)
177 {
178 	__raw_writel(val, OMAP_CTRL_REGADDR(offset));
179 }
180 
181 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
182 /*
183  * Clears the scratchpad contents in case of cold boot-
184  * called during bootup
185  */
186 void omap3_clear_scratchpad_contents(void)
187 {
188 	u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
189 	u32 *v_addr;
190 	u32 offset = 0;
191 	v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
192 	if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
193 		OMAP3430_GLOBAL_COLD_RST) {
194 		for ( ; offset <= max_offset; offset += 0x4)
195 			__raw_writel(0x0, (v_addr + offset));
196 		prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST, OMAP3430_GR_MOD,
197 			OMAP3_PRM_RSTST_OFFSET);
198 	}
199 }
200 
201 /* Populate the scratchpad structure with restore structure */
202 void omap3_save_scratchpad_contents(void)
203 {
204 	void * __iomem scratchpad_address;
205 	u32 arm_context_addr;
206 	struct omap3_scratchpad scratchpad_contents;
207 	struct omap3_scratchpad_prcm_block prcm_block_contents;
208 	struct omap3_scratchpad_sdrc_block sdrc_block_contents;
209 
210 	/* Populate the Scratchpad contents */
211 	scratchpad_contents.boot_config_ptr = 0x0;
212 	if (omap_rev() != OMAP3430_REV_ES3_0 &&
213 					omap_rev() != OMAP3430_REV_ES3_1)
214 		scratchpad_contents.public_restore_ptr =
215 			virt_to_phys(get_restore_pointer());
216 	else
217 		scratchpad_contents.public_restore_ptr =
218 			virt_to_phys(get_es3_restore_pointer());
219 	if (omap_type() == OMAP2_DEVICE_TYPE_GP)
220 		scratchpad_contents.secure_ram_restore_ptr = 0x0;
221 	else
222 		scratchpad_contents.secure_ram_restore_ptr =
223 			(u32) __pa(omap3_secure_ram_storage);
224 	scratchpad_contents.sdrc_module_semaphore = 0x0;
225 	scratchpad_contents.prcm_block_offset = 0x2C;
226 	scratchpad_contents.sdrc_block_offset = 0x64;
227 
228 	/* Populate the PRCM block contents */
229 	prcm_block_contents.prm_clksrc_ctrl = prm_read_mod_reg(OMAP3430_GR_MOD,
230 			OMAP3_PRM_CLKSRC_CTRL_OFFSET);
231 	prcm_block_contents.prm_clksel = prm_read_mod_reg(OMAP3430_CCR_MOD,
232 			OMAP3_PRM_CLKSEL_OFFSET);
233 	prcm_block_contents.cm_clksel_core =
234 			cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
235 	prcm_block_contents.cm_clksel_wkup =
236 			cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
237 	prcm_block_contents.cm_clken_pll =
238 			cm_read_mod_reg(PLL_MOD, CM_CLKEN);
239 	prcm_block_contents.cm_autoidle_pll =
240 			cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL);
241 	prcm_block_contents.cm_clksel1_pll =
242 			cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
243 	prcm_block_contents.cm_clksel2_pll =
244 			cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
245 	prcm_block_contents.cm_clksel3_pll =
246 			cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
247 	prcm_block_contents.cm_clken_pll_mpu =
248 			cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
249 	prcm_block_contents.cm_autoidle_pll_mpu =
250 			cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
251 	prcm_block_contents.cm_clksel1_pll_mpu =
252 			cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
253 	prcm_block_contents.cm_clksel2_pll_mpu =
254 			cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
255 	prcm_block_contents.prcm_block_size = 0x0;
256 
257 	/* Populate the SDRC block contents */
258 	sdrc_block_contents.sysconfig =
259 			(sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF);
260 	sdrc_block_contents.cs_cfg =
261 			(sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF);
262 	sdrc_block_contents.sharing =
263 			(sdrc_read_reg(SDRC_SHARING) & 0xFFFF);
264 	sdrc_block_contents.err_type =
265 			(sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF);
266 	sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL);
267 	sdrc_block_contents.dll_b_ctrl = 0x0;
268 	/*
269 	 * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should
270 	 * be programed to issue automatic self refresh on timeout
271 	 * of AUTO_CNT = 1 prior to any transition to OFF mode.
272 	 */
273 	if ((omap_type() != OMAP2_DEVICE_TYPE_GP)
274 			&& (omap_rev() >= OMAP3430_REV_ES3_0))
275 		sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) &
276 				~(SDRC_POWER_AUTOCOUNT_MASK|
277 				SDRC_POWER_CLKCTRL_MASK)) |
278 				(1 << SDRC_POWER_AUTOCOUNT_SHIFT) |
279 				SDRC_SELF_REFRESH_ON_AUTOCOUNT;
280 	else
281 		sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER);
282 
283 	sdrc_block_contents.cs_0 = 0x0;
284 	sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0);
285 	sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF);
286 	sdrc_block_contents.emr_1_0 = 0x0;
287 	sdrc_block_contents.emr_2_0 = 0x0;
288 	sdrc_block_contents.emr_3_0 = 0x0;
289 	sdrc_block_contents.actim_ctrla_0 =
290 			sdrc_read_reg(SDRC_ACTIM_CTRL_A_0);
291 	sdrc_block_contents.actim_ctrlb_0 =
292 			sdrc_read_reg(SDRC_ACTIM_CTRL_B_0);
293 	sdrc_block_contents.rfr_ctrl_0 =
294 			sdrc_read_reg(SDRC_RFR_CTRL_0);
295 	sdrc_block_contents.cs_1 = 0x0;
296 	sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1);
297 	sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF;
298 	sdrc_block_contents.emr_1_1 = 0x0;
299 	sdrc_block_contents.emr_2_1 = 0x0;
300 	sdrc_block_contents.emr_3_1 = 0x0;
301 	sdrc_block_contents.actim_ctrla_1 =
302 			sdrc_read_reg(SDRC_ACTIM_CTRL_A_1);
303 	sdrc_block_contents.actim_ctrlb_1 =
304 			sdrc_read_reg(SDRC_ACTIM_CTRL_B_1);
305 	sdrc_block_contents.rfr_ctrl_1 =
306 			sdrc_read_reg(SDRC_RFR_CTRL_1);
307 	sdrc_block_contents.dcdl_1_ctrl = 0x0;
308 	sdrc_block_contents.dcdl_2_ctrl = 0x0;
309 	sdrc_block_contents.flags = 0x0;
310 	sdrc_block_contents.block_size = 0x0;
311 
312 	arm_context_addr = virt_to_phys(omap3_arm_context);
313 
314 	/* Copy all the contents to the scratchpad location */
315 	scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
316 	memcpy_toio(scratchpad_address, &scratchpad_contents,
317 		 sizeof(scratchpad_contents));
318 	/* Scratchpad contents being 32 bits, a divide by 4 done here */
319 	memcpy_toio(scratchpad_address +
320 		scratchpad_contents.prcm_block_offset,
321 		&prcm_block_contents, sizeof(prcm_block_contents));
322 	memcpy_toio(scratchpad_address +
323 		scratchpad_contents.sdrc_block_offset,
324 		&sdrc_block_contents, sizeof(sdrc_block_contents));
325 	/*
326 	 * Copies the address of the location in SDRAM where ARM
327 	 * registers get saved during a MPU OFF transition.
328 	 */
329 	memcpy_toio(scratchpad_address +
330 		scratchpad_contents.sdrc_block_offset +
331 		sizeof(sdrc_block_contents), &arm_context_addr, 4);
332 }
333 
334 void omap3_control_save_context(void)
335 {
336 	control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG);
337 	control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
338 	control_context.mem_dftrw0 =
339 			omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0);
340 	control_context.mem_dftrw1 =
341 			omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1);
342 	control_context.msuspendmux_0 =
343 			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0);
344 	control_context.msuspendmux_1 =
345 			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1);
346 	control_context.msuspendmux_2 =
347 			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2);
348 	control_context.msuspendmux_3 =
349 			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3);
350 	control_context.msuspendmux_4 =
351 			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4);
352 	control_context.msuspendmux_5 =
353 			omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5);
354 	control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL);
355 	control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);
356 	control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE);
357 	control_context.iva2_bootaddr =
358 			omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR);
359 	control_context.iva2_bootmod =
360 			omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD);
361 	control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0));
362 	control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1));
363 	control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2));
364 	control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3));
365 	control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4));
366 	control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5));
367 	control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6));
368 	control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7));
369 	control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8));
370 	control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0);
371 	control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
372 	control_context.dss_dpll_spreading =
373 			omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING);
374 	control_context.core_dpll_spreading =
375 			omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING);
376 	control_context.per_dpll_spreading =
377 			omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING);
378 	control_context.usbhost_dpll_spreading =
379 		omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
380 	control_context.pbias_lite =
381 			omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE);
382 	control_context.temp_sensor =
383 			omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR);
384 	control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4);
385 	control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5);
386 	control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI);
387 	return;
388 }
389 
390 void omap3_control_restore_context(void)
391 {
392 	omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG);
393 	omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0);
394 	omap_ctrl_writel(control_context.mem_dftrw0,
395 					OMAP343X_CONTROL_MEM_DFTRW0);
396 	omap_ctrl_writel(control_context.mem_dftrw1,
397 					OMAP343X_CONTROL_MEM_DFTRW1);
398 	omap_ctrl_writel(control_context.msuspendmux_0,
399 					OMAP2_CONTROL_MSUSPENDMUX_0);
400 	omap_ctrl_writel(control_context.msuspendmux_1,
401 					OMAP2_CONTROL_MSUSPENDMUX_1);
402 	omap_ctrl_writel(control_context.msuspendmux_2,
403 					OMAP2_CONTROL_MSUSPENDMUX_2);
404 	omap_ctrl_writel(control_context.msuspendmux_3,
405 					OMAP2_CONTROL_MSUSPENDMUX_3);
406 	omap_ctrl_writel(control_context.msuspendmux_4,
407 					OMAP2_CONTROL_MSUSPENDMUX_4);
408 	omap_ctrl_writel(control_context.msuspendmux_5,
409 					OMAP2_CONTROL_MSUSPENDMUX_5);
410 	omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL);
411 	omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1);
412 	omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE);
413 	omap_ctrl_writel(control_context.iva2_bootaddr,
414 					OMAP343X_CONTROL_IVA2_BOOTADDR);
415 	omap_ctrl_writel(control_context.iva2_bootmod,
416 					OMAP343X_CONTROL_IVA2_BOOTMOD);
417 	omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0));
418 	omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1));
419 	omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2));
420 	omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3));
421 	omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4));
422 	omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5));
423 	omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6));
424 	omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7));
425 	omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8));
426 	omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0);
427 	omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1);
428 	omap_ctrl_writel(control_context.dss_dpll_spreading,
429 					OMAP343X_CONTROL_DSS_DPLL_SPREADING);
430 	omap_ctrl_writel(control_context.core_dpll_spreading,
431 					OMAP343X_CONTROL_CORE_DPLL_SPREADING);
432 	omap_ctrl_writel(control_context.per_dpll_spreading,
433 					OMAP343X_CONTROL_PER_DPLL_SPREADING);
434 	omap_ctrl_writel(control_context.usbhost_dpll_spreading,
435 				OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
436 	omap_ctrl_writel(control_context.pbias_lite,
437 					OMAP343X_CONTROL_PBIAS_LITE);
438 	omap_ctrl_writel(control_context.temp_sensor,
439 					OMAP343X_CONTROL_TEMP_SENSOR);
440 	omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4);
441 	omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5);
442 	omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
443 	return;
444 }
445 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
446