1 /* 2 * OMAP2/3 System Control Module register access 3 * 4 * Copyright (C) 2007, 2012 Texas Instruments, Inc. 5 * Copyright (C) 2007 Nokia Corporation 6 * 7 * Written by Paul Walmsley 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 #undef DEBUG 14 15 #include <linux/kernel.h> 16 #include <linux/io.h> 17 18 #include "soc.h" 19 #include "iomap.h" 20 #include "common.h" 21 #include "cm-regbits-34xx.h" 22 #include "prm-regbits-34xx.h" 23 #include "prm3xxx.h" 24 #include "cm3xxx.h" 25 #include "sdrc.h" 26 #include "pm.h" 27 #include "control.h" 28 29 /* Used by omap3_ctrl_save_padconf() */ 30 #define START_PADCONF_SAVE 0x2 31 #define PADCONF_SAVE_DONE 0x1 32 33 static void __iomem *omap2_ctrl_base; 34 static void __iomem *omap4_ctrl_pad_base; 35 36 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 37 struct omap3_scratchpad { 38 u32 boot_config_ptr; 39 u32 public_restore_ptr; 40 u32 secure_ram_restore_ptr; 41 u32 sdrc_module_semaphore; 42 u32 prcm_block_offset; 43 u32 sdrc_block_offset; 44 }; 45 46 struct omap3_scratchpad_prcm_block { 47 u32 prm_contents[2]; 48 u32 cm_contents[11]; 49 u32 prcm_block_size; 50 }; 51 52 struct omap3_scratchpad_sdrc_block { 53 u16 sysconfig; 54 u16 cs_cfg; 55 u16 sharing; 56 u16 err_type; 57 u32 dll_a_ctrl; 58 u32 dll_b_ctrl; 59 u32 power; 60 u32 cs_0; 61 u32 mcfg_0; 62 u16 mr_0; 63 u16 emr_1_0; 64 u16 emr_2_0; 65 u16 emr_3_0; 66 u32 actim_ctrla_0; 67 u32 actim_ctrlb_0; 68 u32 rfr_ctrl_0; 69 u32 cs_1; 70 u32 mcfg_1; 71 u16 mr_1; 72 u16 emr_1_1; 73 u16 emr_2_1; 74 u16 emr_3_1; 75 u32 actim_ctrla_1; 76 u32 actim_ctrlb_1; 77 u32 rfr_ctrl_1; 78 u16 dcdl_1_ctrl; 79 u16 dcdl_2_ctrl; 80 u32 flags; 81 u32 block_size; 82 }; 83 84 void *omap3_secure_ram_storage; 85 86 /* 87 * This is used to store ARM registers in SDRAM before attempting 88 * an MPU OFF. The save and restore happens from the SRAM sleep code. 89 * The address is stored in scratchpad, so that it can be used 90 * during the restore path. 91 */ 92 u32 omap3_arm_context[128]; 93 94 struct omap3_control_regs { 95 u32 sysconfig; 96 u32 devconf0; 97 u32 mem_dftrw0; 98 u32 mem_dftrw1; 99 u32 msuspendmux_0; 100 u32 msuspendmux_1; 101 u32 msuspendmux_2; 102 u32 msuspendmux_3; 103 u32 msuspendmux_4; 104 u32 msuspendmux_5; 105 u32 sec_ctrl; 106 u32 devconf1; 107 u32 csirxfe; 108 u32 iva2_bootaddr; 109 u32 iva2_bootmod; 110 u32 debobs_0; 111 u32 debobs_1; 112 u32 debobs_2; 113 u32 debobs_3; 114 u32 debobs_4; 115 u32 debobs_5; 116 u32 debobs_6; 117 u32 debobs_7; 118 u32 debobs_8; 119 u32 prog_io0; 120 u32 prog_io1; 121 u32 dss_dpll_spreading; 122 u32 core_dpll_spreading; 123 u32 per_dpll_spreading; 124 u32 usbhost_dpll_spreading; 125 u32 pbias_lite; 126 u32 temp_sensor; 127 u32 sramldo4; 128 u32 sramldo5; 129 u32 csi; 130 u32 padconf_sys_nirq; 131 }; 132 133 static struct omap3_control_regs control_context; 134 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ 135 136 #define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg)) 137 #define OMAP4_CTRL_PAD_REGADDR(reg) (omap4_ctrl_pad_base + (reg)) 138 139 void __init omap2_set_globals_control(void __iomem *ctrl, 140 void __iomem *ctrl_pad) 141 { 142 omap2_ctrl_base = ctrl; 143 omap4_ctrl_pad_base = ctrl_pad; 144 } 145 146 void __iomem *omap_ctrl_base_get(void) 147 { 148 return omap2_ctrl_base; 149 } 150 151 u8 omap_ctrl_readb(u16 offset) 152 { 153 return readb_relaxed(OMAP_CTRL_REGADDR(offset)); 154 } 155 156 u16 omap_ctrl_readw(u16 offset) 157 { 158 return readw_relaxed(OMAP_CTRL_REGADDR(offset)); 159 } 160 161 u32 omap_ctrl_readl(u16 offset) 162 { 163 return readl_relaxed(OMAP_CTRL_REGADDR(offset)); 164 } 165 166 void omap_ctrl_writeb(u8 val, u16 offset) 167 { 168 writeb_relaxed(val, OMAP_CTRL_REGADDR(offset)); 169 } 170 171 void omap_ctrl_writew(u16 val, u16 offset) 172 { 173 writew_relaxed(val, OMAP_CTRL_REGADDR(offset)); 174 } 175 176 void omap_ctrl_writel(u32 val, u16 offset) 177 { 178 writel_relaxed(val, OMAP_CTRL_REGADDR(offset)); 179 } 180 181 /* 182 * On OMAP4 control pad are not addressable from control 183 * core base. So the common omap_ctrl_read/write APIs breaks 184 * Hence export separate APIs to manage the omap4 pad control 185 * registers. This APIs will work only for OMAP4 186 */ 187 188 u32 omap4_ctrl_pad_readl(u16 offset) 189 { 190 return readl_relaxed(OMAP4_CTRL_PAD_REGADDR(offset)); 191 } 192 193 void omap4_ctrl_pad_writel(u32 val, u16 offset) 194 { 195 writel_relaxed(val, OMAP4_CTRL_PAD_REGADDR(offset)); 196 } 197 198 #ifdef CONFIG_ARCH_OMAP3 199 200 /** 201 * omap3_ctrl_write_boot_mode - set scratchpad boot mode for the next boot 202 * @bootmode: 8-bit value to pass to some boot code 203 * 204 * Set the bootmode in the scratchpad RAM. This is used after the 205 * system restarts. Not sure what actually uses this - it may be the 206 * bootloader, rather than the boot ROM - contrary to the preserved 207 * comment below. No return value. 208 */ 209 void omap3_ctrl_write_boot_mode(u8 bootmode) 210 { 211 u32 l; 212 213 l = ('B' << 24) | ('M' << 16) | bootmode; 214 215 /* 216 * Reserve the first word in scratchpad for communicating 217 * with the boot ROM. A pointer to a data structure 218 * describing the boot process can be stored there, 219 * cf. OMAP34xx TRM, Initialization / Software Booting 220 * Configuration. 221 * 222 * XXX This should use some omap_ctrl_writel()-type function 223 */ 224 writel_relaxed(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4)); 225 } 226 227 #endif 228 229 /** 230 * omap_ctrl_write_dsp_boot_addr - set boot address for a remote processor 231 * @bootaddr: physical address of the boot loader 232 * 233 * Set boot address for the boot loader of a supported processor 234 * when a power ON sequence occurs. 235 */ 236 void omap_ctrl_write_dsp_boot_addr(u32 bootaddr) 237 { 238 u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTADDR : 239 cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTADDR : 240 cpu_is_omap44xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR : 241 soc_is_omap54xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR : 242 0; 243 244 if (!offset) { 245 pr_err("%s: unsupported omap type\n", __func__); 246 return; 247 } 248 249 omap_ctrl_writel(bootaddr, offset); 250 } 251 252 /** 253 * omap_ctrl_write_dsp_boot_mode - set boot mode for a remote processor 254 * @bootmode: 8-bit value to pass to some boot code 255 * 256 * Sets boot mode for the boot loader of a supported processor 257 * when a power ON sequence occurs. 258 */ 259 void omap_ctrl_write_dsp_boot_mode(u8 bootmode) 260 { 261 u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTMOD : 262 cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTMOD : 263 0; 264 265 if (!offset) { 266 pr_err("%s: unsupported omap type\n", __func__); 267 return; 268 } 269 270 omap_ctrl_writel(bootmode, offset); 271 } 272 273 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 274 /* 275 * Clears the scratchpad contents in case of cold boot- 276 * called during bootup 277 */ 278 void omap3_clear_scratchpad_contents(void) 279 { 280 u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET; 281 void __iomem *v_addr; 282 u32 offset = 0; 283 284 v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM); 285 if (omap3xxx_prm_clear_global_cold_reset()) { 286 for ( ; offset <= max_offset; offset += 0x4) 287 writel_relaxed(0x0, (v_addr + offset)); 288 } 289 } 290 291 /* Populate the scratchpad structure with restore structure */ 292 void omap3_save_scratchpad_contents(void) 293 { 294 void __iomem *scratchpad_address; 295 u32 arm_context_addr; 296 struct omap3_scratchpad scratchpad_contents; 297 struct omap3_scratchpad_prcm_block prcm_block_contents; 298 struct omap3_scratchpad_sdrc_block sdrc_block_contents; 299 300 /* 301 * Populate the Scratchpad contents 302 * 303 * The "get_*restore_pointer" functions are used to provide a 304 * physical restore address where the ROM code jumps while waking 305 * up from MPU OFF/OSWR state. 306 * The restore pointer is stored into the scratchpad. 307 */ 308 scratchpad_contents.boot_config_ptr = 0x0; 309 if (cpu_is_omap3630()) 310 scratchpad_contents.public_restore_ptr = 311 virt_to_phys(omap3_restore_3630); 312 else if (omap_rev() != OMAP3430_REV_ES3_0 && 313 omap_rev() != OMAP3430_REV_ES3_1 && 314 omap_rev() != OMAP3430_REV_ES3_1_2) 315 scratchpad_contents.public_restore_ptr = 316 virt_to_phys(omap3_restore); 317 else 318 scratchpad_contents.public_restore_ptr = 319 virt_to_phys(omap3_restore_es3); 320 321 if (omap_type() == OMAP2_DEVICE_TYPE_GP) 322 scratchpad_contents.secure_ram_restore_ptr = 0x0; 323 else 324 scratchpad_contents.secure_ram_restore_ptr = 325 (u32) __pa(omap3_secure_ram_storage); 326 scratchpad_contents.sdrc_module_semaphore = 0x0; 327 scratchpad_contents.prcm_block_offset = 0x2C; 328 scratchpad_contents.sdrc_block_offset = 0x64; 329 330 /* Populate the PRCM block contents */ 331 omap3_prm_save_scratchpad_contents(prcm_block_contents.prm_contents); 332 omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents); 333 334 prcm_block_contents.prcm_block_size = 0x0; 335 336 /* Populate the SDRC block contents */ 337 sdrc_block_contents.sysconfig = 338 (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF); 339 sdrc_block_contents.cs_cfg = 340 (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF); 341 sdrc_block_contents.sharing = 342 (sdrc_read_reg(SDRC_SHARING) & 0xFFFF); 343 sdrc_block_contents.err_type = 344 (sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF); 345 sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL); 346 sdrc_block_contents.dll_b_ctrl = 0x0; 347 /* 348 * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should 349 * be programed to issue automatic self refresh on timeout 350 * of AUTO_CNT = 1 prior to any transition to OFF mode. 351 */ 352 if ((omap_type() != OMAP2_DEVICE_TYPE_GP) 353 && (omap_rev() >= OMAP3430_REV_ES3_0)) 354 sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) & 355 ~(SDRC_POWER_AUTOCOUNT_MASK| 356 SDRC_POWER_CLKCTRL_MASK)) | 357 (1 << SDRC_POWER_AUTOCOUNT_SHIFT) | 358 SDRC_SELF_REFRESH_ON_AUTOCOUNT; 359 else 360 sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER); 361 362 sdrc_block_contents.cs_0 = 0x0; 363 sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0); 364 sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF); 365 sdrc_block_contents.emr_1_0 = 0x0; 366 sdrc_block_contents.emr_2_0 = 0x0; 367 sdrc_block_contents.emr_3_0 = 0x0; 368 sdrc_block_contents.actim_ctrla_0 = 369 sdrc_read_reg(SDRC_ACTIM_CTRL_A_0); 370 sdrc_block_contents.actim_ctrlb_0 = 371 sdrc_read_reg(SDRC_ACTIM_CTRL_B_0); 372 sdrc_block_contents.rfr_ctrl_0 = 373 sdrc_read_reg(SDRC_RFR_CTRL_0); 374 sdrc_block_contents.cs_1 = 0x0; 375 sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1); 376 sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF; 377 sdrc_block_contents.emr_1_1 = 0x0; 378 sdrc_block_contents.emr_2_1 = 0x0; 379 sdrc_block_contents.emr_3_1 = 0x0; 380 sdrc_block_contents.actim_ctrla_1 = 381 sdrc_read_reg(SDRC_ACTIM_CTRL_A_1); 382 sdrc_block_contents.actim_ctrlb_1 = 383 sdrc_read_reg(SDRC_ACTIM_CTRL_B_1); 384 sdrc_block_contents.rfr_ctrl_1 = 385 sdrc_read_reg(SDRC_RFR_CTRL_1); 386 sdrc_block_contents.dcdl_1_ctrl = 0x0; 387 sdrc_block_contents.dcdl_2_ctrl = 0x0; 388 sdrc_block_contents.flags = 0x0; 389 sdrc_block_contents.block_size = 0x0; 390 391 arm_context_addr = virt_to_phys(omap3_arm_context); 392 393 /* Copy all the contents to the scratchpad location */ 394 scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD); 395 memcpy_toio(scratchpad_address, &scratchpad_contents, 396 sizeof(scratchpad_contents)); 397 /* Scratchpad contents being 32 bits, a divide by 4 done here */ 398 memcpy_toio(scratchpad_address + 399 scratchpad_contents.prcm_block_offset, 400 &prcm_block_contents, sizeof(prcm_block_contents)); 401 memcpy_toio(scratchpad_address + 402 scratchpad_contents.sdrc_block_offset, 403 &sdrc_block_contents, sizeof(sdrc_block_contents)); 404 /* 405 * Copies the address of the location in SDRAM where ARM 406 * registers get saved during a MPU OFF transition. 407 */ 408 memcpy_toio(scratchpad_address + 409 scratchpad_contents.sdrc_block_offset + 410 sizeof(sdrc_block_contents), &arm_context_addr, 4); 411 } 412 413 void omap3_control_save_context(void) 414 { 415 control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG); 416 control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); 417 control_context.mem_dftrw0 = 418 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0); 419 control_context.mem_dftrw1 = 420 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1); 421 control_context.msuspendmux_0 = 422 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0); 423 control_context.msuspendmux_1 = 424 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1); 425 control_context.msuspendmux_2 = 426 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2); 427 control_context.msuspendmux_3 = 428 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3); 429 control_context.msuspendmux_4 = 430 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4); 431 control_context.msuspendmux_5 = 432 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5); 433 control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL); 434 control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1); 435 control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE); 436 control_context.iva2_bootaddr = 437 omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR); 438 control_context.iva2_bootmod = 439 omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD); 440 control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0)); 441 control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1)); 442 control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2)); 443 control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3)); 444 control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4)); 445 control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5)); 446 control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6)); 447 control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7)); 448 control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8)); 449 control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0); 450 control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1); 451 control_context.dss_dpll_spreading = 452 omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING); 453 control_context.core_dpll_spreading = 454 omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING); 455 control_context.per_dpll_spreading = 456 omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING); 457 control_context.usbhost_dpll_spreading = 458 omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING); 459 control_context.pbias_lite = 460 omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE); 461 control_context.temp_sensor = 462 omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR); 463 control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4); 464 control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5); 465 control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI); 466 control_context.padconf_sys_nirq = 467 omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ); 468 } 469 470 void omap3_control_restore_context(void) 471 { 472 omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG); 473 omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0); 474 omap_ctrl_writel(control_context.mem_dftrw0, 475 OMAP343X_CONTROL_MEM_DFTRW0); 476 omap_ctrl_writel(control_context.mem_dftrw1, 477 OMAP343X_CONTROL_MEM_DFTRW1); 478 omap_ctrl_writel(control_context.msuspendmux_0, 479 OMAP2_CONTROL_MSUSPENDMUX_0); 480 omap_ctrl_writel(control_context.msuspendmux_1, 481 OMAP2_CONTROL_MSUSPENDMUX_1); 482 omap_ctrl_writel(control_context.msuspendmux_2, 483 OMAP2_CONTROL_MSUSPENDMUX_2); 484 omap_ctrl_writel(control_context.msuspendmux_3, 485 OMAP2_CONTROL_MSUSPENDMUX_3); 486 omap_ctrl_writel(control_context.msuspendmux_4, 487 OMAP2_CONTROL_MSUSPENDMUX_4); 488 omap_ctrl_writel(control_context.msuspendmux_5, 489 OMAP2_CONTROL_MSUSPENDMUX_5); 490 omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL); 491 omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1); 492 omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE); 493 omap_ctrl_writel(control_context.iva2_bootaddr, 494 OMAP343X_CONTROL_IVA2_BOOTADDR); 495 omap_ctrl_writel(control_context.iva2_bootmod, 496 OMAP343X_CONTROL_IVA2_BOOTMOD); 497 omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0)); 498 omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1)); 499 omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2)); 500 omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3)); 501 omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4)); 502 omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5)); 503 omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6)); 504 omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7)); 505 omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8)); 506 omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0); 507 omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1); 508 omap_ctrl_writel(control_context.dss_dpll_spreading, 509 OMAP343X_CONTROL_DSS_DPLL_SPREADING); 510 omap_ctrl_writel(control_context.core_dpll_spreading, 511 OMAP343X_CONTROL_CORE_DPLL_SPREADING); 512 omap_ctrl_writel(control_context.per_dpll_spreading, 513 OMAP343X_CONTROL_PER_DPLL_SPREADING); 514 omap_ctrl_writel(control_context.usbhost_dpll_spreading, 515 OMAP343X_CONTROL_USBHOST_DPLL_SPREADING); 516 omap_ctrl_writel(control_context.pbias_lite, 517 OMAP343X_CONTROL_PBIAS_LITE); 518 omap_ctrl_writel(control_context.temp_sensor, 519 OMAP343X_CONTROL_TEMP_SENSOR); 520 omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4); 521 omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5); 522 omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI); 523 omap_ctrl_writel(control_context.padconf_sys_nirq, 524 OMAP343X_CONTROL_PADCONF_SYSNIRQ); 525 } 526 527 void omap3630_ctrl_disable_rta(void) 528 { 529 if (!cpu_is_omap3630()) 530 return; 531 omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL); 532 } 533 534 /** 535 * omap3_ctrl_save_padconf - save padconf registers to scratchpad RAM 536 * 537 * Tell the SCM to start saving the padconf registers, then wait for 538 * the process to complete. Returns 0 unconditionally, although it 539 * should also eventually be able to return -ETIMEDOUT, if the save 540 * does not complete. 541 * 542 * XXX This function is missing a timeout. What should it be? 543 */ 544 int omap3_ctrl_save_padconf(void) 545 { 546 u32 cpo; 547 548 /* Save the padconf registers */ 549 cpo = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF); 550 cpo |= START_PADCONF_SAVE; 551 omap_ctrl_writel(cpo, OMAP343X_CONTROL_PADCONF_OFF); 552 553 /* wait for the save to complete */ 554 while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS) 555 & PADCONF_SAVE_DONE)) 556 udelay(1); 557 558 return 0; 559 } 560 561 /** 562 * omap3_ctrl_set_iva_bootmode_idle - sets the IVA2 bootmode to idle 563 * 564 * Sets the bootmode for IVA2 to idle. This is needed by the PM code to 565 * force disable IVA2 so that it does not prevent any low-power states. 566 */ 567 static void __init omap3_ctrl_set_iva_bootmode_idle(void) 568 { 569 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, 570 OMAP343X_CONTROL_IVA2_BOOTMOD); 571 } 572 573 /** 574 * omap3_ctrl_setup_d2d_padconf - setup stacked modem pads for idle 575 * 576 * Sets up the pads controlling the stacked modem in such way that the 577 * device can enter idle. 578 */ 579 static void __init omap3_ctrl_setup_d2d_padconf(void) 580 { 581 u16 mask, padconf; 582 583 /* 584 * In a stand alone OMAP3430 where there is not a stacked 585 * modem for the D2D Idle Ack and D2D MStandby must be pulled 586 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and 587 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. 588 */ 589 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ 590 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); 591 padconf |= mask; 592 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); 593 594 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); 595 padconf |= mask; 596 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); 597 } 598 599 /** 600 * omap3_ctrl_init - does static initializations for control module 601 * 602 * Initializes system control module. This sets up the sysconfig autoidle, 603 * and sets up modem and iva2 so that they can be idled properly. 604 */ 605 void __init omap3_ctrl_init(void) 606 { 607 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); 608 609 omap3_ctrl_set_iva_bootmode_idle(); 610 611 omap3_ctrl_setup_d2d_padconf(); 612 } 613 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ 614