1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * OMAP2/3 System Control Module register access 4 * 5 * Copyright (C) 2007, 2012 Texas Instruments, Inc. 6 * Copyright (C) 2007 Nokia Corporation 7 * 8 * Written by Paul Walmsley 9 */ 10 #undef DEBUG 11 12 #include <linux/kernel.h> 13 #include <linux/io.h> 14 #include <linux/of_address.h> 15 #include <linux/regmap.h> 16 #include <linux/mfd/syscon.h> 17 #include <linux/cpu_pm.h> 18 19 #include "soc.h" 20 #include "iomap.h" 21 #include "common.h" 22 #include "cm-regbits-34xx.h" 23 #include "prm-regbits-34xx.h" 24 #include "prm3xxx.h" 25 #include "cm3xxx.h" 26 #include "sdrc.h" 27 #include "pm.h" 28 #include "control.h" 29 #include "clock.h" 30 31 /* Used by omap3_ctrl_save_padconf() */ 32 #define START_PADCONF_SAVE 0x2 33 #define PADCONF_SAVE_DONE 0x1 34 35 static void __iomem *omap2_ctrl_base; 36 static s16 omap2_ctrl_offset; 37 38 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 39 struct omap3_scratchpad { 40 u32 boot_config_ptr; 41 u32 public_restore_ptr; 42 u32 secure_ram_restore_ptr; 43 u32 sdrc_module_semaphore; 44 u32 prcm_block_offset; 45 u32 sdrc_block_offset; 46 }; 47 48 struct omap3_scratchpad_prcm_block { 49 u32 prm_contents[2]; 50 u32 cm_contents[11]; 51 u32 prcm_block_size; 52 }; 53 54 struct omap3_scratchpad_sdrc_block { 55 u16 sysconfig; 56 u16 cs_cfg; 57 u16 sharing; 58 u16 err_type; 59 u32 dll_a_ctrl; 60 u32 dll_b_ctrl; 61 u32 power; 62 u32 cs_0; 63 u32 mcfg_0; 64 u16 mr_0; 65 u16 emr_1_0; 66 u16 emr_2_0; 67 u16 emr_3_0; 68 u32 actim_ctrla_0; 69 u32 actim_ctrlb_0; 70 u32 rfr_ctrl_0; 71 u32 cs_1; 72 u32 mcfg_1; 73 u16 mr_1; 74 u16 emr_1_1; 75 u16 emr_2_1; 76 u16 emr_3_1; 77 u32 actim_ctrla_1; 78 u32 actim_ctrlb_1; 79 u32 rfr_ctrl_1; 80 u16 dcdl_1_ctrl; 81 u16 dcdl_2_ctrl; 82 u32 flags; 83 u32 block_size; 84 }; 85 86 void *omap3_secure_ram_storage; 87 88 /* 89 * This is used to store ARM registers in SDRAM before attempting 90 * an MPU OFF. The save and restore happens from the SRAM sleep code. 91 * The address is stored in scratchpad, so that it can be used 92 * during the restore path. 93 */ 94 u32 omap3_arm_context[128]; 95 96 struct omap3_control_regs { 97 u32 sysconfig; 98 u32 devconf0; 99 u32 mem_dftrw0; 100 u32 mem_dftrw1; 101 u32 msuspendmux_0; 102 u32 msuspendmux_1; 103 u32 msuspendmux_2; 104 u32 msuspendmux_3; 105 u32 msuspendmux_4; 106 u32 msuspendmux_5; 107 u32 sec_ctrl; 108 u32 devconf1; 109 u32 csirxfe; 110 u32 iva2_bootaddr; 111 u32 iva2_bootmod; 112 u32 wkup_ctrl; 113 u32 debobs_0; 114 u32 debobs_1; 115 u32 debobs_2; 116 u32 debobs_3; 117 u32 debobs_4; 118 u32 debobs_5; 119 u32 debobs_6; 120 u32 debobs_7; 121 u32 debobs_8; 122 u32 prog_io0; 123 u32 prog_io1; 124 u32 dss_dpll_spreading; 125 u32 core_dpll_spreading; 126 u32 per_dpll_spreading; 127 u32 usbhost_dpll_spreading; 128 u32 pbias_lite; 129 u32 temp_sensor; 130 u32 sramldo4; 131 u32 sramldo5; 132 u32 csi; 133 u32 padconf_sys_nirq; 134 }; 135 136 static struct omap3_control_regs control_context; 137 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ 138 139 u8 omap_ctrl_readb(u16 offset) 140 { 141 u32 val; 142 u8 byte_offset = offset & 0x3; 143 144 val = omap_ctrl_readl(offset); 145 146 return (val >> (byte_offset * 8)) & 0xff; 147 } 148 149 u16 omap_ctrl_readw(u16 offset) 150 { 151 u32 val; 152 u16 byte_offset = offset & 0x2; 153 154 val = omap_ctrl_readl(offset); 155 156 return (val >> (byte_offset * 8)) & 0xffff; 157 } 158 159 u32 omap_ctrl_readl(u16 offset) 160 { 161 offset &= 0xfffc; 162 163 return readl_relaxed(omap2_ctrl_base + offset); 164 } 165 166 void omap_ctrl_writeb(u8 val, u16 offset) 167 { 168 u32 tmp; 169 u8 byte_offset = offset & 0x3; 170 171 tmp = omap_ctrl_readl(offset); 172 173 tmp &= 0xffffffff ^ (0xff << (byte_offset * 8)); 174 tmp |= val << (byte_offset * 8); 175 176 omap_ctrl_writel(tmp, offset); 177 } 178 179 void omap_ctrl_writew(u16 val, u16 offset) 180 { 181 u32 tmp; 182 u8 byte_offset = offset & 0x2; 183 184 tmp = omap_ctrl_readl(offset); 185 186 tmp &= 0xffffffff ^ (0xffff << (byte_offset * 8)); 187 tmp |= val << (byte_offset * 8); 188 189 omap_ctrl_writel(tmp, offset); 190 } 191 192 void omap_ctrl_writel(u32 val, u16 offset) 193 { 194 offset &= 0xfffc; 195 writel_relaxed(val, omap2_ctrl_base + offset); 196 } 197 198 #ifdef CONFIG_ARCH_OMAP3 199 200 /** 201 * omap3_ctrl_write_boot_mode - set scratchpad boot mode for the next boot 202 * @bootmode: 8-bit value to pass to some boot code 203 * 204 * Set the bootmode in the scratchpad RAM. This is used after the 205 * system restarts. Not sure what actually uses this - it may be the 206 * bootloader, rather than the boot ROM - contrary to the preserved 207 * comment below. No return value. 208 */ 209 void omap3_ctrl_write_boot_mode(u8 bootmode) 210 { 211 u32 l; 212 213 l = ('B' << 24) | ('M' << 16) | bootmode; 214 215 /* 216 * Reserve the first word in scratchpad for communicating 217 * with the boot ROM. A pointer to a data structure 218 * describing the boot process can be stored there, 219 * cf. OMAP34xx TRM, Initialization / Software Booting 220 * Configuration. 221 * 222 * XXX This should use some omap_ctrl_writel()-type function 223 */ 224 writel_relaxed(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4)); 225 } 226 227 #endif 228 229 /** 230 * omap_ctrl_write_dsp_boot_addr - set boot address for a remote processor 231 * @bootaddr: physical address of the boot loader 232 * 233 * Set boot address for the boot loader of a supported processor 234 * when a power ON sequence occurs. 235 */ 236 void omap_ctrl_write_dsp_boot_addr(u32 bootaddr) 237 { 238 u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTADDR : 239 cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTADDR : 240 cpu_is_omap44xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR : 241 soc_is_omap54xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR : 242 0; 243 244 if (!offset) { 245 pr_err("%s: unsupported omap type\n", __func__); 246 return; 247 } 248 249 omap_ctrl_writel(bootaddr, offset); 250 } 251 252 /** 253 * omap_ctrl_write_dsp_boot_mode - set boot mode for a remote processor 254 * @bootmode: 8-bit value to pass to some boot code 255 * 256 * Sets boot mode for the boot loader of a supported processor 257 * when a power ON sequence occurs. 258 */ 259 void omap_ctrl_write_dsp_boot_mode(u8 bootmode) 260 { 261 u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTMOD : 262 cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTMOD : 263 0; 264 265 if (!offset) { 266 pr_err("%s: unsupported omap type\n", __func__); 267 return; 268 } 269 270 omap_ctrl_writel(bootmode, offset); 271 } 272 273 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 274 /* 275 * Clears the scratchpad contents in case of cold boot- 276 * called during bootup 277 */ 278 void omap3_clear_scratchpad_contents(void) 279 { 280 u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET; 281 void __iomem *v_addr; 282 u32 offset = 0; 283 284 v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM); 285 if (omap3xxx_prm_clear_global_cold_reset()) { 286 for ( ; offset <= max_offset; offset += 0x4) 287 writel_relaxed(0x0, (v_addr + offset)); 288 } 289 } 290 291 /* Populate the scratchpad structure with restore structure */ 292 void omap3_save_scratchpad_contents(void) 293 { 294 void __iomem *scratchpad_address; 295 u32 arm_context_addr; 296 struct omap3_scratchpad scratchpad_contents; 297 struct omap3_scratchpad_prcm_block prcm_block_contents; 298 struct omap3_scratchpad_sdrc_block sdrc_block_contents; 299 300 /* 301 * Populate the Scratchpad contents 302 * 303 * The "get_*restore_pointer" functions are used to provide a 304 * physical restore address where the ROM code jumps while waking 305 * up from MPU OFF/OSWR state. 306 * The restore pointer is stored into the scratchpad. 307 */ 308 scratchpad_contents.boot_config_ptr = 0x0; 309 if (cpu_is_omap3630()) 310 scratchpad_contents.public_restore_ptr = 311 __pa_symbol(omap3_restore_3630); 312 else if (omap_rev() != OMAP3430_REV_ES3_0 && 313 omap_rev() != OMAP3430_REV_ES3_1 && 314 omap_rev() != OMAP3430_REV_ES3_1_2) 315 scratchpad_contents.public_restore_ptr = 316 __pa_symbol(omap3_restore); 317 else 318 scratchpad_contents.public_restore_ptr = 319 __pa_symbol(omap3_restore_es3); 320 321 if (omap_type() == OMAP2_DEVICE_TYPE_GP) 322 scratchpad_contents.secure_ram_restore_ptr = 0x0; 323 else 324 scratchpad_contents.secure_ram_restore_ptr = 325 (u32) __pa(omap3_secure_ram_storage); 326 scratchpad_contents.sdrc_module_semaphore = 0x0; 327 scratchpad_contents.prcm_block_offset = 0x2C; 328 scratchpad_contents.sdrc_block_offset = 0x64; 329 330 /* Populate the PRCM block contents */ 331 omap3_prm_save_scratchpad_contents(prcm_block_contents.prm_contents); 332 omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents); 333 334 prcm_block_contents.prcm_block_size = 0x0; 335 336 /* Populate the SDRC block contents */ 337 sdrc_block_contents.sysconfig = 338 (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF); 339 sdrc_block_contents.cs_cfg = 340 (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF); 341 sdrc_block_contents.sharing = 342 (sdrc_read_reg(SDRC_SHARING) & 0xFFFF); 343 sdrc_block_contents.err_type = 344 (sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF); 345 sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL); 346 sdrc_block_contents.dll_b_ctrl = 0x0; 347 /* 348 * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should 349 * be programed to issue automatic self refresh on timeout 350 * of AUTO_CNT = 1 prior to any transition to OFF mode. 351 */ 352 if ((omap_type() != OMAP2_DEVICE_TYPE_GP) 353 && (omap_rev() >= OMAP3430_REV_ES3_0)) 354 sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) & 355 ~(SDRC_POWER_AUTOCOUNT_MASK| 356 SDRC_POWER_CLKCTRL_MASK)) | 357 (1 << SDRC_POWER_AUTOCOUNT_SHIFT) | 358 SDRC_SELF_REFRESH_ON_AUTOCOUNT; 359 else 360 sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER); 361 362 sdrc_block_contents.cs_0 = 0x0; 363 sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0); 364 sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF); 365 sdrc_block_contents.emr_1_0 = 0x0; 366 sdrc_block_contents.emr_2_0 = 0x0; 367 sdrc_block_contents.emr_3_0 = 0x0; 368 sdrc_block_contents.actim_ctrla_0 = 369 sdrc_read_reg(SDRC_ACTIM_CTRL_A_0); 370 sdrc_block_contents.actim_ctrlb_0 = 371 sdrc_read_reg(SDRC_ACTIM_CTRL_B_0); 372 sdrc_block_contents.rfr_ctrl_0 = 373 sdrc_read_reg(SDRC_RFR_CTRL_0); 374 sdrc_block_contents.cs_1 = 0x0; 375 sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1); 376 sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF; 377 sdrc_block_contents.emr_1_1 = 0x0; 378 sdrc_block_contents.emr_2_1 = 0x0; 379 sdrc_block_contents.emr_3_1 = 0x0; 380 sdrc_block_contents.actim_ctrla_1 = 381 sdrc_read_reg(SDRC_ACTIM_CTRL_A_1); 382 sdrc_block_contents.actim_ctrlb_1 = 383 sdrc_read_reg(SDRC_ACTIM_CTRL_B_1); 384 sdrc_block_contents.rfr_ctrl_1 = 385 sdrc_read_reg(SDRC_RFR_CTRL_1); 386 sdrc_block_contents.dcdl_1_ctrl = 0x0; 387 sdrc_block_contents.dcdl_2_ctrl = 0x0; 388 sdrc_block_contents.flags = 0x0; 389 sdrc_block_contents.block_size = 0x0; 390 391 arm_context_addr = __pa_symbol(omap3_arm_context); 392 393 /* Copy all the contents to the scratchpad location */ 394 scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD); 395 memcpy_toio(scratchpad_address, &scratchpad_contents, 396 sizeof(scratchpad_contents)); 397 /* Scratchpad contents being 32 bits, a divide by 4 done here */ 398 memcpy_toio(scratchpad_address + 399 scratchpad_contents.prcm_block_offset, 400 &prcm_block_contents, sizeof(prcm_block_contents)); 401 memcpy_toio(scratchpad_address + 402 scratchpad_contents.sdrc_block_offset, 403 &sdrc_block_contents, sizeof(sdrc_block_contents)); 404 /* 405 * Copies the address of the location in SDRAM where ARM 406 * registers get saved during a MPU OFF transition. 407 */ 408 memcpy_toio(scratchpad_address + 409 scratchpad_contents.sdrc_block_offset + 410 sizeof(sdrc_block_contents), &arm_context_addr, 4); 411 } 412 413 void omap3_control_save_context(void) 414 { 415 control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG); 416 control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); 417 control_context.mem_dftrw0 = 418 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0); 419 control_context.mem_dftrw1 = 420 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1); 421 control_context.msuspendmux_0 = 422 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0); 423 control_context.msuspendmux_1 = 424 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1); 425 control_context.msuspendmux_2 = 426 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2); 427 control_context.msuspendmux_3 = 428 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3); 429 control_context.msuspendmux_4 = 430 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4); 431 control_context.msuspendmux_5 = 432 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5); 433 control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL); 434 control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1); 435 control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE); 436 control_context.iva2_bootaddr = 437 omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR); 438 control_context.iva2_bootmod = 439 omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD); 440 control_context.wkup_ctrl = omap_ctrl_readl(OMAP34XX_CONTROL_WKUP_CTRL); 441 control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0)); 442 control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1)); 443 control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2)); 444 control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3)); 445 control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4)); 446 control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5)); 447 control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6)); 448 control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7)); 449 control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8)); 450 control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0); 451 control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1); 452 control_context.dss_dpll_spreading = 453 omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING); 454 control_context.core_dpll_spreading = 455 omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING); 456 control_context.per_dpll_spreading = 457 omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING); 458 control_context.usbhost_dpll_spreading = 459 omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING); 460 control_context.pbias_lite = 461 omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE); 462 control_context.temp_sensor = 463 omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR); 464 control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4); 465 control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5); 466 control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI); 467 control_context.padconf_sys_nirq = 468 omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ); 469 } 470 471 void omap3_control_restore_context(void) 472 { 473 omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG); 474 omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0); 475 omap_ctrl_writel(control_context.mem_dftrw0, 476 OMAP343X_CONTROL_MEM_DFTRW0); 477 omap_ctrl_writel(control_context.mem_dftrw1, 478 OMAP343X_CONTROL_MEM_DFTRW1); 479 omap_ctrl_writel(control_context.msuspendmux_0, 480 OMAP2_CONTROL_MSUSPENDMUX_0); 481 omap_ctrl_writel(control_context.msuspendmux_1, 482 OMAP2_CONTROL_MSUSPENDMUX_1); 483 omap_ctrl_writel(control_context.msuspendmux_2, 484 OMAP2_CONTROL_MSUSPENDMUX_2); 485 omap_ctrl_writel(control_context.msuspendmux_3, 486 OMAP2_CONTROL_MSUSPENDMUX_3); 487 omap_ctrl_writel(control_context.msuspendmux_4, 488 OMAP2_CONTROL_MSUSPENDMUX_4); 489 omap_ctrl_writel(control_context.msuspendmux_5, 490 OMAP2_CONTROL_MSUSPENDMUX_5); 491 omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL); 492 omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1); 493 omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE); 494 omap_ctrl_writel(control_context.iva2_bootaddr, 495 OMAP343X_CONTROL_IVA2_BOOTADDR); 496 omap_ctrl_writel(control_context.iva2_bootmod, 497 OMAP343X_CONTROL_IVA2_BOOTMOD); 498 omap_ctrl_writel(control_context.wkup_ctrl, OMAP34XX_CONTROL_WKUP_CTRL); 499 omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0)); 500 omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1)); 501 omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2)); 502 omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3)); 503 omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4)); 504 omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5)); 505 omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6)); 506 omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7)); 507 omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8)); 508 omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0); 509 omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1); 510 omap_ctrl_writel(control_context.dss_dpll_spreading, 511 OMAP343X_CONTROL_DSS_DPLL_SPREADING); 512 omap_ctrl_writel(control_context.core_dpll_spreading, 513 OMAP343X_CONTROL_CORE_DPLL_SPREADING); 514 omap_ctrl_writel(control_context.per_dpll_spreading, 515 OMAP343X_CONTROL_PER_DPLL_SPREADING); 516 omap_ctrl_writel(control_context.usbhost_dpll_spreading, 517 OMAP343X_CONTROL_USBHOST_DPLL_SPREADING); 518 omap_ctrl_writel(control_context.pbias_lite, 519 OMAP343X_CONTROL_PBIAS_LITE); 520 omap_ctrl_writel(control_context.temp_sensor, 521 OMAP343X_CONTROL_TEMP_SENSOR); 522 omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4); 523 omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5); 524 omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI); 525 omap_ctrl_writel(control_context.padconf_sys_nirq, 526 OMAP343X_CONTROL_PADCONF_SYSNIRQ); 527 } 528 529 void omap3630_ctrl_disable_rta(void) 530 { 531 if (!cpu_is_omap3630()) 532 return; 533 omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL); 534 } 535 536 /** 537 * omap3_ctrl_save_padconf - save padconf registers to scratchpad RAM 538 * 539 * Tell the SCM to start saving the padconf registers, then wait for 540 * the process to complete. Returns 0 unconditionally, although it 541 * should also eventually be able to return -ETIMEDOUT, if the save 542 * does not complete. 543 * 544 * XXX This function is missing a timeout. What should it be? 545 */ 546 int omap3_ctrl_save_padconf(void) 547 { 548 u32 cpo; 549 550 /* Save the padconf registers */ 551 cpo = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF); 552 cpo |= START_PADCONF_SAVE; 553 omap_ctrl_writel(cpo, OMAP343X_CONTROL_PADCONF_OFF); 554 555 /* wait for the save to complete */ 556 while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS) 557 & PADCONF_SAVE_DONE)) 558 udelay(1); 559 560 return 0; 561 } 562 563 /** 564 * omap3_ctrl_set_iva_bootmode_idle - sets the IVA2 bootmode to idle 565 * 566 * Sets the bootmode for IVA2 to idle. This is needed by the PM code to 567 * force disable IVA2 so that it does not prevent any low-power states. 568 */ 569 static void __init omap3_ctrl_set_iva_bootmode_idle(void) 570 { 571 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, 572 OMAP343X_CONTROL_IVA2_BOOTMOD); 573 } 574 575 /** 576 * omap3_ctrl_setup_d2d_padconf - setup stacked modem pads for idle 577 * 578 * Sets up the pads controlling the stacked modem in such way that the 579 * device can enter idle. 580 */ 581 static void __init omap3_ctrl_setup_d2d_padconf(void) 582 { 583 u16 mask, padconf; 584 585 /* 586 * In a stand alone OMAP3430 where there is not a stacked 587 * modem for the D2D Idle Ack and D2D MStandby must be pulled 588 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and 589 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. 590 */ 591 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ 592 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); 593 padconf |= mask; 594 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); 595 596 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); 597 padconf |= mask; 598 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); 599 } 600 601 /** 602 * omap3_ctrl_init - does static initializations for control module 603 * 604 * Initializes system control module. This sets up the sysconfig autoidle, 605 * and sets up modem and iva2 so that they can be idled properly. 606 */ 607 void __init omap3_ctrl_init(void) 608 { 609 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); 610 611 omap3_ctrl_set_iva_bootmode_idle(); 612 613 omap3_ctrl_setup_d2d_padconf(); 614 } 615 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ 616 617 static unsigned long am43xx_control_reg_offsets[] = { 618 AM33XX_CONTROL_SYSCONFIG_OFFSET, 619 AM33XX_CONTROL_STATUS_OFFSET, 620 AM43XX_CONTROL_MPU_L2_CTRL_OFFSET, 621 AM33XX_CONTROL_CORE_SLDO_CTRL_OFFSET, 622 AM33XX_CONTROL_MPU_SLDO_CTRL_OFFSET, 623 AM33XX_CONTROL_CLK32KDIVRATIO_CTRL_OFFSET, 624 AM33XX_CONTROL_BANDGAP_CTRL_OFFSET, 625 AM33XX_CONTROL_BANDGAP_TRIM_OFFSET, 626 AM33XX_CONTROL_PLL_CLKINPULOW_CTRL_OFFSET, 627 AM33XX_CONTROL_MOSC_CTRL_OFFSET, 628 AM33XX_CONTROL_DEEPSLEEP_CTRL_OFFSET, 629 AM43XX_CONTROL_DISPLAY_PLL_SEL_OFFSET, 630 AM33XX_CONTROL_INIT_PRIORITY_0_OFFSET, 631 AM33XX_CONTROL_INIT_PRIORITY_1_OFFSET, 632 AM33XX_CONTROL_TPTC_CFG_OFFSET, 633 AM33XX_CONTROL_USB_CTRL0_OFFSET, 634 AM33XX_CONTROL_USB_CTRL1_OFFSET, 635 AM43XX_CONTROL_USB_CTRL2_OFFSET, 636 AM43XX_CONTROL_GMII_SEL_OFFSET, 637 AM43XX_CONTROL_MPUSS_CTRL_OFFSET, 638 AM43XX_CONTROL_TIMER_CASCADE_CTRL_OFFSET, 639 AM43XX_CONTROL_PWMSS_CTRL_OFFSET, 640 AM33XX_CONTROL_MREQPRIO_0_OFFSET, 641 AM33XX_CONTROL_MREQPRIO_1_OFFSET, 642 AM33XX_CONTROL_HW_EVENT_SEL_GRP1_OFFSET, 643 AM33XX_CONTROL_HW_EVENT_SEL_GRP2_OFFSET, 644 AM33XX_CONTROL_HW_EVENT_SEL_GRP3_OFFSET, 645 AM33XX_CONTROL_HW_EVENT_SEL_GRP4_OFFSET, 646 AM33XX_CONTROL_SMRT_CTRL_OFFSET, 647 AM33XX_CONTROL_MPUSS_HW_DEBUG_SEL_OFFSET, 648 AM43XX_CONTROL_CQDETECT_STS_OFFSET, 649 AM43XX_CONTROL_CQDETECT_STS2_OFFSET, 650 AM43XX_CONTROL_VTP_CTRL_OFFSET, 651 AM33XX_CONTROL_VREF_CTRL_OFFSET, 652 AM33XX_CONTROL_TPCC_EVT_MUX_0_3_OFFSET, 653 AM33XX_CONTROL_TPCC_EVT_MUX_4_7_OFFSET, 654 AM33XX_CONTROL_TPCC_EVT_MUX_8_11_OFFSET, 655 AM33XX_CONTROL_TPCC_EVT_MUX_12_15_OFFSET, 656 AM33XX_CONTROL_TPCC_EVT_MUX_16_19_OFFSET, 657 AM33XX_CONTROL_TPCC_EVT_MUX_20_23_OFFSET, 658 AM33XX_CONTROL_TPCC_EVT_MUX_24_27_OFFSET, 659 AM33XX_CONTROL_TPCC_EVT_MUX_28_31_OFFSET, 660 AM33XX_CONTROL_TPCC_EVT_MUX_32_35_OFFSET, 661 AM33XX_CONTROL_TPCC_EVT_MUX_36_39_OFFSET, 662 AM33XX_CONTROL_TPCC_EVT_MUX_40_43_OFFSET, 663 AM33XX_CONTROL_TPCC_EVT_MUX_44_47_OFFSET, 664 AM33XX_CONTROL_TPCC_EVT_MUX_48_51_OFFSET, 665 AM33XX_CONTROL_TPCC_EVT_MUX_52_55_OFFSET, 666 AM33XX_CONTROL_TPCC_EVT_MUX_56_59_OFFSET, 667 AM33XX_CONTROL_TPCC_EVT_MUX_60_63_OFFSET, 668 AM33XX_CONTROL_TIMER_EVT_CAPT_OFFSET, 669 AM33XX_CONTROL_ECAP_EVT_CAPT_OFFSET, 670 AM33XX_CONTROL_ADC_EVT_CAPT_OFFSET, 671 AM43XX_CONTROL_ADC1_EVT_CAPT_OFFSET, 672 AM33XX_CONTROL_RESET_ISO_OFFSET, 673 }; 674 675 static u32 am33xx_control_vals[ARRAY_SIZE(am43xx_control_reg_offsets)]; 676 677 /** 678 * am43xx_control_save_context - Save the wakeup domain registers 679 * 680 * Save the wkup domain registers 681 */ 682 static void am43xx_control_save_context(void) 683 { 684 int i; 685 686 for (i = 0; i < ARRAY_SIZE(am43xx_control_reg_offsets); i++) 687 am33xx_control_vals[i] = 688 omap_ctrl_readl(am43xx_control_reg_offsets[i]); 689 } 690 691 /** 692 * am43xx_control_restore_context - Restore the wakeup domain registers 693 * 694 * Restore the wkup domain registers 695 */ 696 static void am43xx_control_restore_context(void) 697 { 698 int i; 699 700 for (i = 0; i < ARRAY_SIZE(am43xx_control_reg_offsets); i++) 701 omap_ctrl_writel(am33xx_control_vals[i], 702 am43xx_control_reg_offsets[i]); 703 } 704 705 static int cpu_notifier(struct notifier_block *nb, unsigned long cmd, void *v) 706 { 707 switch (cmd) { 708 case CPU_CLUSTER_PM_ENTER: 709 if (enable_off_mode) 710 am43xx_control_save_context(); 711 break; 712 case CPU_CLUSTER_PM_EXIT: 713 if (enable_off_mode) 714 am43xx_control_restore_context(); 715 break; 716 } 717 718 return NOTIFY_OK; 719 } 720 721 struct control_init_data { 722 int index; 723 void __iomem *mem; 724 s16 offset; 725 }; 726 727 static struct control_init_data ctrl_data = { 728 .index = TI_CLKM_CTRL, 729 }; 730 731 static const struct control_init_data omap2_ctrl_data = { 732 .index = TI_CLKM_CTRL, 733 .offset = -OMAP2_CONTROL_GENERAL, 734 }; 735 736 static const struct control_init_data ctrl_aux_data = { 737 .index = TI_CLKM_CTRL_AUX, 738 }; 739 740 static const struct of_device_id omap_scrm_dt_match_table[] = { 741 { .compatible = "ti,am3-scm", .data = &ctrl_data }, 742 { .compatible = "ti,am4-scm", .data = &ctrl_data }, 743 { .compatible = "ti,omap2-scm", .data = &omap2_ctrl_data }, 744 { .compatible = "ti,omap3-scm", .data = &omap2_ctrl_data }, 745 { .compatible = "ti,dm814-scm", .data = &ctrl_data }, 746 { .compatible = "ti,dm816-scrm", .data = &ctrl_data }, 747 { .compatible = "ti,omap4-scm-core", .data = &ctrl_data }, 748 { .compatible = "ti,omap5-scm-core", .data = &ctrl_data }, 749 { .compatible = "ti,omap5-scm-wkup-pad-conf", .data = &ctrl_aux_data }, 750 { .compatible = "ti,dra7-scm-core", .data = &ctrl_data }, 751 { } 752 }; 753 754 /** 755 * omap2_control_base_init - initialize iomappings for the control driver 756 * 757 * Detects and initializes the iomappings for the control driver, based 758 * on the DT data. Returns 0 in success, negative error value 759 * otherwise. 760 */ 761 int __init omap2_control_base_init(void) 762 { 763 struct device_node *np; 764 const struct of_device_id *match; 765 struct control_init_data *data; 766 void __iomem *mem; 767 768 for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) { 769 data = (struct control_init_data *)match->data; 770 771 mem = of_iomap(np, 0); 772 if (!mem) 773 return -ENOMEM; 774 775 if (data->index == TI_CLKM_CTRL) { 776 omap2_ctrl_base = mem; 777 omap2_ctrl_offset = data->offset; 778 } 779 780 data->mem = mem; 781 } 782 783 return 0; 784 } 785 786 /** 787 * omap_control_init - low level init for the control driver 788 * 789 * Initializes the low level clock infrastructure for control driver. 790 * Returns 0 in success, negative error value in failure. 791 */ 792 int __init omap_control_init(void) 793 { 794 struct device_node *np, *scm_conf; 795 const struct of_device_id *match; 796 const struct omap_prcm_init_data *data; 797 int ret; 798 struct regmap *syscon; 799 static struct notifier_block nb; 800 801 for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) { 802 data = match->data; 803 804 /* 805 * Check if we have scm_conf node, if yes, use this to 806 * access clock registers. 807 */ 808 scm_conf = of_get_child_by_name(np, "scm_conf"); 809 810 if (scm_conf) { 811 syscon = syscon_node_to_regmap(scm_conf); 812 813 if (IS_ERR(syscon)) 814 return PTR_ERR(syscon); 815 816 if (of_get_child_by_name(scm_conf, "clocks")) { 817 ret = omap2_clk_provider_init(scm_conf, 818 data->index, 819 syscon, NULL); 820 if (ret) 821 return ret; 822 } 823 } else { 824 /* No scm_conf found, direct access */ 825 ret = omap2_clk_provider_init(np, data->index, NULL, 826 data->mem); 827 if (ret) 828 return ret; 829 } 830 } 831 832 /* Only AM43XX can lose ctrl registers context during rtc-ddr suspend */ 833 if (soc_is_am43xx()) { 834 nb.notifier_call = cpu_notifier; 835 cpu_pm_register_notifier(&nb); 836 } 837 838 return 0; 839 } 840 841 /** 842 * omap3_control_legacy_iomap_init - legacy iomap init for clock providers 843 * 844 * Legacy iomap init for clock provider. Needed only by legacy boot mode, 845 * where the base addresses are not parsed from DT, but still required 846 * by the clock driver to be setup properly. 847 */ 848 void __init omap3_control_legacy_iomap_init(void) 849 { 850 omap2_clk_legacy_provider_init(TI_CLKM_SCRM, omap2_ctrl_base); 851 } 852