1 /* 2 * OMAP2/3 System Control Module register access 3 * 4 * Copyright (C) 2007, 2012 Texas Instruments, Inc. 5 * Copyright (C) 2007 Nokia Corporation 6 * 7 * Written by Paul Walmsley 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 #undef DEBUG 14 15 #include <linux/kernel.h> 16 #include <linux/io.h> 17 #include <linux/of_address.h> 18 19 #include "soc.h" 20 #include "iomap.h" 21 #include "common.h" 22 #include "cm-regbits-34xx.h" 23 #include "prm-regbits-34xx.h" 24 #include "prm3xxx.h" 25 #include "cm3xxx.h" 26 #include "sdrc.h" 27 #include "pm.h" 28 #include "control.h" 29 #include "clock.h" 30 31 /* Used by omap3_ctrl_save_padconf() */ 32 #define START_PADCONF_SAVE 0x2 33 #define PADCONF_SAVE_DONE 0x1 34 35 static void __iomem *omap2_ctrl_base; 36 static void __iomem *omap4_ctrl_pad_base; 37 38 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 39 struct omap3_scratchpad { 40 u32 boot_config_ptr; 41 u32 public_restore_ptr; 42 u32 secure_ram_restore_ptr; 43 u32 sdrc_module_semaphore; 44 u32 prcm_block_offset; 45 u32 sdrc_block_offset; 46 }; 47 48 struct omap3_scratchpad_prcm_block { 49 u32 prm_contents[2]; 50 u32 cm_contents[11]; 51 u32 prcm_block_size; 52 }; 53 54 struct omap3_scratchpad_sdrc_block { 55 u16 sysconfig; 56 u16 cs_cfg; 57 u16 sharing; 58 u16 err_type; 59 u32 dll_a_ctrl; 60 u32 dll_b_ctrl; 61 u32 power; 62 u32 cs_0; 63 u32 mcfg_0; 64 u16 mr_0; 65 u16 emr_1_0; 66 u16 emr_2_0; 67 u16 emr_3_0; 68 u32 actim_ctrla_0; 69 u32 actim_ctrlb_0; 70 u32 rfr_ctrl_0; 71 u32 cs_1; 72 u32 mcfg_1; 73 u16 mr_1; 74 u16 emr_1_1; 75 u16 emr_2_1; 76 u16 emr_3_1; 77 u32 actim_ctrla_1; 78 u32 actim_ctrlb_1; 79 u32 rfr_ctrl_1; 80 u16 dcdl_1_ctrl; 81 u16 dcdl_2_ctrl; 82 u32 flags; 83 u32 block_size; 84 }; 85 86 void *omap3_secure_ram_storage; 87 88 /* 89 * This is used to store ARM registers in SDRAM before attempting 90 * an MPU OFF. The save and restore happens from the SRAM sleep code. 91 * The address is stored in scratchpad, so that it can be used 92 * during the restore path. 93 */ 94 u32 omap3_arm_context[128]; 95 96 struct omap3_control_regs { 97 u32 sysconfig; 98 u32 devconf0; 99 u32 mem_dftrw0; 100 u32 mem_dftrw1; 101 u32 msuspendmux_0; 102 u32 msuspendmux_1; 103 u32 msuspendmux_2; 104 u32 msuspendmux_3; 105 u32 msuspendmux_4; 106 u32 msuspendmux_5; 107 u32 sec_ctrl; 108 u32 devconf1; 109 u32 csirxfe; 110 u32 iva2_bootaddr; 111 u32 iva2_bootmod; 112 u32 debobs_0; 113 u32 debobs_1; 114 u32 debobs_2; 115 u32 debobs_3; 116 u32 debobs_4; 117 u32 debobs_5; 118 u32 debobs_6; 119 u32 debobs_7; 120 u32 debobs_8; 121 u32 prog_io0; 122 u32 prog_io1; 123 u32 dss_dpll_spreading; 124 u32 core_dpll_spreading; 125 u32 per_dpll_spreading; 126 u32 usbhost_dpll_spreading; 127 u32 pbias_lite; 128 u32 temp_sensor; 129 u32 sramldo4; 130 u32 sramldo5; 131 u32 csi; 132 u32 padconf_sys_nirq; 133 }; 134 135 static struct omap3_control_regs control_context; 136 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ 137 138 #define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg)) 139 #define OMAP4_CTRL_PAD_REGADDR(reg) (omap4_ctrl_pad_base + (reg)) 140 141 void __init omap2_set_globals_control(void __iomem *ctrl, 142 void __iomem *ctrl_pad) 143 { 144 omap2_ctrl_base = ctrl; 145 omap4_ctrl_pad_base = ctrl_pad; 146 } 147 148 void __iomem *omap_ctrl_base_get(void) 149 { 150 return omap2_ctrl_base; 151 } 152 153 u8 omap_ctrl_readb(u16 offset) 154 { 155 return readb_relaxed(OMAP_CTRL_REGADDR(offset)); 156 } 157 158 u16 omap_ctrl_readw(u16 offset) 159 { 160 return readw_relaxed(OMAP_CTRL_REGADDR(offset)); 161 } 162 163 u32 omap_ctrl_readl(u16 offset) 164 { 165 return readl_relaxed(OMAP_CTRL_REGADDR(offset)); 166 } 167 168 void omap_ctrl_writeb(u8 val, u16 offset) 169 { 170 writeb_relaxed(val, OMAP_CTRL_REGADDR(offset)); 171 } 172 173 void omap_ctrl_writew(u16 val, u16 offset) 174 { 175 writew_relaxed(val, OMAP_CTRL_REGADDR(offset)); 176 } 177 178 void omap_ctrl_writel(u32 val, u16 offset) 179 { 180 writel_relaxed(val, OMAP_CTRL_REGADDR(offset)); 181 } 182 183 /* 184 * On OMAP4 control pad are not addressable from control 185 * core base. So the common omap_ctrl_read/write APIs breaks 186 * Hence export separate APIs to manage the omap4 pad control 187 * registers. This APIs will work only for OMAP4 188 */ 189 190 u32 omap4_ctrl_pad_readl(u16 offset) 191 { 192 return readl_relaxed(OMAP4_CTRL_PAD_REGADDR(offset)); 193 } 194 195 void omap4_ctrl_pad_writel(u32 val, u16 offset) 196 { 197 writel_relaxed(val, OMAP4_CTRL_PAD_REGADDR(offset)); 198 } 199 200 #ifdef CONFIG_ARCH_OMAP3 201 202 /** 203 * omap3_ctrl_write_boot_mode - set scratchpad boot mode for the next boot 204 * @bootmode: 8-bit value to pass to some boot code 205 * 206 * Set the bootmode in the scratchpad RAM. This is used after the 207 * system restarts. Not sure what actually uses this - it may be the 208 * bootloader, rather than the boot ROM - contrary to the preserved 209 * comment below. No return value. 210 */ 211 void omap3_ctrl_write_boot_mode(u8 bootmode) 212 { 213 u32 l; 214 215 l = ('B' << 24) | ('M' << 16) | bootmode; 216 217 /* 218 * Reserve the first word in scratchpad for communicating 219 * with the boot ROM. A pointer to a data structure 220 * describing the boot process can be stored there, 221 * cf. OMAP34xx TRM, Initialization / Software Booting 222 * Configuration. 223 * 224 * XXX This should use some omap_ctrl_writel()-type function 225 */ 226 writel_relaxed(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4)); 227 } 228 229 #endif 230 231 /** 232 * omap_ctrl_write_dsp_boot_addr - set boot address for a remote processor 233 * @bootaddr: physical address of the boot loader 234 * 235 * Set boot address for the boot loader of a supported processor 236 * when a power ON sequence occurs. 237 */ 238 void omap_ctrl_write_dsp_boot_addr(u32 bootaddr) 239 { 240 u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTADDR : 241 cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTADDR : 242 cpu_is_omap44xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR : 243 soc_is_omap54xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR : 244 0; 245 246 if (!offset) { 247 pr_err("%s: unsupported omap type\n", __func__); 248 return; 249 } 250 251 omap_ctrl_writel(bootaddr, offset); 252 } 253 254 /** 255 * omap_ctrl_write_dsp_boot_mode - set boot mode for a remote processor 256 * @bootmode: 8-bit value to pass to some boot code 257 * 258 * Sets boot mode for the boot loader of a supported processor 259 * when a power ON sequence occurs. 260 */ 261 void omap_ctrl_write_dsp_boot_mode(u8 bootmode) 262 { 263 u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTMOD : 264 cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTMOD : 265 0; 266 267 if (!offset) { 268 pr_err("%s: unsupported omap type\n", __func__); 269 return; 270 } 271 272 omap_ctrl_writel(bootmode, offset); 273 } 274 275 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 276 /* 277 * Clears the scratchpad contents in case of cold boot- 278 * called during bootup 279 */ 280 void omap3_clear_scratchpad_contents(void) 281 { 282 u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET; 283 void __iomem *v_addr; 284 u32 offset = 0; 285 286 v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM); 287 if (omap3xxx_prm_clear_global_cold_reset()) { 288 for ( ; offset <= max_offset; offset += 0x4) 289 writel_relaxed(0x0, (v_addr + offset)); 290 } 291 } 292 293 /* Populate the scratchpad structure with restore structure */ 294 void omap3_save_scratchpad_contents(void) 295 { 296 void __iomem *scratchpad_address; 297 u32 arm_context_addr; 298 struct omap3_scratchpad scratchpad_contents; 299 struct omap3_scratchpad_prcm_block prcm_block_contents; 300 struct omap3_scratchpad_sdrc_block sdrc_block_contents; 301 302 /* 303 * Populate the Scratchpad contents 304 * 305 * The "get_*restore_pointer" functions are used to provide a 306 * physical restore address where the ROM code jumps while waking 307 * up from MPU OFF/OSWR state. 308 * The restore pointer is stored into the scratchpad. 309 */ 310 scratchpad_contents.boot_config_ptr = 0x0; 311 if (cpu_is_omap3630()) 312 scratchpad_contents.public_restore_ptr = 313 virt_to_phys(omap3_restore_3630); 314 else if (omap_rev() != OMAP3430_REV_ES3_0 && 315 omap_rev() != OMAP3430_REV_ES3_1 && 316 omap_rev() != OMAP3430_REV_ES3_1_2) 317 scratchpad_contents.public_restore_ptr = 318 virt_to_phys(omap3_restore); 319 else 320 scratchpad_contents.public_restore_ptr = 321 virt_to_phys(omap3_restore_es3); 322 323 if (omap_type() == OMAP2_DEVICE_TYPE_GP) 324 scratchpad_contents.secure_ram_restore_ptr = 0x0; 325 else 326 scratchpad_contents.secure_ram_restore_ptr = 327 (u32) __pa(omap3_secure_ram_storage); 328 scratchpad_contents.sdrc_module_semaphore = 0x0; 329 scratchpad_contents.prcm_block_offset = 0x2C; 330 scratchpad_contents.sdrc_block_offset = 0x64; 331 332 /* Populate the PRCM block contents */ 333 omap3_prm_save_scratchpad_contents(prcm_block_contents.prm_contents); 334 omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents); 335 336 prcm_block_contents.prcm_block_size = 0x0; 337 338 /* Populate the SDRC block contents */ 339 sdrc_block_contents.sysconfig = 340 (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF); 341 sdrc_block_contents.cs_cfg = 342 (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF); 343 sdrc_block_contents.sharing = 344 (sdrc_read_reg(SDRC_SHARING) & 0xFFFF); 345 sdrc_block_contents.err_type = 346 (sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF); 347 sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL); 348 sdrc_block_contents.dll_b_ctrl = 0x0; 349 /* 350 * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should 351 * be programed to issue automatic self refresh on timeout 352 * of AUTO_CNT = 1 prior to any transition to OFF mode. 353 */ 354 if ((omap_type() != OMAP2_DEVICE_TYPE_GP) 355 && (omap_rev() >= OMAP3430_REV_ES3_0)) 356 sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) & 357 ~(SDRC_POWER_AUTOCOUNT_MASK| 358 SDRC_POWER_CLKCTRL_MASK)) | 359 (1 << SDRC_POWER_AUTOCOUNT_SHIFT) | 360 SDRC_SELF_REFRESH_ON_AUTOCOUNT; 361 else 362 sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER); 363 364 sdrc_block_contents.cs_0 = 0x0; 365 sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0); 366 sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF); 367 sdrc_block_contents.emr_1_0 = 0x0; 368 sdrc_block_contents.emr_2_0 = 0x0; 369 sdrc_block_contents.emr_3_0 = 0x0; 370 sdrc_block_contents.actim_ctrla_0 = 371 sdrc_read_reg(SDRC_ACTIM_CTRL_A_0); 372 sdrc_block_contents.actim_ctrlb_0 = 373 sdrc_read_reg(SDRC_ACTIM_CTRL_B_0); 374 sdrc_block_contents.rfr_ctrl_0 = 375 sdrc_read_reg(SDRC_RFR_CTRL_0); 376 sdrc_block_contents.cs_1 = 0x0; 377 sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1); 378 sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF; 379 sdrc_block_contents.emr_1_1 = 0x0; 380 sdrc_block_contents.emr_2_1 = 0x0; 381 sdrc_block_contents.emr_3_1 = 0x0; 382 sdrc_block_contents.actim_ctrla_1 = 383 sdrc_read_reg(SDRC_ACTIM_CTRL_A_1); 384 sdrc_block_contents.actim_ctrlb_1 = 385 sdrc_read_reg(SDRC_ACTIM_CTRL_B_1); 386 sdrc_block_contents.rfr_ctrl_1 = 387 sdrc_read_reg(SDRC_RFR_CTRL_1); 388 sdrc_block_contents.dcdl_1_ctrl = 0x0; 389 sdrc_block_contents.dcdl_2_ctrl = 0x0; 390 sdrc_block_contents.flags = 0x0; 391 sdrc_block_contents.block_size = 0x0; 392 393 arm_context_addr = virt_to_phys(omap3_arm_context); 394 395 /* Copy all the contents to the scratchpad location */ 396 scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD); 397 memcpy_toio(scratchpad_address, &scratchpad_contents, 398 sizeof(scratchpad_contents)); 399 /* Scratchpad contents being 32 bits, a divide by 4 done here */ 400 memcpy_toio(scratchpad_address + 401 scratchpad_contents.prcm_block_offset, 402 &prcm_block_contents, sizeof(prcm_block_contents)); 403 memcpy_toio(scratchpad_address + 404 scratchpad_contents.sdrc_block_offset, 405 &sdrc_block_contents, sizeof(sdrc_block_contents)); 406 /* 407 * Copies the address of the location in SDRAM where ARM 408 * registers get saved during a MPU OFF transition. 409 */ 410 memcpy_toio(scratchpad_address + 411 scratchpad_contents.sdrc_block_offset + 412 sizeof(sdrc_block_contents), &arm_context_addr, 4); 413 } 414 415 void omap3_control_save_context(void) 416 { 417 control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG); 418 control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); 419 control_context.mem_dftrw0 = 420 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0); 421 control_context.mem_dftrw1 = 422 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1); 423 control_context.msuspendmux_0 = 424 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0); 425 control_context.msuspendmux_1 = 426 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1); 427 control_context.msuspendmux_2 = 428 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2); 429 control_context.msuspendmux_3 = 430 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3); 431 control_context.msuspendmux_4 = 432 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4); 433 control_context.msuspendmux_5 = 434 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5); 435 control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL); 436 control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1); 437 control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE); 438 control_context.iva2_bootaddr = 439 omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR); 440 control_context.iva2_bootmod = 441 omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD); 442 control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0)); 443 control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1)); 444 control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2)); 445 control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3)); 446 control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4)); 447 control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5)); 448 control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6)); 449 control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7)); 450 control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8)); 451 control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0); 452 control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1); 453 control_context.dss_dpll_spreading = 454 omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING); 455 control_context.core_dpll_spreading = 456 omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING); 457 control_context.per_dpll_spreading = 458 omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING); 459 control_context.usbhost_dpll_spreading = 460 omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING); 461 control_context.pbias_lite = 462 omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE); 463 control_context.temp_sensor = 464 omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR); 465 control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4); 466 control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5); 467 control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI); 468 control_context.padconf_sys_nirq = 469 omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ); 470 } 471 472 void omap3_control_restore_context(void) 473 { 474 omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG); 475 omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0); 476 omap_ctrl_writel(control_context.mem_dftrw0, 477 OMAP343X_CONTROL_MEM_DFTRW0); 478 omap_ctrl_writel(control_context.mem_dftrw1, 479 OMAP343X_CONTROL_MEM_DFTRW1); 480 omap_ctrl_writel(control_context.msuspendmux_0, 481 OMAP2_CONTROL_MSUSPENDMUX_0); 482 omap_ctrl_writel(control_context.msuspendmux_1, 483 OMAP2_CONTROL_MSUSPENDMUX_1); 484 omap_ctrl_writel(control_context.msuspendmux_2, 485 OMAP2_CONTROL_MSUSPENDMUX_2); 486 omap_ctrl_writel(control_context.msuspendmux_3, 487 OMAP2_CONTROL_MSUSPENDMUX_3); 488 omap_ctrl_writel(control_context.msuspendmux_4, 489 OMAP2_CONTROL_MSUSPENDMUX_4); 490 omap_ctrl_writel(control_context.msuspendmux_5, 491 OMAP2_CONTROL_MSUSPENDMUX_5); 492 omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL); 493 omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1); 494 omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE); 495 omap_ctrl_writel(control_context.iva2_bootaddr, 496 OMAP343X_CONTROL_IVA2_BOOTADDR); 497 omap_ctrl_writel(control_context.iva2_bootmod, 498 OMAP343X_CONTROL_IVA2_BOOTMOD); 499 omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0)); 500 omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1)); 501 omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2)); 502 omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3)); 503 omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4)); 504 omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5)); 505 omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6)); 506 omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7)); 507 omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8)); 508 omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0); 509 omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1); 510 omap_ctrl_writel(control_context.dss_dpll_spreading, 511 OMAP343X_CONTROL_DSS_DPLL_SPREADING); 512 omap_ctrl_writel(control_context.core_dpll_spreading, 513 OMAP343X_CONTROL_CORE_DPLL_SPREADING); 514 omap_ctrl_writel(control_context.per_dpll_spreading, 515 OMAP343X_CONTROL_PER_DPLL_SPREADING); 516 omap_ctrl_writel(control_context.usbhost_dpll_spreading, 517 OMAP343X_CONTROL_USBHOST_DPLL_SPREADING); 518 omap_ctrl_writel(control_context.pbias_lite, 519 OMAP343X_CONTROL_PBIAS_LITE); 520 omap_ctrl_writel(control_context.temp_sensor, 521 OMAP343X_CONTROL_TEMP_SENSOR); 522 omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4); 523 omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5); 524 omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI); 525 omap_ctrl_writel(control_context.padconf_sys_nirq, 526 OMAP343X_CONTROL_PADCONF_SYSNIRQ); 527 } 528 529 void omap3630_ctrl_disable_rta(void) 530 { 531 if (!cpu_is_omap3630()) 532 return; 533 omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL); 534 } 535 536 /** 537 * omap3_ctrl_save_padconf - save padconf registers to scratchpad RAM 538 * 539 * Tell the SCM to start saving the padconf registers, then wait for 540 * the process to complete. Returns 0 unconditionally, although it 541 * should also eventually be able to return -ETIMEDOUT, if the save 542 * does not complete. 543 * 544 * XXX This function is missing a timeout. What should it be? 545 */ 546 int omap3_ctrl_save_padconf(void) 547 { 548 u32 cpo; 549 550 /* Save the padconf registers */ 551 cpo = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF); 552 cpo |= START_PADCONF_SAVE; 553 omap_ctrl_writel(cpo, OMAP343X_CONTROL_PADCONF_OFF); 554 555 /* wait for the save to complete */ 556 while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS) 557 & PADCONF_SAVE_DONE)) 558 udelay(1); 559 560 return 0; 561 } 562 563 /** 564 * omap3_ctrl_set_iva_bootmode_idle - sets the IVA2 bootmode to idle 565 * 566 * Sets the bootmode for IVA2 to idle. This is needed by the PM code to 567 * force disable IVA2 so that it does not prevent any low-power states. 568 */ 569 static void __init omap3_ctrl_set_iva_bootmode_idle(void) 570 { 571 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, 572 OMAP343X_CONTROL_IVA2_BOOTMOD); 573 } 574 575 /** 576 * omap3_ctrl_setup_d2d_padconf - setup stacked modem pads for idle 577 * 578 * Sets up the pads controlling the stacked modem in such way that the 579 * device can enter idle. 580 */ 581 static void __init omap3_ctrl_setup_d2d_padconf(void) 582 { 583 u16 mask, padconf; 584 585 /* 586 * In a stand alone OMAP3430 where there is not a stacked 587 * modem for the D2D Idle Ack and D2D MStandby must be pulled 588 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and 589 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. 590 */ 591 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ 592 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); 593 padconf |= mask; 594 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); 595 596 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); 597 padconf |= mask; 598 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); 599 } 600 601 /** 602 * omap3_ctrl_init - does static initializations for control module 603 * 604 * Initializes system control module. This sets up the sysconfig autoidle, 605 * and sets up modem and iva2 so that they can be idled properly. 606 */ 607 void __init omap3_ctrl_init(void) 608 { 609 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); 610 611 omap3_ctrl_set_iva_bootmode_idle(); 612 613 omap3_ctrl_setup_d2d_padconf(); 614 } 615 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ 616 617 struct control_init_data { 618 int index; 619 void __iomem *mem; 620 }; 621 622 static struct control_init_data ctrl_data = { 623 .index = TI_CLKM_CTRL, 624 }; 625 626 static const struct of_device_id omap_scrm_dt_match_table[] = { 627 { .compatible = "ti,am3-scrm", .data = &ctrl_data }, 628 { .compatible = "ti,am4-scrm", .data = &ctrl_data }, 629 { .compatible = "ti,omap2-scrm", .data = &ctrl_data }, 630 { .compatible = "ti,omap3-scrm", .data = &ctrl_data }, 631 { .compatible = "ti,dm816-scrm", .data = &ctrl_data }, 632 { } 633 }; 634 635 /** 636 * omap2_control_base_init - initialize iomappings for the control driver 637 * 638 * Detects and initializes the iomappings for the control driver, based 639 * on the DT data. Returns 0 in success, negative error value 640 * otherwise. 641 */ 642 int __init omap2_control_base_init(void) 643 { 644 struct device_node *np; 645 const struct of_device_id *match; 646 struct control_init_data *data; 647 void __iomem *mem; 648 649 for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) { 650 data = (struct control_init_data *)match->data; 651 652 mem = of_iomap(np, 0); 653 if (!mem) 654 return -ENOMEM; 655 656 omap2_ctrl_base = mem; 657 data->mem = mem; 658 } 659 660 return 0; 661 } 662 663 /** 664 * omap_control_init - low level init for the control driver 665 * 666 * Initializes the low level clock infrastructure for control driver. 667 * Returns 0 in success, negative error value in failure. 668 */ 669 int __init omap_control_init(void) 670 { 671 struct device_node *np; 672 const struct of_device_id *match; 673 const struct omap_prcm_init_data *data; 674 int ret; 675 676 for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) { 677 data = match->data; 678 679 ret = omap2_clk_provider_init(np, data->index, data->mem); 680 if (ret) 681 return ret; 682 } 683 684 return 0; 685 } 686 687 /** 688 * omap3_control_legacy_iomap_init - legacy iomap init for clock providers 689 * 690 * Legacy iomap init for clock provider. Needed only by legacy boot mode, 691 * where the base addresses are not parsed from DT, but still required 692 * by the clock driver to be setup properly. 693 */ 694 void __init omap3_control_legacy_iomap_init(void) 695 { 696 omap2_clk_legacy_provider_init(TI_CLKM_SCRM, omap2_ctrl_base); 697 } 698