1 /* 2 * OMAP2/3 System Control Module register access 3 * 4 * Copyright (C) 2007 Texas Instruments, Inc. 5 * Copyright (C) 2007 Nokia Corporation 6 * 7 * Written by Paul Walmsley 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 #undef DEBUG 14 15 #include <linux/kernel.h> 16 #include <linux/io.h> 17 18 #include <plat/common.h> 19 #include <plat/sdrc.h> 20 21 #include "cm-regbits-34xx.h" 22 #include "prm-regbits-34xx.h" 23 #include "prm2xxx_3xxx.h" 24 #include "cm2xxx_3xxx.h" 25 #include "sdrc.h" 26 #include "pm.h" 27 #include "control.h" 28 29 /* Used by omap3_ctrl_save_padconf() */ 30 #define START_PADCONF_SAVE 0x2 31 #define PADCONF_SAVE_DONE 0x1 32 33 static void __iomem *omap2_ctrl_base; 34 static void __iomem *omap4_ctrl_pad_base; 35 36 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 37 struct omap3_scratchpad { 38 u32 boot_config_ptr; 39 u32 public_restore_ptr; 40 u32 secure_ram_restore_ptr; 41 u32 sdrc_module_semaphore; 42 u32 prcm_block_offset; 43 u32 sdrc_block_offset; 44 }; 45 46 struct omap3_scratchpad_prcm_block { 47 u32 prm_clksrc_ctrl; 48 u32 prm_clksel; 49 u32 cm_clksel_core; 50 u32 cm_clksel_wkup; 51 u32 cm_clken_pll; 52 u32 cm_autoidle_pll; 53 u32 cm_clksel1_pll; 54 u32 cm_clksel2_pll; 55 u32 cm_clksel3_pll; 56 u32 cm_clken_pll_mpu; 57 u32 cm_autoidle_pll_mpu; 58 u32 cm_clksel1_pll_mpu; 59 u32 cm_clksel2_pll_mpu; 60 u32 prcm_block_size; 61 }; 62 63 struct omap3_scratchpad_sdrc_block { 64 u16 sysconfig; 65 u16 cs_cfg; 66 u16 sharing; 67 u16 err_type; 68 u32 dll_a_ctrl; 69 u32 dll_b_ctrl; 70 u32 power; 71 u32 cs_0; 72 u32 mcfg_0; 73 u16 mr_0; 74 u16 emr_1_0; 75 u16 emr_2_0; 76 u16 emr_3_0; 77 u32 actim_ctrla_0; 78 u32 actim_ctrlb_0; 79 u32 rfr_ctrl_0; 80 u32 cs_1; 81 u32 mcfg_1; 82 u16 mr_1; 83 u16 emr_1_1; 84 u16 emr_2_1; 85 u16 emr_3_1; 86 u32 actim_ctrla_1; 87 u32 actim_ctrlb_1; 88 u32 rfr_ctrl_1; 89 u16 dcdl_1_ctrl; 90 u16 dcdl_2_ctrl; 91 u32 flags; 92 u32 block_size; 93 }; 94 95 void *omap3_secure_ram_storage; 96 97 /* 98 * This is used to store ARM registers in SDRAM before attempting 99 * an MPU OFF. The save and restore happens from the SRAM sleep code. 100 * The address is stored in scratchpad, so that it can be used 101 * during the restore path. 102 */ 103 u32 omap3_arm_context[128]; 104 105 struct omap3_control_regs { 106 u32 sysconfig; 107 u32 devconf0; 108 u32 mem_dftrw0; 109 u32 mem_dftrw1; 110 u32 msuspendmux_0; 111 u32 msuspendmux_1; 112 u32 msuspendmux_2; 113 u32 msuspendmux_3; 114 u32 msuspendmux_4; 115 u32 msuspendmux_5; 116 u32 sec_ctrl; 117 u32 devconf1; 118 u32 csirxfe; 119 u32 iva2_bootaddr; 120 u32 iva2_bootmod; 121 u32 debobs_0; 122 u32 debobs_1; 123 u32 debobs_2; 124 u32 debobs_3; 125 u32 debobs_4; 126 u32 debobs_5; 127 u32 debobs_6; 128 u32 debobs_7; 129 u32 debobs_8; 130 u32 prog_io0; 131 u32 prog_io1; 132 u32 dss_dpll_spreading; 133 u32 core_dpll_spreading; 134 u32 per_dpll_spreading; 135 u32 usbhost_dpll_spreading; 136 u32 pbias_lite; 137 u32 temp_sensor; 138 u32 sramldo4; 139 u32 sramldo5; 140 u32 csi; 141 u32 padconf_sys_nirq; 142 }; 143 144 static struct omap3_control_regs control_context; 145 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ 146 147 #define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg)) 148 #define OMAP4_CTRL_PAD_REGADDR(reg) (omap4_ctrl_pad_base + (reg)) 149 150 void __init omap2_set_globals_control(struct omap_globals *omap2_globals) 151 { 152 if (omap2_globals->ctrl) 153 omap2_ctrl_base = omap2_globals->ctrl; 154 155 if (omap2_globals->ctrl_pad) 156 omap4_ctrl_pad_base = omap2_globals->ctrl_pad; 157 } 158 159 void __iomem *omap_ctrl_base_get(void) 160 { 161 return omap2_ctrl_base; 162 } 163 164 u8 omap_ctrl_readb(u16 offset) 165 { 166 return __raw_readb(OMAP_CTRL_REGADDR(offset)); 167 } 168 169 u16 omap_ctrl_readw(u16 offset) 170 { 171 return __raw_readw(OMAP_CTRL_REGADDR(offset)); 172 } 173 174 u32 omap_ctrl_readl(u16 offset) 175 { 176 return __raw_readl(OMAP_CTRL_REGADDR(offset)); 177 } 178 179 void omap_ctrl_writeb(u8 val, u16 offset) 180 { 181 __raw_writeb(val, OMAP_CTRL_REGADDR(offset)); 182 } 183 184 void omap_ctrl_writew(u16 val, u16 offset) 185 { 186 __raw_writew(val, OMAP_CTRL_REGADDR(offset)); 187 } 188 189 void omap_ctrl_writel(u32 val, u16 offset) 190 { 191 __raw_writel(val, OMAP_CTRL_REGADDR(offset)); 192 } 193 194 /* 195 * On OMAP4 control pad are not addressable from control 196 * core base. So the common omap_ctrl_read/write APIs breaks 197 * Hence export separate APIs to manage the omap4 pad control 198 * registers. This APIs will work only for OMAP4 199 */ 200 201 u32 omap4_ctrl_pad_readl(u16 offset) 202 { 203 return __raw_readl(OMAP4_CTRL_PAD_REGADDR(offset)); 204 } 205 206 void omap4_ctrl_pad_writel(u32 val, u16 offset) 207 { 208 __raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset)); 209 } 210 211 #ifdef CONFIG_ARCH_OMAP3 212 213 /** 214 * omap3_ctrl_write_boot_mode - set scratchpad boot mode for the next boot 215 * @bootmode: 8-bit value to pass to some boot code 216 * 217 * Set the bootmode in the scratchpad RAM. This is used after the 218 * system restarts. Not sure what actually uses this - it may be the 219 * bootloader, rather than the boot ROM - contrary to the preserved 220 * comment below. No return value. 221 */ 222 void omap3_ctrl_write_boot_mode(u8 bootmode) 223 { 224 u32 l; 225 226 l = ('B' << 24) | ('M' << 16) | bootmode; 227 228 /* 229 * Reserve the first word in scratchpad for communicating 230 * with the boot ROM. A pointer to a data structure 231 * describing the boot process can be stored there, 232 * cf. OMAP34xx TRM, Initialization / Software Booting 233 * Configuration. 234 * 235 * XXX This should use some omap_ctrl_writel()-type function 236 */ 237 __raw_writel(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4)); 238 } 239 240 #endif 241 242 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 243 /* 244 * Clears the scratchpad contents in case of cold boot- 245 * called during bootup 246 */ 247 void omap3_clear_scratchpad_contents(void) 248 { 249 u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET; 250 void __iomem *v_addr; 251 u32 offset = 0; 252 v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM); 253 if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) & 254 OMAP3430_GLOBAL_COLD_RST_MASK) { 255 for ( ; offset <= max_offset; offset += 0x4) 256 __raw_writel(0x0, (v_addr + offset)); 257 omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK, 258 OMAP3430_GR_MOD, 259 OMAP3_PRM_RSTST_OFFSET); 260 } 261 } 262 263 /* Populate the scratchpad structure with restore structure */ 264 void omap3_save_scratchpad_contents(void) 265 { 266 void __iomem *scratchpad_address; 267 u32 arm_context_addr; 268 struct omap3_scratchpad scratchpad_contents; 269 struct omap3_scratchpad_prcm_block prcm_block_contents; 270 struct omap3_scratchpad_sdrc_block sdrc_block_contents; 271 272 /* 273 * Populate the Scratchpad contents 274 * 275 * The "get_*restore_pointer" functions are used to provide a 276 * physical restore address where the ROM code jumps while waking 277 * up from MPU OFF/OSWR state. 278 * The restore pointer is stored into the scratchpad. 279 */ 280 scratchpad_contents.boot_config_ptr = 0x0; 281 if (cpu_is_omap3630()) 282 scratchpad_contents.public_restore_ptr = 283 virt_to_phys(omap3_restore_3630); 284 else if (omap_rev() != OMAP3430_REV_ES3_0 && 285 omap_rev() != OMAP3430_REV_ES3_1) 286 scratchpad_contents.public_restore_ptr = 287 virt_to_phys(omap3_restore); 288 else 289 scratchpad_contents.public_restore_ptr = 290 virt_to_phys(omap3_restore_es3); 291 292 if (omap_type() == OMAP2_DEVICE_TYPE_GP) 293 scratchpad_contents.secure_ram_restore_ptr = 0x0; 294 else 295 scratchpad_contents.secure_ram_restore_ptr = 296 (u32) __pa(omap3_secure_ram_storage); 297 scratchpad_contents.sdrc_module_semaphore = 0x0; 298 scratchpad_contents.prcm_block_offset = 0x2C; 299 scratchpad_contents.sdrc_block_offset = 0x64; 300 301 /* Populate the PRCM block contents */ 302 prcm_block_contents.prm_clksrc_ctrl = 303 omap2_prm_read_mod_reg(OMAP3430_GR_MOD, 304 OMAP3_PRM_CLKSRC_CTRL_OFFSET); 305 prcm_block_contents.prm_clksel = 306 omap2_prm_read_mod_reg(OMAP3430_CCR_MOD, 307 OMAP3_PRM_CLKSEL_OFFSET); 308 prcm_block_contents.cm_clksel_core = 309 omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL); 310 prcm_block_contents.cm_clksel_wkup = 311 omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL); 312 prcm_block_contents.cm_clken_pll = 313 omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); 314 /* 315 * As per erratum i671, ROM code does not respect the PER DPLL 316 * programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1. 317 * Then, in anycase, clear these bits to avoid extra latencies. 318 */ 319 prcm_block_contents.cm_autoidle_pll = 320 omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) & 321 ~OMAP3430_AUTO_PERIPH_DPLL_MASK; 322 prcm_block_contents.cm_clksel1_pll = 323 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL); 324 prcm_block_contents.cm_clksel2_pll = 325 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL); 326 prcm_block_contents.cm_clksel3_pll = 327 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3); 328 prcm_block_contents.cm_clken_pll_mpu = 329 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL); 330 prcm_block_contents.cm_autoidle_pll_mpu = 331 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL); 332 prcm_block_contents.cm_clksel1_pll_mpu = 333 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL); 334 prcm_block_contents.cm_clksel2_pll_mpu = 335 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL); 336 prcm_block_contents.prcm_block_size = 0x0; 337 338 /* Populate the SDRC block contents */ 339 sdrc_block_contents.sysconfig = 340 (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF); 341 sdrc_block_contents.cs_cfg = 342 (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF); 343 sdrc_block_contents.sharing = 344 (sdrc_read_reg(SDRC_SHARING) & 0xFFFF); 345 sdrc_block_contents.err_type = 346 (sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF); 347 sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL); 348 sdrc_block_contents.dll_b_ctrl = 0x0; 349 /* 350 * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should 351 * be programed to issue automatic self refresh on timeout 352 * of AUTO_CNT = 1 prior to any transition to OFF mode. 353 */ 354 if ((omap_type() != OMAP2_DEVICE_TYPE_GP) 355 && (omap_rev() >= OMAP3430_REV_ES3_0)) 356 sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) & 357 ~(SDRC_POWER_AUTOCOUNT_MASK| 358 SDRC_POWER_CLKCTRL_MASK)) | 359 (1 << SDRC_POWER_AUTOCOUNT_SHIFT) | 360 SDRC_SELF_REFRESH_ON_AUTOCOUNT; 361 else 362 sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER); 363 364 sdrc_block_contents.cs_0 = 0x0; 365 sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0); 366 sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF); 367 sdrc_block_contents.emr_1_0 = 0x0; 368 sdrc_block_contents.emr_2_0 = 0x0; 369 sdrc_block_contents.emr_3_0 = 0x0; 370 sdrc_block_contents.actim_ctrla_0 = 371 sdrc_read_reg(SDRC_ACTIM_CTRL_A_0); 372 sdrc_block_contents.actim_ctrlb_0 = 373 sdrc_read_reg(SDRC_ACTIM_CTRL_B_0); 374 sdrc_block_contents.rfr_ctrl_0 = 375 sdrc_read_reg(SDRC_RFR_CTRL_0); 376 sdrc_block_contents.cs_1 = 0x0; 377 sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1); 378 sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF; 379 sdrc_block_contents.emr_1_1 = 0x0; 380 sdrc_block_contents.emr_2_1 = 0x0; 381 sdrc_block_contents.emr_3_1 = 0x0; 382 sdrc_block_contents.actim_ctrla_1 = 383 sdrc_read_reg(SDRC_ACTIM_CTRL_A_1); 384 sdrc_block_contents.actim_ctrlb_1 = 385 sdrc_read_reg(SDRC_ACTIM_CTRL_B_1); 386 sdrc_block_contents.rfr_ctrl_1 = 387 sdrc_read_reg(SDRC_RFR_CTRL_1); 388 sdrc_block_contents.dcdl_1_ctrl = 0x0; 389 sdrc_block_contents.dcdl_2_ctrl = 0x0; 390 sdrc_block_contents.flags = 0x0; 391 sdrc_block_contents.block_size = 0x0; 392 393 arm_context_addr = virt_to_phys(omap3_arm_context); 394 395 /* Copy all the contents to the scratchpad location */ 396 scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD); 397 memcpy_toio(scratchpad_address, &scratchpad_contents, 398 sizeof(scratchpad_contents)); 399 /* Scratchpad contents being 32 bits, a divide by 4 done here */ 400 memcpy_toio(scratchpad_address + 401 scratchpad_contents.prcm_block_offset, 402 &prcm_block_contents, sizeof(prcm_block_contents)); 403 memcpy_toio(scratchpad_address + 404 scratchpad_contents.sdrc_block_offset, 405 &sdrc_block_contents, sizeof(sdrc_block_contents)); 406 /* 407 * Copies the address of the location in SDRAM where ARM 408 * registers get saved during a MPU OFF transition. 409 */ 410 memcpy_toio(scratchpad_address + 411 scratchpad_contents.sdrc_block_offset + 412 sizeof(sdrc_block_contents), &arm_context_addr, 4); 413 } 414 415 void omap3_control_save_context(void) 416 { 417 control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG); 418 control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); 419 control_context.mem_dftrw0 = 420 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0); 421 control_context.mem_dftrw1 = 422 omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1); 423 control_context.msuspendmux_0 = 424 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0); 425 control_context.msuspendmux_1 = 426 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1); 427 control_context.msuspendmux_2 = 428 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2); 429 control_context.msuspendmux_3 = 430 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3); 431 control_context.msuspendmux_4 = 432 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4); 433 control_context.msuspendmux_5 = 434 omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5); 435 control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL); 436 control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1); 437 control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE); 438 control_context.iva2_bootaddr = 439 omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR); 440 control_context.iva2_bootmod = 441 omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD); 442 control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0)); 443 control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1)); 444 control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2)); 445 control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3)); 446 control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4)); 447 control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5)); 448 control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6)); 449 control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7)); 450 control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8)); 451 control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0); 452 control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1); 453 control_context.dss_dpll_spreading = 454 omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING); 455 control_context.core_dpll_spreading = 456 omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING); 457 control_context.per_dpll_spreading = 458 omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING); 459 control_context.usbhost_dpll_spreading = 460 omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING); 461 control_context.pbias_lite = 462 omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE); 463 control_context.temp_sensor = 464 omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR); 465 control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4); 466 control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5); 467 control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI); 468 control_context.padconf_sys_nirq = 469 omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ); 470 return; 471 } 472 473 void omap3_control_restore_context(void) 474 { 475 omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG); 476 omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0); 477 omap_ctrl_writel(control_context.mem_dftrw0, 478 OMAP343X_CONTROL_MEM_DFTRW0); 479 omap_ctrl_writel(control_context.mem_dftrw1, 480 OMAP343X_CONTROL_MEM_DFTRW1); 481 omap_ctrl_writel(control_context.msuspendmux_0, 482 OMAP2_CONTROL_MSUSPENDMUX_0); 483 omap_ctrl_writel(control_context.msuspendmux_1, 484 OMAP2_CONTROL_MSUSPENDMUX_1); 485 omap_ctrl_writel(control_context.msuspendmux_2, 486 OMAP2_CONTROL_MSUSPENDMUX_2); 487 omap_ctrl_writel(control_context.msuspendmux_3, 488 OMAP2_CONTROL_MSUSPENDMUX_3); 489 omap_ctrl_writel(control_context.msuspendmux_4, 490 OMAP2_CONTROL_MSUSPENDMUX_4); 491 omap_ctrl_writel(control_context.msuspendmux_5, 492 OMAP2_CONTROL_MSUSPENDMUX_5); 493 omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL); 494 omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1); 495 omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE); 496 omap_ctrl_writel(control_context.iva2_bootaddr, 497 OMAP343X_CONTROL_IVA2_BOOTADDR); 498 omap_ctrl_writel(control_context.iva2_bootmod, 499 OMAP343X_CONTROL_IVA2_BOOTMOD); 500 omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0)); 501 omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1)); 502 omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2)); 503 omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3)); 504 omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4)); 505 omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5)); 506 omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6)); 507 omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7)); 508 omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8)); 509 omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0); 510 omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1); 511 omap_ctrl_writel(control_context.dss_dpll_spreading, 512 OMAP343X_CONTROL_DSS_DPLL_SPREADING); 513 omap_ctrl_writel(control_context.core_dpll_spreading, 514 OMAP343X_CONTROL_CORE_DPLL_SPREADING); 515 omap_ctrl_writel(control_context.per_dpll_spreading, 516 OMAP343X_CONTROL_PER_DPLL_SPREADING); 517 omap_ctrl_writel(control_context.usbhost_dpll_spreading, 518 OMAP343X_CONTROL_USBHOST_DPLL_SPREADING); 519 omap_ctrl_writel(control_context.pbias_lite, 520 OMAP343X_CONTROL_PBIAS_LITE); 521 omap_ctrl_writel(control_context.temp_sensor, 522 OMAP343X_CONTROL_TEMP_SENSOR); 523 omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4); 524 omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5); 525 omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI); 526 omap_ctrl_writel(control_context.padconf_sys_nirq, 527 OMAP343X_CONTROL_PADCONF_SYSNIRQ); 528 return; 529 } 530 531 void omap3630_ctrl_disable_rta(void) 532 { 533 if (!cpu_is_omap3630()) 534 return; 535 omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL); 536 } 537 538 /** 539 * omap3_ctrl_save_padconf - save padconf registers to scratchpad RAM 540 * 541 * Tell the SCM to start saving the padconf registers, then wait for 542 * the process to complete. Returns 0 unconditionally, although it 543 * should also eventually be able to return -ETIMEDOUT, if the save 544 * does not complete. 545 * 546 * XXX This function is missing a timeout. What should it be? 547 */ 548 int omap3_ctrl_save_padconf(void) 549 { 550 u32 cpo; 551 552 /* Save the padconf registers */ 553 cpo = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF); 554 cpo |= START_PADCONF_SAVE; 555 omap_ctrl_writel(cpo, OMAP343X_CONTROL_PADCONF_OFF); 556 557 /* wait for the save to complete */ 558 while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS) 559 & PADCONF_SAVE_DONE)) 560 udelay(1); 561 562 return 0; 563 } 564 565 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ 566