159fb659bSPaul Walmsley /* 259fb659bSPaul Walmsley * OMAP2/3 Clock Management (CM) register definitions 359fb659bSPaul Walmsley * 459fb659bSPaul Walmsley * Copyright (C) 2007-2009 Texas Instruments, Inc. 559fb659bSPaul Walmsley * Copyright (C) 2007-2010 Nokia Corporation 659fb659bSPaul Walmsley * Paul Walmsley 759fb659bSPaul Walmsley * 859fb659bSPaul Walmsley * This program is free software; you can redistribute it and/or modify 959fb659bSPaul Walmsley * it under the terms of the GNU General Public License version 2 as 1059fb659bSPaul Walmsley * published by the Free Software Foundation. 1159fb659bSPaul Walmsley * 1259fb659bSPaul Walmsley * The CM hardware modules on the OMAP2/3 are quite similar to each 1359fb659bSPaul Walmsley * other. The CM modules/instances on OMAP4 are quite different, so 1459fb659bSPaul Walmsley * they are handled in a separate file. 1559fb659bSPaul Walmsley */ 1659fb659bSPaul Walmsley #ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H 1759fb659bSPaul Walmsley #define __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H 1859fb659bSPaul Walmsley 1959fb659bSPaul Walmsley #include "prcm-common.h" 2059fb659bSPaul Walmsley 2159fb659bSPaul Walmsley #define OMAP2420_CM_REGADDR(module, reg) \ 2259fb659bSPaul Walmsley OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg)) 2359fb659bSPaul Walmsley #define OMAP2430_CM_REGADDR(module, reg) \ 2459fb659bSPaul Walmsley OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) 2559fb659bSPaul Walmsley #define OMAP34XX_CM_REGADDR(module, reg) \ 2659fb659bSPaul Walmsley OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) 2759fb659bSPaul Walmsley 2859fb659bSPaul Walmsley 2959fb659bSPaul Walmsley /* 3059fb659bSPaul Walmsley * OMAP3-specific global CM registers 3159fb659bSPaul Walmsley * Use cm_{read,write}_reg() with these registers. 3259fb659bSPaul Walmsley * These registers appear once per CM module. 3359fb659bSPaul Walmsley */ 3459fb659bSPaul Walmsley 3559fb659bSPaul Walmsley #define OMAP3430_CM_REVISION OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000) 3659fb659bSPaul Walmsley #define OMAP3430_CM_SYSCONFIG OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010) 3759fb659bSPaul Walmsley #define OMAP3430_CM_POLCTRL OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c) 3859fb659bSPaul Walmsley 3959fb659bSPaul Walmsley #define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070 4059fb659bSPaul Walmsley #define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070) 4159fb659bSPaul Walmsley 4259fb659bSPaul Walmsley /* 4359fb659bSPaul Walmsley * Module specific CM register offsets from CM_BASE + domain offset 4459fb659bSPaul Walmsley * Use cm_{read,write}_mod_reg() with these registers. 4559fb659bSPaul Walmsley * These register offsets generally appear in more than one PRCM submodule. 4659fb659bSPaul Walmsley */ 4759fb659bSPaul Walmsley 4859fb659bSPaul Walmsley /* Common between OMAP2 and OMAP3 */ 4959fb659bSPaul Walmsley 5059fb659bSPaul Walmsley #define CM_FCLKEN 0x0000 5159fb659bSPaul Walmsley #define CM_FCLKEN1 CM_FCLKEN 5259fb659bSPaul Walmsley #define CM_CLKEN CM_FCLKEN 5359fb659bSPaul Walmsley #define CM_ICLKEN 0x0010 5459fb659bSPaul Walmsley #define CM_ICLKEN1 CM_ICLKEN 5559fb659bSPaul Walmsley #define CM_ICLKEN2 0x0014 5659fb659bSPaul Walmsley #define CM_ICLKEN3 0x0018 5759fb659bSPaul Walmsley #define CM_IDLEST 0x0020 5859fb659bSPaul Walmsley #define CM_IDLEST1 CM_IDLEST 5959fb659bSPaul Walmsley #define CM_IDLEST2 0x0024 6059fb659bSPaul Walmsley #define CM_AUTOIDLE 0x0030 6159fb659bSPaul Walmsley #define CM_AUTOIDLE1 CM_AUTOIDLE 6259fb659bSPaul Walmsley #define CM_AUTOIDLE2 0x0034 6359fb659bSPaul Walmsley #define CM_AUTOIDLE3 0x0038 6459fb659bSPaul Walmsley #define CM_CLKSEL 0x0040 6559fb659bSPaul Walmsley #define CM_CLKSEL1 CM_CLKSEL 6659fb659bSPaul Walmsley #define CM_CLKSEL2 0x0044 6759fb659bSPaul Walmsley #define OMAP2_CM_CLKSTCTRL 0x0048 6859fb659bSPaul Walmsley 6959fb659bSPaul Walmsley /* OMAP2-specific register offsets */ 7059fb659bSPaul Walmsley 7159fb659bSPaul Walmsley #define OMAP24XX_CM_FCLKEN2 0x0004 7259fb659bSPaul Walmsley #define OMAP24XX_CM_ICLKEN4 0x001c 7359fb659bSPaul Walmsley #define OMAP24XX_CM_AUTOIDLE4 0x003c 7459fb659bSPaul Walmsley 7559fb659bSPaul Walmsley #define OMAP2430_CM_IDLEST3 0x0028 7659fb659bSPaul Walmsley 7759fb659bSPaul Walmsley /* OMAP3-specific register offsets */ 7859fb659bSPaul Walmsley 7959fb659bSPaul Walmsley #define OMAP3430_CM_CLKEN_PLL 0x0004 8059fb659bSPaul Walmsley #define OMAP3430ES2_CM_CLKEN2 0x0004 8159fb659bSPaul Walmsley #define OMAP3430ES2_CM_FCLKEN3 0x0008 8259fb659bSPaul Walmsley #define OMAP3430_CM_IDLEST_PLL CM_IDLEST2 8359fb659bSPaul Walmsley #define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2 8459fb659bSPaul Walmsley #define OMAP3430ES2_CM_AUTOIDLE2_PLL CM_AUTOIDLE2 8559fb659bSPaul Walmsley #define OMAP3430_CM_CLKSEL1 CM_CLKSEL 8659fb659bSPaul Walmsley #define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL 8759fb659bSPaul Walmsley #define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2 8859fb659bSPaul Walmsley #define OMAP3430_CM_SLEEPDEP CM_CLKSEL2 8959fb659bSPaul Walmsley #define OMAP3430_CM_CLKSEL3 OMAP2_CM_CLKSTCTRL 9059fb659bSPaul Walmsley #define OMAP3430_CM_CLKSTST 0x004c 9159fb659bSPaul Walmsley #define OMAP3430ES2_CM_CLKSEL4 0x004c 9259fb659bSPaul Walmsley #define OMAP3430ES2_CM_CLKSEL5 0x0050 9359fb659bSPaul Walmsley #define OMAP3430_CM_CLKSEL2_EMU 0x0050 9459fb659bSPaul Walmsley #define OMAP3430_CM_CLKSEL3_EMU 0x0054 9559fb659bSPaul Walmsley 9659fb659bSPaul Walmsley 9759fb659bSPaul Walmsley /* CM_IDLEST bit field values to indicate deasserted IdleReq */ 9859fb659bSPaul Walmsley 9959fb659bSPaul Walmsley #define OMAP24XX_CM_IDLEST_VAL 0 10059fb659bSPaul Walmsley #define OMAP34XX_CM_IDLEST_VAL 1 10159fb659bSPaul Walmsley 10259fb659bSPaul Walmsley 10359fb659bSPaul Walmsley /* Clock management domain register get/set */ 10459fb659bSPaul Walmsley 10559fb659bSPaul Walmsley #ifndef __ASSEMBLER__ 10659fb659bSPaul Walmsley 10759fb659bSPaul Walmsley extern u32 cm_read_mod_reg(s16 module, u16 idx); 10859fb659bSPaul Walmsley extern void cm_write_mod_reg(u32 val, s16 module, u16 idx); 10959fb659bSPaul Walmsley extern u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); 11059fb659bSPaul Walmsley 11159fb659bSPaul Walmsley extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, 11259fb659bSPaul Walmsley u8 idlest_shift); 11359fb659bSPaul Walmsley extern u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx); 11459fb659bSPaul Walmsley extern u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx); 11559fb659bSPaul Walmsley 11659fb659bSPaul Walmsley #endif 11759fb659bSPaul Walmsley 11859fb659bSPaul Walmsley /* CM register bits shared between 24XX and 3430 */ 11959fb659bSPaul Walmsley 12059fb659bSPaul Walmsley /* CM_CLKSEL_GFX */ 12159fb659bSPaul Walmsley #define OMAP_CLKSEL_GFX_SHIFT 0 12259fb659bSPaul Walmsley #define OMAP_CLKSEL_GFX_MASK (0x7 << 0) 12359fb659bSPaul Walmsley 12459fb659bSPaul Walmsley /* CM_ICLKEN_GFX */ 12559fb659bSPaul Walmsley #define OMAP_EN_GFX_SHIFT 0 12659fb659bSPaul Walmsley #define OMAP_EN_GFX_MASK (1 << 0) 12759fb659bSPaul Walmsley 12859fb659bSPaul Walmsley /* CM_IDLEST_GFX */ 12959fb659bSPaul Walmsley #define OMAP_ST_GFX_MASK (1 << 0) 13059fb659bSPaul Walmsley 131f0611a5cSPaul Walmsley 132f0611a5cSPaul Walmsley /* Function prototypes */ 133f0611a5cSPaul Walmsley # ifndef __ASSEMBLER__ 134f0611a5cSPaul Walmsley extern void omap3_cm_save_context(void); 135f0611a5cSPaul Walmsley extern void omap3_cm_restore_context(void); 136f0611a5cSPaul Walmsley # endif 137f0611a5cSPaul Walmsley 13859fb659bSPaul Walmsley #endif 139