140ca6091SAmbresh K /* 240ca6091SAmbresh K * DRA7xx CM2 instance offset macros 340ca6091SAmbresh K * 440ca6091SAmbresh K * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com 540ca6091SAmbresh K * 640ca6091SAmbresh K * Generated by code originally written by: 740ca6091SAmbresh K * Paul Walmsley (paul@pwsan.com) 840ca6091SAmbresh K * Rajendra Nayak (rnayak@ti.com) 940ca6091SAmbresh K * Benoit Cousson (b-cousson@ti.com) 1040ca6091SAmbresh K * 1140ca6091SAmbresh K * This file is automatically generated from the OMAP hardware databases. 1240ca6091SAmbresh K * We respectfully ask that any modifications to this file be coordinated 1340ca6091SAmbresh K * with the public linux-omap@vger.kernel.org mailing list and the 1440ca6091SAmbresh K * authors above to ensure that the autogeneration scripts are kept 1540ca6091SAmbresh K * up-to-date with the file contents. 1640ca6091SAmbresh K * 1740ca6091SAmbresh K * This program is free software; you can redistribute it and/or modify 1840ca6091SAmbresh K * it under the terms of the GNU General Public License version 2 as 1940ca6091SAmbresh K * published by the Free Software Foundation. 2040ca6091SAmbresh K */ 2140ca6091SAmbresh K 2240ca6091SAmbresh K #ifndef __ARCH_ARM_MACH_OMAP2_CM2_7XX_H 2340ca6091SAmbresh K #define __ARCH_ARM_MACH_OMAP2_CM2_7XX_H 2440ca6091SAmbresh K 2540ca6091SAmbresh K #include "cm_44xx_54xx.h" 2640ca6091SAmbresh K 2740ca6091SAmbresh K /* CM2 base address */ 2840ca6091SAmbresh K #define DRA7XX_CM_CORE_BASE 0x4a008000 2940ca6091SAmbresh K 3040ca6091SAmbresh K #define DRA7XX_CM_CORE_REGADDR(inst, reg) \ 3140ca6091SAmbresh K OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_BASE + (inst) + (reg)) 3240ca6091SAmbresh K 3340ca6091SAmbresh K /* CM_CORE instances */ 3440ca6091SAmbresh K #define DRA7XX_CM_CORE_OCP_SOCKET_INST 0x0000 3540ca6091SAmbresh K #define DRA7XX_CM_CORE_CKGEN_INST 0x0104 3640ca6091SAmbresh K #define DRA7XX_CM_CORE_COREAON_INST 0x0600 3740ca6091SAmbresh K #define DRA7XX_CM_CORE_CORE_INST 0x0700 3840ca6091SAmbresh K #define DRA7XX_CM_CORE_IVA_INST 0x0f00 3940ca6091SAmbresh K #define DRA7XX_CM_CORE_CAM_INST 0x1000 4040ca6091SAmbresh K #define DRA7XX_CM_CORE_DSS_INST 0x1100 4140ca6091SAmbresh K #define DRA7XX_CM_CORE_GPU_INST 0x1200 4240ca6091SAmbresh K #define DRA7XX_CM_CORE_L3INIT_INST 0x1300 4340ca6091SAmbresh K #define DRA7XX_CM_CORE_CUSTEFUSE_INST 0x1600 4440ca6091SAmbresh K #define DRA7XX_CM_CORE_L4PER_INST 0x1700 4540ca6091SAmbresh K #define DRA7XX_CM_CORE_RESTORE_INST 0x1e18 4640ca6091SAmbresh K 4740ca6091SAmbresh K /* CM_CORE clockdomain register offsets (from instance start) */ 4840ca6091SAmbresh K #define DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS 0x0000 4940ca6091SAmbresh K #define DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS 0x0000 5040ca6091SAmbresh K #define DRA7XX_CM_CORE_CORE_IPU2_CDOFFS 0x0200 5140ca6091SAmbresh K #define DRA7XX_CM_CORE_CORE_DMA_CDOFFS 0x0300 5240ca6091SAmbresh K #define DRA7XX_CM_CORE_CORE_EMIF_CDOFFS 0x0400 5340ca6091SAmbresh K #define DRA7XX_CM_CORE_CORE_ATL_CDOFFS 0x0520 5440ca6091SAmbresh K #define DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS 0x0600 5540ca6091SAmbresh K #define DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS 0x0700 5640ca6091SAmbresh K #define DRA7XX_CM_CORE_IVA_IVA_CDOFFS 0x0000 5740ca6091SAmbresh K #define DRA7XX_CM_CORE_CAM_CAM_CDOFFS 0x0000 5840ca6091SAmbresh K #define DRA7XX_CM_CORE_DSS_DSS_CDOFFS 0x0000 5940ca6091SAmbresh K #define DRA7XX_CM_CORE_GPU_GPU_CDOFFS 0x0000 6040ca6091SAmbresh K #define DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS 0x0000 6140ca6091SAmbresh K #define DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS 0x00a0 6240ca6091SAmbresh K #define DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS 0x00c0 6340ca6091SAmbresh K #define DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS 0x0000 6440ca6091SAmbresh K #define DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS 0x0000 6540ca6091SAmbresh K #define DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS 0x0180 6640ca6091SAmbresh K #define DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS 0x01fc 6740ca6091SAmbresh K #define DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS 0x0210 6840ca6091SAmbresh K 6940ca6091SAmbresh K /* CM_CORE */ 7040ca6091SAmbresh K 7140ca6091SAmbresh K /* CM_CORE.OCP_SOCKET_CM_CORE register offsets */ 7240ca6091SAmbresh K #define DRA7XX_REVISION_CM_CORE_OFFSET 0x0000 7340ca6091SAmbresh K #define DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL_OFFSET 0x0040 7440ca6091SAmbresh K #define DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_OCP_SOCKET_INST, 0x0040) 7540ca6091SAmbresh K #define DRA7XX_CM_CORE_DEBUG_CFG_OFFSET 0x00f0 7640ca6091SAmbresh K 7740ca6091SAmbresh K /* CM_CORE.CKGEN_CM_CORE register offsets */ 7840ca6091SAmbresh K #define DRA7XX_CM_CLKSEL_USB_60MHZ_OFFSET 0x0000 7940ca6091SAmbresh K #define DRA7XX_CM_CLKSEL_USB_60MHZ DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0000) 8040ca6091SAmbresh K #define DRA7XX_CM_CLKMODE_DPLL_PER_OFFSET 0x003c 8140ca6091SAmbresh K #define DRA7XX_CM_CLKMODE_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x003c) 8240ca6091SAmbresh K #define DRA7XX_CM_IDLEST_DPLL_PER_OFFSET 0x0040 8340ca6091SAmbresh K #define DRA7XX_CM_IDLEST_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0040) 8440ca6091SAmbresh K #define DRA7XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0044 8540ca6091SAmbresh K #define DRA7XX_CM_AUTOIDLE_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0044) 8640ca6091SAmbresh K #define DRA7XX_CM_CLKSEL_DPLL_PER_OFFSET 0x0048 8740ca6091SAmbresh K #define DRA7XX_CM_CLKSEL_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0048) 8840ca6091SAmbresh K #define DRA7XX_CM_DIV_M2_DPLL_PER_OFFSET 0x004c 8940ca6091SAmbresh K #define DRA7XX_CM_DIV_M2_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x004c) 9040ca6091SAmbresh K #define DRA7XX_CM_DIV_M3_DPLL_PER_OFFSET 0x0050 9140ca6091SAmbresh K #define DRA7XX_CM_DIV_M3_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0050) 9240ca6091SAmbresh K #define DRA7XX_CM_DIV_H11_DPLL_PER_OFFSET 0x0054 9340ca6091SAmbresh K #define DRA7XX_CM_DIV_H11_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0054) 9440ca6091SAmbresh K #define DRA7XX_CM_DIV_H12_DPLL_PER_OFFSET 0x0058 9540ca6091SAmbresh K #define DRA7XX_CM_DIV_H12_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0058) 9640ca6091SAmbresh K #define DRA7XX_CM_DIV_H13_DPLL_PER_OFFSET 0x005c 9740ca6091SAmbresh K #define DRA7XX_CM_DIV_H13_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x005c) 9840ca6091SAmbresh K #define DRA7XX_CM_DIV_H14_DPLL_PER_OFFSET 0x0060 9940ca6091SAmbresh K #define DRA7XX_CM_DIV_H14_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0060) 10040ca6091SAmbresh K #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0064 10140ca6091SAmbresh K #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x0068 10240ca6091SAmbresh K #define DRA7XX_CM_CLKMODE_DPLL_USB_OFFSET 0x007c 10340ca6091SAmbresh K #define DRA7XX_CM_CLKMODE_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x007c) 10440ca6091SAmbresh K #define DRA7XX_CM_IDLEST_DPLL_USB_OFFSET 0x0080 10540ca6091SAmbresh K #define DRA7XX_CM_IDLEST_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0080) 10640ca6091SAmbresh K #define DRA7XX_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0084 10740ca6091SAmbresh K #define DRA7XX_CM_AUTOIDLE_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0084) 10840ca6091SAmbresh K #define DRA7XX_CM_CLKSEL_DPLL_USB_OFFSET 0x0088 10940ca6091SAmbresh K #define DRA7XX_CM_CLKSEL_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0088) 11040ca6091SAmbresh K #define DRA7XX_CM_DIV_M2_DPLL_USB_OFFSET 0x008c 11140ca6091SAmbresh K #define DRA7XX_CM_DIV_M2_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x008c) 11240ca6091SAmbresh K #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a4 11340ca6091SAmbresh K #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00a8 11440ca6091SAmbresh K #define DRA7XX_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b0 11540ca6091SAmbresh K #define DRA7XX_CM_CLKDCOLDO_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00b0) 11640ca6091SAmbresh K #define DRA7XX_CM_CLKMODE_DPLL_PCIE_REF_OFFSET 0x00fc 11740ca6091SAmbresh K #define DRA7XX_CM_CLKMODE_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00fc) 11840ca6091SAmbresh K #define DRA7XX_CM_IDLEST_DPLL_PCIE_REF_OFFSET 0x0100 11940ca6091SAmbresh K #define DRA7XX_CM_IDLEST_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0100) 12040ca6091SAmbresh K #define DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF_OFFSET 0x0104 12140ca6091SAmbresh K #define DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0104) 12240ca6091SAmbresh K #define DRA7XX_CM_CLKSEL_DPLL_PCIE_REF_OFFSET 0x0108 12340ca6091SAmbresh K #define DRA7XX_CM_CLKSEL_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0108) 12440ca6091SAmbresh K #define DRA7XX_CM_DIV_M2_DPLL_PCIE_REF_OFFSET 0x010c 12540ca6091SAmbresh K #define DRA7XX_CM_DIV_M2_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x010c) 12640ca6091SAmbresh K #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_PCIE_REF_OFFSET 0x0110 12740ca6091SAmbresh K #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_PCIE_REF_OFFSET 0x0114 12840ca6091SAmbresh K #define DRA7XX_CM_CLKMODE_APLL_PCIE_OFFSET 0x0118 12940ca6091SAmbresh K #define DRA7XX_CM_CLKMODE_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0118) 13040ca6091SAmbresh K #define DRA7XX_CM_IDLEST_APLL_PCIE_OFFSET 0x011c 13140ca6091SAmbresh K #define DRA7XX_CM_IDLEST_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x011c) 13240ca6091SAmbresh K #define DRA7XX_CM_DIV_M2_APLL_PCIE_OFFSET 0x0120 13340ca6091SAmbresh K #define DRA7XX_CM_DIV_M2_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0120) 13440ca6091SAmbresh K #define DRA7XX_CM_CLKVCOLDO_APLL_PCIE_OFFSET 0x0124 13540ca6091SAmbresh K #define DRA7XX_CM_CLKVCOLDO_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0124) 13640ca6091SAmbresh K 13740ca6091SAmbresh K /* CM_CORE.COREAON_CM_CORE register offsets */ 13840ca6091SAmbresh K #define DRA7XX_CM_COREAON_CLKSTCTRL_OFFSET 0x0000 13940ca6091SAmbresh K #define DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET 0x0028 14040ca6091SAmbresh K #define DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0028) 14140ca6091SAmbresh K #define DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET 0x0038 14240ca6091SAmbresh K #define DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0038) 14340ca6091SAmbresh K #define DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL_OFFSET 0x0040 14440ca6091SAmbresh K #define DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0040) 14540ca6091SAmbresh K #define DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0050 14640ca6091SAmbresh K #define DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0050) 14740ca6091SAmbresh K #define DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL_OFFSET 0x0058 14840ca6091SAmbresh K #define DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0058) 14940ca6091SAmbresh K #define DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL_OFFSET 0x0068 15040ca6091SAmbresh K #define DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0068) 15140ca6091SAmbresh K #define DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL_OFFSET 0x0078 15240ca6091SAmbresh K #define DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0078) 15340ca6091SAmbresh K #define DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL_OFFSET 0x0088 15440ca6091SAmbresh K #define DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0088) 15540ca6091SAmbresh K #define DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL_OFFSET 0x0098 15640ca6091SAmbresh K #define DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0098) 15740ca6091SAmbresh K #define DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL_OFFSET 0x00a0 15840ca6091SAmbresh K #define DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00a0) 15940ca6091SAmbresh K #define DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL_OFFSET 0x00b0 16040ca6091SAmbresh K #define DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00b0) 16140ca6091SAmbresh K #define DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL_OFFSET 0x00c0 16240ca6091SAmbresh K #define DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00c0) 16340ca6091SAmbresh K #define DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL_OFFSET 0x00d0 16440ca6091SAmbresh K #define DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00d0) 16540ca6091SAmbresh K 16640ca6091SAmbresh K /* CM_CORE.CORE_CM_CORE register offsets */ 16740ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_CLKSTCTRL_OFFSET 0x0000 16840ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_DYNAMICDEP_OFFSET 0x0008 16940ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET 0x0020 17040ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0020) 17140ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET 0x0028 17240ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0028) 17340ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL_OFFSET 0x0030 17440ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0030) 17540ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL_OFFSET 0x0050 17640ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0050) 17740ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL_OFFSET 0x0058 17840ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0058) 17940ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL_OFFSET 0x0060 18040ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0060) 18140ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL_OFFSET 0x0068 18240ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0068) 18340ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET 0x0070 18440ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0070) 18540ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET 0x0078 18640ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0078) 18740ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET 0x0080 18840ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0080) 18940ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET 0x0088 19040ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0088) 19140ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET 0x0090 19240ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0090) 19340ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL_OFFSET 0x0098 19440ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0098) 19540ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL_OFFSET 0x00a0 19640ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a0) 19740ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL_OFFSET 0x00a8 19840ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a8) 19940ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL_OFFSET 0x00b0 20040ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b0) 20140ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL_OFFSET 0x00b8 20240ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b8) 20340ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL_OFFSET 0x00c0 20440ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c0) 20540ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL_OFFSET 0x00c8 20640ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c8) 20740ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL_OFFSET 0x00d0 20840ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d0) 20940ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL_OFFSET 0x00d8 21040ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d8) 21140ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL_OFFSET 0x00f0 21240ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f0) 21340ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL_OFFSET 0x00f8 21440ca6091SAmbresh K #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f8) 21540ca6091SAmbresh K #define DRA7XX_CM_IPU2_CLKSTCTRL_OFFSET 0x0200 21640ca6091SAmbresh K #define DRA7XX_CM_IPU2_STATICDEP_OFFSET 0x0204 21740ca6091SAmbresh K #define DRA7XX_CM_IPU2_DYNAMICDEP_OFFSET 0x0208 21840ca6091SAmbresh K #define DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET 0x0220 21940ca6091SAmbresh K #define DRA7XX_CM_IPU2_IPU2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0220) 22040ca6091SAmbresh K #define DRA7XX_CM_DMA_CLKSTCTRL_OFFSET 0x0300 22140ca6091SAmbresh K #define DRA7XX_CM_DMA_STATICDEP_OFFSET 0x0304 22240ca6091SAmbresh K #define DRA7XX_CM_DMA_DYNAMICDEP_OFFSET 0x0308 22340ca6091SAmbresh K #define DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET 0x0320 22440ca6091SAmbresh K #define DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0320) 22540ca6091SAmbresh K #define DRA7XX_CM_EMIF_CLKSTCTRL_OFFSET 0x0400 22640ca6091SAmbresh K #define DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET 0x0420 22740ca6091SAmbresh K #define DRA7XX_CM_EMIF_DMM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0420) 22840ca6091SAmbresh K #define DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET 0x0428 22940ca6091SAmbresh K #define DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0428) 23040ca6091SAmbresh K #define DRA7XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET 0x0430 23140ca6091SAmbresh K #define DRA7XX_CM_EMIF_EMIF1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0430) 23240ca6091SAmbresh K #define DRA7XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET 0x0438 23340ca6091SAmbresh K #define DRA7XX_CM_EMIF_EMIF2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0438) 23440ca6091SAmbresh K #define DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL_OFFSET 0x0440 23540ca6091SAmbresh K #define DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0440) 23640ca6091SAmbresh K #define DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET 0x0500 23740ca6091SAmbresh K #define DRA7XX_CM_ATL_ATL_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0500) 23840ca6091SAmbresh K #define DRA7XX_CM_ATL_CLKSTCTRL_OFFSET 0x0520 23940ca6091SAmbresh K #define DRA7XX_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600 24040ca6091SAmbresh K #define DRA7XX_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608 24140ca6091SAmbresh K #define DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620 24240ca6091SAmbresh K #define DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0620) 24340ca6091SAmbresh K #define DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET 0x0628 24440ca6091SAmbresh K #define DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0628) 24540ca6091SAmbresh K #define DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET 0x0630 24640ca6091SAmbresh K #define DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0630) 24740ca6091SAmbresh K #define DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638 24840ca6091SAmbresh K #define DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0638) 24940ca6091SAmbresh K #define DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL_OFFSET 0x0640 25040ca6091SAmbresh K #define DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0640) 25140ca6091SAmbresh K #define DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET 0x0648 25240ca6091SAmbresh K #define DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0648) 25340ca6091SAmbresh K #define DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET 0x0650 25440ca6091SAmbresh K #define DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0650) 25540ca6091SAmbresh K #define DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET 0x0658 25640ca6091SAmbresh K #define DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0658) 25740ca6091SAmbresh K #define DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET 0x0660 25840ca6091SAmbresh K #define DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0660) 25940ca6091SAmbresh K #define DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET 0x0668 26040ca6091SAmbresh K #define DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0668) 26140ca6091SAmbresh K #define DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET 0x0670 26240ca6091SAmbresh K #define DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0670) 26340ca6091SAmbresh K #define DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET 0x0678 26440ca6091SAmbresh K #define DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0678) 26540ca6091SAmbresh K #define DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET 0x0680 26640ca6091SAmbresh K #define DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0680) 26740ca6091SAmbresh K #define DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET 0x0688 26840ca6091SAmbresh K #define DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0688) 26940ca6091SAmbresh K #define DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET 0x0690 27040ca6091SAmbresh K #define DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0690) 27140ca6091SAmbresh K #define DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET 0x0698 27240ca6091SAmbresh K #define DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0698) 27340ca6091SAmbresh K #define DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET 0x06a0 27440ca6091SAmbresh K #define DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a0) 27540ca6091SAmbresh K #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL_OFFSET 0x06a8 27640ca6091SAmbresh K #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a8) 27740ca6091SAmbresh K #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL_OFFSET 0x06b0 27840ca6091SAmbresh K #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b0) 27940ca6091SAmbresh K #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL_OFFSET 0x06b8 28040ca6091SAmbresh K #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b8) 28140ca6091SAmbresh K #define DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL_OFFSET 0x06c0 28240ca6091SAmbresh K #define DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06c0) 28340ca6091SAmbresh K #define DRA7XX_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700 28440ca6091SAmbresh K #define DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET 0x0720 28540ca6091SAmbresh K #define DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0720) 28640ca6091SAmbresh K #define DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728 28740ca6091SAmbresh K #define DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0728) 28840ca6091SAmbresh K #define DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET 0x0740 28940ca6091SAmbresh K #define DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0740) 29040ca6091SAmbresh K #define DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL_OFFSET 0x0748 29140ca6091SAmbresh K #define DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0748) 29240ca6091SAmbresh K #define DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL_OFFSET 0x0750 29340ca6091SAmbresh K #define DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0750) 29440ca6091SAmbresh K 29540ca6091SAmbresh K /* CM_CORE.IVA_CM_CORE register offsets */ 29640ca6091SAmbresh K #define DRA7XX_CM_IVA_CLKSTCTRL_OFFSET 0x0000 29740ca6091SAmbresh K #define DRA7XX_CM_IVA_STATICDEP_OFFSET 0x0004 29840ca6091SAmbresh K #define DRA7XX_CM_IVA_DYNAMICDEP_OFFSET 0x0008 29940ca6091SAmbresh K #define DRA7XX_CM_IVA_IVA_CLKCTRL_OFFSET 0x0020 30040ca6091SAmbresh K #define DRA7XX_CM_IVA_IVA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_IVA_INST, 0x0020) 30140ca6091SAmbresh K #define DRA7XX_CM_IVA_SL2_CLKCTRL_OFFSET 0x0028 30240ca6091SAmbresh K #define DRA7XX_CM_IVA_SL2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_IVA_INST, 0x0028) 30340ca6091SAmbresh K 30440ca6091SAmbresh K /* CM_CORE.CAM_CM_CORE register offsets */ 30540ca6091SAmbresh K #define DRA7XX_CM_CAM_CLKSTCTRL_OFFSET 0x0000 30640ca6091SAmbresh K #define DRA7XX_CM_CAM_STATICDEP_OFFSET 0x0004 30740ca6091SAmbresh K #define DRA7XX_CM_CAM_VIP1_CLKCTRL_OFFSET 0x0020 30840ca6091SAmbresh K #define DRA7XX_CM_CAM_VIP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0020) 30940ca6091SAmbresh K #define DRA7XX_CM_CAM_VIP2_CLKCTRL_OFFSET 0x0028 31040ca6091SAmbresh K #define DRA7XX_CM_CAM_VIP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0028) 31140ca6091SAmbresh K #define DRA7XX_CM_CAM_VIP3_CLKCTRL_OFFSET 0x0030 31240ca6091SAmbresh K #define DRA7XX_CM_CAM_VIP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0030) 31340ca6091SAmbresh K #define DRA7XX_CM_CAM_LVDSRX_CLKCTRL_OFFSET 0x0038 31440ca6091SAmbresh K #define DRA7XX_CM_CAM_LVDSRX_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0038) 31540ca6091SAmbresh K #define DRA7XX_CM_CAM_CSI1_CLKCTRL_OFFSET 0x0040 31640ca6091SAmbresh K #define DRA7XX_CM_CAM_CSI1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0040) 31740ca6091SAmbresh K #define DRA7XX_CM_CAM_CSI2_CLKCTRL_OFFSET 0x0048 31840ca6091SAmbresh K #define DRA7XX_CM_CAM_CSI2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0048) 31940ca6091SAmbresh K 32040ca6091SAmbresh K /* CM_CORE.DSS_CM_CORE register offsets */ 32140ca6091SAmbresh K #define DRA7XX_CM_DSS_CLKSTCTRL_OFFSET 0x0000 32240ca6091SAmbresh K #define DRA7XX_CM_DSS_STATICDEP_OFFSET 0x0004 32340ca6091SAmbresh K #define DRA7XX_CM_DSS_DYNAMICDEP_OFFSET 0x0008 32440ca6091SAmbresh K #define DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020 32540ca6091SAmbresh K #define DRA7XX_CM_DSS_DSS_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x0020) 32640ca6091SAmbresh K #define DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET 0x0030 32740ca6091SAmbresh K #define DRA7XX_CM_DSS_BB2D_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x0030) 32840ca6091SAmbresh K #define DRA7XX_CM_DSS_SDVENC_CLKCTRL_OFFSET 0x003c 32940ca6091SAmbresh K #define DRA7XX_CM_DSS_SDVENC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x003c) 33040ca6091SAmbresh K 33140ca6091SAmbresh K /* CM_CORE.GPU_CM_CORE register offsets */ 33240ca6091SAmbresh K #define DRA7XX_CM_GPU_CLKSTCTRL_OFFSET 0x0000 33340ca6091SAmbresh K #define DRA7XX_CM_GPU_STATICDEP_OFFSET 0x0004 33440ca6091SAmbresh K #define DRA7XX_CM_GPU_DYNAMICDEP_OFFSET 0x0008 33540ca6091SAmbresh K #define DRA7XX_CM_GPU_GPU_CLKCTRL_OFFSET 0x0020 33640ca6091SAmbresh K #define DRA7XX_CM_GPU_GPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_GPU_INST, 0x0020) 33740ca6091SAmbresh K 33840ca6091SAmbresh K /* CM_CORE.L3INIT_CM_CORE register offsets */ 33940ca6091SAmbresh K #define DRA7XX_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000 34040ca6091SAmbresh K #define DRA7XX_CM_L3INIT_STATICDEP_OFFSET 0x0004 34140ca6091SAmbresh K #define DRA7XX_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008 34240ca6091SAmbresh K #define DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028 34340ca6091SAmbresh K #define DRA7XX_CM_L3INIT_MMC1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0028) 34440ca6091SAmbresh K #define DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030 34540ca6091SAmbresh K #define DRA7XX_CM_L3INIT_MMC2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0030) 34640ca6091SAmbresh K #define DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET 0x0040 34740ca6091SAmbresh K #define DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0040) 34840ca6091SAmbresh K #define DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET 0x0048 34940ca6091SAmbresh K #define DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0048) 35040ca6091SAmbresh K #define DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET 0x0050 35140ca6091SAmbresh K #define DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0050) 35240ca6091SAmbresh K #define DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL_OFFSET 0x0058 35340ca6091SAmbresh K #define DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0058) 35440ca6091SAmbresh K #define DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL_OFFSET 0x0078 35540ca6091SAmbresh K #define DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0078) 35640ca6091SAmbresh K #define DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088 35740ca6091SAmbresh K #define DRA7XX_CM_L3INIT_SATA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088) 35840ca6091SAmbresh K #define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET 0x00a0 35940ca6091SAmbresh K #define DRA7XX_CM_PCIE_STATICDEP_OFFSET 0x00a4 36040ca6091SAmbresh K #define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET 0x00c0 36140ca6091SAmbresh K #define DRA7XX_CM_GMAC_STATICDEP_OFFSET 0x00c4 36240ca6091SAmbresh K #define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET 0x00c8 36340ca6091SAmbresh K #define DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET 0x00d0 36440ca6091SAmbresh K #define DRA7XX_CM_GMAC_GMAC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00d0) 36540ca6091SAmbresh K #define DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET 0x00e0 36640ca6091SAmbresh K #define DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e0) 36740ca6091SAmbresh K #define DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET 0x00e8 36840ca6091SAmbresh K #define DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e8) 36940ca6091SAmbresh K #define DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET 0x00f0 37040ca6091SAmbresh K #define DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00f0) 37140ca6091SAmbresh K 37240ca6091SAmbresh K /* CM_CORE.CUSTEFUSE_CM_CORE register offsets */ 37340ca6091SAmbresh K #define DRA7XX_CM_CUSTEFUSE_CLKSTCTRL_OFFSET 0x0000 37440ca6091SAmbresh K #define DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL_OFFSET 0x0020 37540ca6091SAmbresh K #define DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CUSTEFUSE_INST, 0x0020) 37640ca6091SAmbresh K 37740ca6091SAmbresh K /* CM_CORE.L4PER_CM_CORE register offsets */ 37840ca6091SAmbresh K #define DRA7XX_CM_L4PER_CLKSTCTRL_OFFSET 0x0000 37940ca6091SAmbresh K #define DRA7XX_CM_L4PER_DYNAMICDEP_OFFSET 0x0008 38040ca6091SAmbresh K #define DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET 0x000c 38140ca6091SAmbresh K #define DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x000c) 38240ca6091SAmbresh K #define DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET 0x0014 38340ca6091SAmbresh K #define DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0014) 38440ca6091SAmbresh K #define DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL_OFFSET 0x0018 38540ca6091SAmbresh K #define DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0018) 38640ca6091SAmbresh K #define DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL_OFFSET 0x0020 38740ca6091SAmbresh K #define DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0020) 38840ca6091SAmbresh K #define DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET 0x0028 38940ca6091SAmbresh K #define DRA7XX_CM_L4PER_TIMER10_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0028) 39040ca6091SAmbresh K #define DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET 0x0030 39140ca6091SAmbresh K #define DRA7XX_CM_L4PER_TIMER11_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0030) 39240ca6091SAmbresh K #define DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET 0x0038 39340ca6091SAmbresh K #define DRA7XX_CM_L4PER_TIMER2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0038) 39440ca6091SAmbresh K #define DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET 0x0040 39540ca6091SAmbresh K #define DRA7XX_CM_L4PER_TIMER3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0040) 39640ca6091SAmbresh K #define DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET 0x0048 39740ca6091SAmbresh K #define DRA7XX_CM_L4PER_TIMER4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0048) 39840ca6091SAmbresh K #define DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET 0x0050 39940ca6091SAmbresh K #define DRA7XX_CM_L4PER_TIMER9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0050) 40040ca6091SAmbresh K #define DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058 40140ca6091SAmbresh K #define DRA7XX_CM_L4PER_ELM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0058) 40240ca6091SAmbresh K #define DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060 40340ca6091SAmbresh K #define DRA7XX_CM_L4PER_GPIO2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0060) 40440ca6091SAmbresh K #define DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068 40540ca6091SAmbresh K #define DRA7XX_CM_L4PER_GPIO3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0068) 40640ca6091SAmbresh K #define DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070 40740ca6091SAmbresh K #define DRA7XX_CM_L4PER_GPIO4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0070) 40840ca6091SAmbresh K #define DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078 40940ca6091SAmbresh K #define DRA7XX_CM_L4PER_GPIO5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0078) 41040ca6091SAmbresh K #define DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080 41140ca6091SAmbresh K #define DRA7XX_CM_L4PER_GPIO6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0080) 41240ca6091SAmbresh K #define DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088 41340ca6091SAmbresh K #define DRA7XX_CM_L4PER_HDQ1W_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0088) 41440ca6091SAmbresh K #define DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET 0x0090 41540ca6091SAmbresh K #define DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0090) 41640ca6091SAmbresh K #define DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET 0x0098 41740ca6091SAmbresh K #define DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0098) 41840ca6091SAmbresh K #define DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0 41940ca6091SAmbresh K #define DRA7XX_CM_L4PER_I2C1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a0) 42040ca6091SAmbresh K #define DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8 42140ca6091SAmbresh K #define DRA7XX_CM_L4PER_I2C2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a8) 42240ca6091SAmbresh K #define DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0 42340ca6091SAmbresh K #define DRA7XX_CM_L4PER_I2C3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b0) 42440ca6091SAmbresh K #define DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8 42540ca6091SAmbresh K #define DRA7XX_CM_L4PER_I2C4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b8) 42640ca6091SAmbresh K #define DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET 0x00c0 42740ca6091SAmbresh K #define DRA7XX_CM_L4PER_L4_PER1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c0) 42840ca6091SAmbresh K #define DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET 0x00c4 42940ca6091SAmbresh K #define DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c4) 43040ca6091SAmbresh K #define DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET 0x00c8 43140ca6091SAmbresh K #define DRA7XX_CM_L4PER3_TIMER13_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c8) 43240ca6091SAmbresh K #define DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET 0x00d0 43340ca6091SAmbresh K #define DRA7XX_CM_L4PER3_TIMER14_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d0) 43440ca6091SAmbresh K #define DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET 0x00d8 43540ca6091SAmbresh K #define DRA7XX_CM_L4PER3_TIMER15_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d8) 43640ca6091SAmbresh K #define DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0 43740ca6091SAmbresh K #define DRA7XX_CM_L4PER_MCSPI1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f0) 43840ca6091SAmbresh K #define DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8 43940ca6091SAmbresh K #define DRA7XX_CM_L4PER_MCSPI2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f8) 44040ca6091SAmbresh K #define DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100 44140ca6091SAmbresh K #define DRA7XX_CM_L4PER_MCSPI3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0100) 44240ca6091SAmbresh K #define DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108 44340ca6091SAmbresh K #define DRA7XX_CM_L4PER_MCSPI4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0108) 44440ca6091SAmbresh K #define DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET 0x0110 44540ca6091SAmbresh K #define DRA7XX_CM_L4PER_GPIO7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0110) 44640ca6091SAmbresh K #define DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET 0x0118 44740ca6091SAmbresh K #define DRA7XX_CM_L4PER_GPIO8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0118) 44840ca6091SAmbresh K #define DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET 0x0120 44940ca6091SAmbresh K #define DRA7XX_CM_L4PER_MMC3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0120) 45040ca6091SAmbresh K #define DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET 0x0128 45140ca6091SAmbresh K #define DRA7XX_CM_L4PER_MMC4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0128) 45240ca6091SAmbresh K #define DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET 0x0130 45340ca6091SAmbresh K #define DRA7XX_CM_L4PER3_TIMER16_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0130) 45440ca6091SAmbresh K #define DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET 0x0138 45540ca6091SAmbresh K #define DRA7XX_CM_L4PER2_QSPI_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0138) 45640ca6091SAmbresh K #define DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140 45740ca6091SAmbresh K #define DRA7XX_CM_L4PER_UART1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0140) 45840ca6091SAmbresh K #define DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148 45940ca6091SAmbresh K #define DRA7XX_CM_L4PER_UART2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0148) 46040ca6091SAmbresh K #define DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150 46140ca6091SAmbresh K #define DRA7XX_CM_L4PER_UART3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0150) 46240ca6091SAmbresh K #define DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158 46340ca6091SAmbresh K #define DRA7XX_CM_L4PER_UART4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0158) 46440ca6091SAmbresh K #define DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET 0x0160 46540ca6091SAmbresh K #define DRA7XX_CM_L4PER2_MCASP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0160) 46640ca6091SAmbresh K #define DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET 0x0168 46740ca6091SAmbresh K #define DRA7XX_CM_L4PER2_MCASP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0168) 46840ca6091SAmbresh K #define DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET 0x0170 46940ca6091SAmbresh K #define DRA7XX_CM_L4PER_UART5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0170) 47040ca6091SAmbresh K #define DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET 0x0178 47140ca6091SAmbresh K #define DRA7XX_CM_L4PER2_MCASP5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0178) 47240ca6091SAmbresh K #define DRA7XX_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180 47340ca6091SAmbresh K #define DRA7XX_CM_L4SEC_STATICDEP_OFFSET 0x0184 47440ca6091SAmbresh K #define DRA7XX_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188 47540ca6091SAmbresh K #define DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET 0x0190 47640ca6091SAmbresh K #define DRA7XX_CM_L4PER2_MCASP8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0190) 47740ca6091SAmbresh K #define DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET 0x0198 47840ca6091SAmbresh K #define DRA7XX_CM_L4PER2_MCASP4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0198) 47940ca6091SAmbresh K #define DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0 48040ca6091SAmbresh K #define DRA7XX_CM_L4SEC_AES1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a0) 48140ca6091SAmbresh K #define DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8 48240ca6091SAmbresh K #define DRA7XX_CM_L4SEC_AES2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a8) 48340ca6091SAmbresh K #define DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0 48440ca6091SAmbresh K #define DRA7XX_CM_L4SEC_DES3DES_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b0) 48540ca6091SAmbresh K #define DRA7XX_CM_L4SEC_FPKA_CLKCTRL_OFFSET 0x01b8 48640ca6091SAmbresh K #define DRA7XX_CM_L4SEC_FPKA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b8) 48740ca6091SAmbresh K #define DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0 48840ca6091SAmbresh K #define DRA7XX_CM_L4SEC_RNG_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c0) 48940ca6091SAmbresh K #define DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8 49040ca6091SAmbresh K #define DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c8) 49140ca6091SAmbresh K #define DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET 0x01d0 49240ca6091SAmbresh K #define DRA7XX_CM_L4PER2_UART7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d0) 49340ca6091SAmbresh K #define DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL_OFFSET 0x01d8 49440ca6091SAmbresh K #define DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d8) 49540ca6091SAmbresh K #define DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET 0x01e0 49640ca6091SAmbresh K #define DRA7XX_CM_L4PER2_UART8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e0) 49740ca6091SAmbresh K #define DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET 0x01e8 49840ca6091SAmbresh K #define DRA7XX_CM_L4PER2_UART9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e8) 49940ca6091SAmbresh K #define DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET 0x01f0 50040ca6091SAmbresh K #define DRA7XX_CM_L4PER2_DCAN2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f0) 50140ca6091SAmbresh K #define DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL_OFFSET 0x01f8 50240ca6091SAmbresh K #define DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f8) 50340ca6091SAmbresh K #define DRA7XX_CM_L4PER2_CLKSTCTRL_OFFSET 0x01fc 50440ca6091SAmbresh K #define DRA7XX_CM_L4PER2_DYNAMICDEP_OFFSET 0x0200 50540ca6091SAmbresh K #define DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET 0x0204 50640ca6091SAmbresh K #define DRA7XX_CM_L4PER2_MCASP6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0204) 50740ca6091SAmbresh K #define DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET 0x0208 50840ca6091SAmbresh K #define DRA7XX_CM_L4PER2_MCASP7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0208) 50940ca6091SAmbresh K #define DRA7XX_CM_L4PER2_STATICDEP_OFFSET 0x020c 51040ca6091SAmbresh K #define DRA7XX_CM_L4PER3_CLKSTCTRL_OFFSET 0x0210 51140ca6091SAmbresh K #define DRA7XX_CM_L4PER3_DYNAMICDEP_OFFSET 0x0214 51240ca6091SAmbresh K 51340ca6091SAmbresh K #endif 514