1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * OMAP54xx CM2 instance offset macros 4 * 5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Paul Walmsley (paul@pwsan.com) 8 * Rajendra Nayak (rnayak@ti.com) 9 * Benoit Cousson (b-cousson@ti.com) 10 * 11 * This file is automatically generated from the OMAP hardware databases. 12 * We respectfully ask that any modifications to this file be coordinated 13 * with the public linux-omap@vger.kernel.org mailing list and the 14 * authors above to ensure that the autogeneration scripts are kept 15 * up-to-date with the file contents. 16 */ 17 18 #ifndef __ARCH_ARM_MACH_OMAP2_CM2_54XX_H 19 #define __ARCH_ARM_MACH_OMAP2_CM2_54XX_H 20 21 /* CM2 base address */ 22 #define OMAP54XX_CM_CORE_BASE 0x4a008000 23 24 #define OMAP54XX_CM_CORE_REGADDR(inst, reg) \ 25 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE + (inst) + (reg)) 26 27 /* CM_CORE instances */ 28 #define OMAP54XX_CM_CORE_OCP_SOCKET_INST 0x0000 29 #define OMAP54XX_CM_CORE_CKGEN_INST 0x0100 30 #define OMAP54XX_CM_CORE_COREAON_INST 0x0600 31 #define OMAP54XX_CM_CORE_CORE_INST 0x0700 32 #define OMAP54XX_CM_CORE_IVA_INST 0x1200 33 #define OMAP54XX_CM_CORE_CAM_INST 0x1300 34 #define OMAP54XX_CM_CORE_DSS_INST 0x1400 35 #define OMAP54XX_CM_CORE_GPU_INST 0x1500 36 #define OMAP54XX_CM_CORE_L3INIT_INST 0x1600 37 #define OMAP54XX_CM_CORE_CUSTEFUSE_INST 0x1700 38 39 /* CM_CORE clockdomain register offsets (from instance start) */ 40 #define OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS 0x0000 41 #define OMAP54XX_CM_CORE_CORE_L3MAIN1_CDOFFS 0x0000 42 #define OMAP54XX_CM_CORE_CORE_L3MAIN2_CDOFFS 0x0100 43 #define OMAP54XX_CM_CORE_CORE_IPU_CDOFFS 0x0200 44 #define OMAP54XX_CM_CORE_CORE_DMA_CDOFFS 0x0300 45 #define OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS 0x0400 46 #define OMAP54XX_CM_CORE_CORE_C2C_CDOFFS 0x0500 47 #define OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS 0x0600 48 #define OMAP54XX_CM_CORE_CORE_L3INSTR_CDOFFS 0x0700 49 #define OMAP54XX_CM_CORE_CORE_MIPIEXT_CDOFFS 0x0800 50 #define OMAP54XX_CM_CORE_CORE_L4PER_CDOFFS 0x0900 51 #define OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS 0x0a80 52 #define OMAP54XX_CM_CORE_IVA_IVA_CDOFFS 0x0000 53 #define OMAP54XX_CM_CORE_CAM_CAM_CDOFFS 0x0000 54 #define OMAP54XX_CM_CORE_DSS_DSS_CDOFFS 0x0000 55 #define OMAP54XX_CM_CORE_GPU_GPU_CDOFFS 0x0000 56 #define OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS 0x0000 57 #define OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS 0x0000 58 59 #endif 60