1 /* 2 * OMAP54xx CM2 instance offset macros 3 * 4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Paul Walmsley (paul@pwsan.com) 7 * Rajendra Nayak (rnayak@ti.com) 8 * Benoit Cousson (b-cousson@ti.com) 9 * 10 * This file is automatically generated from the OMAP hardware databases. 11 * We respectfully ask that any modifications to this file be coordinated 12 * with the public linux-omap@vger.kernel.org mailing list and the 13 * authors above to ensure that the autogeneration scripts are kept 14 * up-to-date with the file contents. 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License version 2 as 18 * published by the Free Software Foundation. 19 */ 20 21 #ifndef __ARCH_ARM_MACH_OMAP2_CM2_54XX_H 22 #define __ARCH_ARM_MACH_OMAP2_CM2_54XX_H 23 24 #include "cm_44xx_54xx.h" 25 26 /* CM2 base address */ 27 #define OMAP54XX_CM_CORE_BASE 0x4a008000 28 29 #define OMAP54XX_CM_CORE_REGADDR(inst, reg) \ 30 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE + (inst) + (reg)) 31 32 /* CM_CORE instances */ 33 #define OMAP54XX_CM_CORE_OCP_SOCKET_INST 0x0000 34 #define OMAP54XX_CM_CORE_CKGEN_INST 0x0100 35 #define OMAP54XX_CM_CORE_COREAON_INST 0x0600 36 #define OMAP54XX_CM_CORE_CORE_INST 0x0700 37 #define OMAP54XX_CM_CORE_IVA_INST 0x1200 38 #define OMAP54XX_CM_CORE_CAM_INST 0x1300 39 #define OMAP54XX_CM_CORE_DSS_INST 0x1400 40 #define OMAP54XX_CM_CORE_GPU_INST 0x1500 41 #define OMAP54XX_CM_CORE_L3INIT_INST 0x1600 42 #define OMAP54XX_CM_CORE_CUSTEFUSE_INST 0x1700 43 #define OMAP54XX_CM_CORE_RESTORE_INST 0x1e00 44 #define OMAP54XX_CM_CORE_INSTR_INST 0x1f00 45 46 /* CM_CORE clockdomain register offsets (from instance start) */ 47 #define OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS 0x0000 48 #define OMAP54XX_CM_CORE_CORE_L3MAIN1_CDOFFS 0x0000 49 #define OMAP54XX_CM_CORE_CORE_L3MAIN2_CDOFFS 0x0100 50 #define OMAP54XX_CM_CORE_CORE_IPU_CDOFFS 0x0200 51 #define OMAP54XX_CM_CORE_CORE_DMA_CDOFFS 0x0300 52 #define OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS 0x0400 53 #define OMAP54XX_CM_CORE_CORE_C2C_CDOFFS 0x0500 54 #define OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS 0x0600 55 #define OMAP54XX_CM_CORE_CORE_L3INSTR_CDOFFS 0x0700 56 #define OMAP54XX_CM_CORE_CORE_MIPIEXT_CDOFFS 0x0800 57 #define OMAP54XX_CM_CORE_CORE_L4PER_CDOFFS 0x0900 58 #define OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS 0x0a80 59 #define OMAP54XX_CM_CORE_IVA_IVA_CDOFFS 0x0000 60 #define OMAP54XX_CM_CORE_CAM_CAM_CDOFFS 0x0000 61 #define OMAP54XX_CM_CORE_DSS_DSS_CDOFFS 0x0000 62 #define OMAP54XX_CM_CORE_GPU_GPU_CDOFFS 0x0000 63 #define OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS 0x0000 64 #define OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS 0x0000 65 66 /* CM_CORE */ 67 68 /* CM_CORE.OCP_SOCKET_CM_CORE register offsets */ 69 #define OMAP54XX_REVISION_CM_CORE_OFFSET 0x0000 70 #define OMAP54XX_CM_CM_CORE_PROFILING_CLKCTRL_OFFSET 0x0040 71 #define OMAP54XX_CM_CM_CORE_PROFILING_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_OCP_SOCKET_INST, 0x0040) 72 #define OMAP54XX_CM_CORE_DEBUG_CFG_OFFSET 0x0080 73 #define OMAP54XX_CM_CORE_DEBUG_OUT_OFFSET 0x0084 74 75 /* CM_CORE.CKGEN_CM_CORE register offsets */ 76 #define OMAP54XX_CM_CLKSEL_USB_60MHZ_OFFSET 0x0004 77 #define OMAP54XX_CM_CLKSEL_USB_60MHZ OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0004) 78 #define OMAP54XX_CM_CLKMODE_DPLL_PER_OFFSET 0x0040 79 #define OMAP54XX_CM_CLKMODE_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0040) 80 #define OMAP54XX_CM_IDLEST_DPLL_PER_OFFSET 0x0044 81 #define OMAP54XX_CM_IDLEST_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0044) 82 #define OMAP54XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0048 83 #define OMAP54XX_CM_AUTOIDLE_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0048) 84 #define OMAP54XX_CM_CLKSEL_DPLL_PER_OFFSET 0x004c 85 #define OMAP54XX_CM_CLKSEL_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x004c) 86 #define OMAP54XX_CM_DIV_M2_DPLL_PER_OFFSET 0x0050 87 #define OMAP54XX_CM_DIV_M2_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0050) 88 #define OMAP54XX_CM_DIV_M3_DPLL_PER_OFFSET 0x0054 89 #define OMAP54XX_CM_DIV_M3_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0054) 90 #define OMAP54XX_CM_DIV_H11_DPLL_PER_OFFSET 0x0058 91 #define OMAP54XX_CM_DIV_H11_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0058) 92 #define OMAP54XX_CM_DIV_H12_DPLL_PER_OFFSET 0x005c 93 #define OMAP54XX_CM_DIV_H12_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x005c) 94 #define OMAP54XX_CM_DIV_H13_DPLL_PER_OFFSET 0x0060 95 #define OMAP54XX_CM_DIV_H13_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0060) 96 #define OMAP54XX_CM_DIV_H14_DPLL_PER_OFFSET 0x0064 97 #define OMAP54XX_CM_DIV_H14_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0064) 98 #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068 99 #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c 100 #define OMAP54XX_CM_CLKMODE_DPLL_USB_OFFSET 0x0080 101 #define OMAP54XX_CM_CLKMODE_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0080) 102 #define OMAP54XX_CM_IDLEST_DPLL_USB_OFFSET 0x0084 103 #define OMAP54XX_CM_IDLEST_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0084) 104 #define OMAP54XX_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0088 105 #define OMAP54XX_CM_AUTOIDLE_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0088) 106 #define OMAP54XX_CM_CLKSEL_DPLL_USB_OFFSET 0x008c 107 #define OMAP54XX_CM_CLKSEL_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x008c) 108 #define OMAP54XX_CM_DIV_M2_DPLL_USB_OFFSET 0x0090 109 #define OMAP54XX_CM_DIV_M2_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0090) 110 #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8 111 #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac 112 #define OMAP54XX_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4 113 #define OMAP54XX_CM_CLKDCOLDO_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00b4) 114 #define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2_OFFSET 0x00c0 115 #define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c0) 116 #define OMAP54XX_CM_IDLEST_DPLL_UNIPRO2_OFFSET 0x00c4 117 #define OMAP54XX_CM_IDLEST_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c4) 118 #define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2_OFFSET 0x00c8 119 #define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c8) 120 #define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2_OFFSET 0x00cc 121 #define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00cc) 122 #define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2_OFFSET 0x00d0 123 #define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00d0) 124 #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_UNIPRO2_OFFSET 0x00e8 125 #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_UNIPRO2_OFFSET 0x00ec 126 #define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2_OFFSET 0x00f4 127 #define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00f4) 128 #define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1_OFFSET 0x0100 129 #define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0100) 130 #define OMAP54XX_CM_IDLEST_DPLL_UNIPRO1_OFFSET 0x0104 131 #define OMAP54XX_CM_IDLEST_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0104) 132 #define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1_OFFSET 0x0108 133 #define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0108) 134 #define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1_OFFSET 0x010c 135 #define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x010c) 136 #define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1_OFFSET 0x0110 137 #define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0110) 138 #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_UNIPRO1_OFFSET 0x0128 139 #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_UNIPRO1_OFFSET 0x012c 140 #define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1_OFFSET 0x0134 141 #define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0134) 142 143 /* CM_CORE.COREAON_CM_CORE register offsets */ 144 #define OMAP54XX_CM_COREAON_CLKSTCTRL_OFFSET 0x0000 145 #define OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET 0x0028 146 #define OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0028) 147 #define OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL_OFFSET 0x0030 148 #define OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0030) 149 #define OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET 0x0038 150 #define OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0038) 151 #define OMAP54XX_CM_COREAON_USB_PHY_CORE_CLKCTRL_OFFSET 0x0040 152 #define OMAP54XX_CM_COREAON_USB_PHY_CORE_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0040) 153 #define OMAP54XX_CM_COREAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0050 154 #define OMAP54XX_CM_COREAON_IO_SRCOMP_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0050) 155 156 /* CM_CORE.CORE_CM_CORE register offsets */ 157 #define OMAP54XX_CM_L3MAIN1_CLKSTCTRL_OFFSET 0x0000 158 #define OMAP54XX_CM_L3MAIN1_DYNAMICDEP_OFFSET 0x0008 159 #define OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET 0x0020 160 #define OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0020) 161 #define OMAP54XX_CM_L3MAIN2_CLKSTCTRL_OFFSET 0x0100 162 #define OMAP54XX_CM_L3MAIN2_DYNAMICDEP_OFFSET 0x0108 163 #define OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET 0x0120 164 #define OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0120) 165 #define OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL_OFFSET 0x0128 166 #define OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0128) 167 #define OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL_OFFSET 0x0130 168 #define OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0130) 169 #define OMAP54XX_CM_IPU_CLKSTCTRL_OFFSET 0x0200 170 #define OMAP54XX_CM_IPU_STATICDEP_OFFSET 0x0204 171 #define OMAP54XX_CM_IPU_DYNAMICDEP_OFFSET 0x0208 172 #define OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET 0x0220 173 #define OMAP54XX_CM_IPU_IPU_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0220) 174 #define OMAP54XX_CM_DMA_CLKSTCTRL_OFFSET 0x0300 175 #define OMAP54XX_CM_DMA_STATICDEP_OFFSET 0x0304 176 #define OMAP54XX_CM_DMA_DYNAMICDEP_OFFSET 0x0308 177 #define OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET 0x0320 178 #define OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0320) 179 #define OMAP54XX_CM_EMIF_CLKSTCTRL_OFFSET 0x0400 180 #define OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET 0x0420 181 #define OMAP54XX_CM_EMIF_DMM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0420) 182 #define OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET 0x0428 183 #define OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0428) 184 #define OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET 0x0430 185 #define OMAP54XX_CM_EMIF_EMIF1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0430) 186 #define OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET 0x0438 187 #define OMAP54XX_CM_EMIF_EMIF2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0438) 188 #define OMAP54XX_CM_EMIF_EMIF_DLL_CLKCTRL_OFFSET 0x0440 189 #define OMAP54XX_CM_EMIF_EMIF_DLL_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0440) 190 #define OMAP54XX_CM_C2C_CLKSTCTRL_OFFSET 0x0500 191 #define OMAP54XX_CM_C2C_STATICDEP_OFFSET 0x0504 192 #define OMAP54XX_CM_C2C_DYNAMICDEP_OFFSET 0x0508 193 #define OMAP54XX_CM_C2C_C2C_CLKCTRL_OFFSET 0x0520 194 #define OMAP54XX_CM_C2C_C2C_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0520) 195 #define OMAP54XX_CM_C2C_MODEM_ICR_CLKCTRL_OFFSET 0x0528 196 #define OMAP54XX_CM_C2C_MODEM_ICR_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0528) 197 #define OMAP54XX_CM_C2C_C2C_OCP_FW_CLKCTRL_OFFSET 0x0530 198 #define OMAP54XX_CM_C2C_C2C_OCP_FW_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0530) 199 #define OMAP54XX_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600 200 #define OMAP54XX_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608 201 #define OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620 202 #define OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0620) 203 #define OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET 0x0628 204 #define OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0628) 205 #define OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET 0x0630 206 #define OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0630) 207 #define OMAP54XX_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638 208 #define OMAP54XX_CM_L4CFG_SAR_ROM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0638) 209 #define OMAP54XX_CM_L4CFG_OCP2SCP2_CLKCTRL_OFFSET 0x0640 210 #define OMAP54XX_CM_L4CFG_OCP2SCP2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0640) 211 #define OMAP54XX_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700 212 #define OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET 0x0720 213 #define OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0720) 214 #define OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728 215 #define OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0728) 216 #define OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET 0x0740 217 #define OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0740) 218 #define OMAP54XX_CM_L3INSTR_DLL_AGING_CLKCTRL_OFFSET 0x0748 219 #define OMAP54XX_CM_L3INSTR_DLL_AGING_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0748) 220 #define OMAP54XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL_OFFSET 0x0750 221 #define OMAP54XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0750) 222 #define OMAP54XX_CM_MIPIEXT_CLKSTCTRL_OFFSET 0x0800 223 #define OMAP54XX_CM_MIPIEXT_STATICDEP_OFFSET 0x0804 224 #define OMAP54XX_CM_MIPIEXT_DYNAMICDEP_OFFSET 0x0808 225 #define OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL_OFFSET 0x0820 226 #define OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0820) 227 #define OMAP54XX_CM_MIPIEXT_LLI_OCP_FW_CLKCTRL_OFFSET 0x0828 228 #define OMAP54XX_CM_MIPIEXT_LLI_OCP_FW_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0828) 229 #define OMAP54XX_CM_MIPIEXT_MPHY_CLKCTRL_OFFSET 0x0830 230 #define OMAP54XX_CM_MIPIEXT_MPHY_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0830) 231 #define OMAP54XX_CM_L4PER_CLKSTCTRL_OFFSET 0x0900 232 #define OMAP54XX_CM_L4PER_DYNAMICDEP_OFFSET 0x0908 233 #define OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET 0x0928 234 #define OMAP54XX_CM_L4PER_TIMER10_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0928) 235 #define OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET 0x0930 236 #define OMAP54XX_CM_L4PER_TIMER11_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0930) 237 #define OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET 0x0938 238 #define OMAP54XX_CM_L4PER_TIMER2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0938) 239 #define OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET 0x0940 240 #define OMAP54XX_CM_L4PER_TIMER3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0940) 241 #define OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET 0x0948 242 #define OMAP54XX_CM_L4PER_TIMER4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0948) 243 #define OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET 0x0950 244 #define OMAP54XX_CM_L4PER_TIMER9_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0950) 245 #define OMAP54XX_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0958 246 #define OMAP54XX_CM_L4PER_ELM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0958) 247 #define OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0960 248 #define OMAP54XX_CM_L4PER_GPIO2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0960) 249 #define OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0968 250 #define OMAP54XX_CM_L4PER_GPIO3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0968) 251 #define OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0970 252 #define OMAP54XX_CM_L4PER_GPIO4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0970) 253 #define OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0978 254 #define OMAP54XX_CM_L4PER_GPIO5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0978) 255 #define OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0980 256 #define OMAP54XX_CM_L4PER_GPIO6_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0980) 257 #define OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0988 258 #define OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0988) 259 #define OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x09a0 260 #define OMAP54XX_CM_L4PER_I2C1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09a0) 261 #define OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x09a8 262 #define OMAP54XX_CM_L4PER_I2C2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09a8) 263 #define OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x09b0 264 #define OMAP54XX_CM_L4PER_I2C3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09b0) 265 #define OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x09b8 266 #define OMAP54XX_CM_L4PER_I2C4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09b8) 267 #define OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET 0x09c0 268 #define OMAP54XX_CM_L4PER_L4_PER_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09c0) 269 #define OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x09f0 270 #define OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09f0) 271 #define OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x09f8 272 #define OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09f8) 273 #define OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0a00 274 #define OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a00) 275 #define OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0a08 276 #define OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a08) 277 #define OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET 0x0a10 278 #define OMAP54XX_CM_L4PER_GPIO7_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a10) 279 #define OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET 0x0a18 280 #define OMAP54XX_CM_L4PER_GPIO8_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a18) 281 #define OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET 0x0a20 282 #define OMAP54XX_CM_L4PER_MMC3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a20) 283 #define OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET 0x0a28 284 #define OMAP54XX_CM_L4PER_MMC4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a28) 285 #define OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0a40 286 #define OMAP54XX_CM_L4PER_UART1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a40) 287 #define OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0a48 288 #define OMAP54XX_CM_L4PER_UART2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a48) 289 #define OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0a50 290 #define OMAP54XX_CM_L4PER_UART3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a50) 291 #define OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0a58 292 #define OMAP54XX_CM_L4PER_UART4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a58) 293 #define OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET 0x0a60 294 #define OMAP54XX_CM_L4PER_MMC5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a60) 295 #define OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET 0x0a68 296 #define OMAP54XX_CM_L4PER_I2C5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a68) 297 #define OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET 0x0a70 298 #define OMAP54XX_CM_L4PER_UART5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a70) 299 #define OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET 0x0a78 300 #define OMAP54XX_CM_L4PER_UART6_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a78) 301 #define OMAP54XX_CM_L4SEC_CLKSTCTRL_OFFSET 0x0a80 302 #define OMAP54XX_CM_L4SEC_STATICDEP_OFFSET 0x0a84 303 #define OMAP54XX_CM_L4SEC_DYNAMICDEP_OFFSET 0x0a88 304 #define OMAP54XX_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x0aa0 305 #define OMAP54XX_CM_L4SEC_AES1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0aa0) 306 #define OMAP54XX_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x0aa8 307 #define OMAP54XX_CM_L4SEC_AES2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0aa8) 308 #define OMAP54XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x0ab0 309 #define OMAP54XX_CM_L4SEC_DES3DES_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ab0) 310 #define OMAP54XX_CM_L4SEC_FPKA_CLKCTRL_OFFSET 0x0ab8 311 #define OMAP54XX_CM_L4SEC_FPKA_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ab8) 312 #define OMAP54XX_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x0ac0 313 #define OMAP54XX_CM_L4SEC_RNG_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ac0) 314 #define OMAP54XX_CM_L4SEC_SHA2MD5_CLKCTRL_OFFSET 0x0ac8 315 #define OMAP54XX_CM_L4SEC_SHA2MD5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ac8) 316 #define OMAP54XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL_OFFSET 0x0ad8 317 #define OMAP54XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ad8) 318 319 /* CM_CORE.IVA_CM_CORE register offsets */ 320 #define OMAP54XX_CM_IVA_CLKSTCTRL_OFFSET 0x0000 321 #define OMAP54XX_CM_IVA_STATICDEP_OFFSET 0x0004 322 #define OMAP54XX_CM_IVA_DYNAMICDEP_OFFSET 0x0008 323 #define OMAP54XX_CM_IVA_IVA_CLKCTRL_OFFSET 0x0020 324 #define OMAP54XX_CM_IVA_IVA_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_IVA_INST, 0x0020) 325 #define OMAP54XX_CM_IVA_SL2_CLKCTRL_OFFSET 0x0028 326 #define OMAP54XX_CM_IVA_SL2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_IVA_INST, 0x0028) 327 328 /* CM_CORE.CAM_CM_CORE register offsets */ 329 #define OMAP54XX_CM_CAM_CLKSTCTRL_OFFSET 0x0000 330 #define OMAP54XX_CM_CAM_STATICDEP_OFFSET 0x0004 331 #define OMAP54XX_CM_CAM_DYNAMICDEP_OFFSET 0x0008 332 #define OMAP54XX_CM_CAM_ISS_CLKCTRL_OFFSET 0x0020 333 #define OMAP54XX_CM_CAM_ISS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0020) 334 #define OMAP54XX_CM_CAM_FDIF_CLKCTRL_OFFSET 0x0028 335 #define OMAP54XX_CM_CAM_FDIF_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0028) 336 #define OMAP54XX_CM_CAM_CAL_CLKCTRL_OFFSET 0x0030 337 #define OMAP54XX_CM_CAM_CAL_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0030) 338 339 /* CM_CORE.DSS_CM_CORE register offsets */ 340 #define OMAP54XX_CM_DSS_CLKSTCTRL_OFFSET 0x0000 341 #define OMAP54XX_CM_DSS_STATICDEP_OFFSET 0x0004 342 #define OMAP54XX_CM_DSS_DYNAMICDEP_OFFSET 0x0008 343 #define OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020 344 #define OMAP54XX_CM_DSS_DSS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_DSS_INST, 0x0020) 345 #define OMAP54XX_CM_DSS_BB2D_CLKCTRL_OFFSET 0x0030 346 #define OMAP54XX_CM_DSS_BB2D_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_DSS_INST, 0x0030) 347 348 /* CM_CORE.GPU_CM_CORE register offsets */ 349 #define OMAP54XX_CM_GPU_CLKSTCTRL_OFFSET 0x0000 350 #define OMAP54XX_CM_GPU_STATICDEP_OFFSET 0x0004 351 #define OMAP54XX_CM_GPU_DYNAMICDEP_OFFSET 0x0008 352 #define OMAP54XX_CM_GPU_GPU_CLKCTRL_OFFSET 0x0020 353 #define OMAP54XX_CM_GPU_GPU_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_GPU_INST, 0x0020) 354 355 /* CM_CORE.L3INIT_CM_CORE register offsets */ 356 #define OMAP54XX_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000 357 #define OMAP54XX_CM_L3INIT_STATICDEP_OFFSET 0x0004 358 #define OMAP54XX_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008 359 #define OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028 360 #define OMAP54XX_CM_L3INIT_MMC1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0028) 361 #define OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030 362 #define OMAP54XX_CM_L3INIT_MMC2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0030) 363 #define OMAP54XX_CM_L3INIT_HSI_CLKCTRL_OFFSET 0x0038 364 #define OMAP54XX_CM_L3INIT_HSI_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0038) 365 #define OMAP54XX_CM_L3INIT_UNIPRO2_CLKCTRL_OFFSET 0x0040 366 #define OMAP54XX_CM_L3INIT_UNIPRO2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0040) 367 #define OMAP54XX_CM_L3INIT_MPHY_UNIPRO2_CLKCTRL_OFFSET 0x0048 368 #define OMAP54XX_CM_L3INIT_MPHY_UNIPRO2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0048) 369 #define OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET 0x0058 370 #define OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0058) 371 #define OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET 0x0068 372 #define OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0068) 373 #define OMAP54XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL_OFFSET 0x0078 374 #define OMAP54XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0078) 375 #define OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088 376 #define OMAP54XX_CM_L3INIT_SATA_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0088) 377 #define OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET 0x00e0 378 #define OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00e0) 379 #define OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET 0x00e8 380 #define OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00e8) 381 #define OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET 0x00f0 382 #define OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00f0) 383 384 /* CM_CORE.CUSTEFUSE_CM_CORE register offsets */ 385 #define OMAP54XX_CM_CUSTEFUSE_CLKSTCTRL_OFFSET 0x0000 386 #define OMAP54XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL_OFFSET 0x0020 387 #define OMAP54XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CUSTEFUSE_INST, 0x0020) 388 389 #endif 390