1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * OMAP54xx CM2 instance offset macros 4 * 5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Paul Walmsley (paul@pwsan.com) 8 * Rajendra Nayak (rnayak@ti.com) 9 * Benoit Cousson (b-cousson@ti.com) 10 * 11 * This file is automatically generated from the OMAP hardware databases. 12 * We respectfully ask that any modifications to this file be coordinated 13 * with the public linux-omap@vger.kernel.org mailing list and the 14 * authors above to ensure that the autogeneration scripts are kept 15 * up-to-date with the file contents. 16 */ 17 18 #ifndef __ARCH_ARM_MACH_OMAP2_CM2_54XX_H 19 #define __ARCH_ARM_MACH_OMAP2_CM2_54XX_H 20 21 /* CM2 base address */ 22 #define OMAP54XX_CM_CORE_BASE 0x4a008000 23 24 #define OMAP54XX_CM_CORE_REGADDR(inst, reg) \ 25 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE + (inst) + (reg)) 26 27 /* CM_CORE instances */ 28 #define OMAP54XX_CM_CORE_OCP_SOCKET_INST 0x0000 29 #define OMAP54XX_CM_CORE_CKGEN_INST 0x0100 30 #define OMAP54XX_CM_CORE_COREAON_INST 0x0600 31 #define OMAP54XX_CM_CORE_CORE_INST 0x0700 32 #define OMAP54XX_CM_CORE_IVA_INST 0x1200 33 #define OMAP54XX_CM_CORE_CAM_INST 0x1300 34 #define OMAP54XX_CM_CORE_DSS_INST 0x1400 35 #define OMAP54XX_CM_CORE_GPU_INST 0x1500 36 #define OMAP54XX_CM_CORE_L3INIT_INST 0x1600 37 #define OMAP54XX_CM_CORE_CUSTEFUSE_INST 0x1700 38 #define OMAP54XX_CM_CORE_RESTORE_INST 0x1e00 39 #define OMAP54XX_CM_CORE_INSTR_INST 0x1f00 40 41 /* CM_CORE clockdomain register offsets (from instance start) */ 42 #define OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS 0x0000 43 #define OMAP54XX_CM_CORE_CORE_L3MAIN1_CDOFFS 0x0000 44 #define OMAP54XX_CM_CORE_CORE_L3MAIN2_CDOFFS 0x0100 45 #define OMAP54XX_CM_CORE_CORE_IPU_CDOFFS 0x0200 46 #define OMAP54XX_CM_CORE_CORE_DMA_CDOFFS 0x0300 47 #define OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS 0x0400 48 #define OMAP54XX_CM_CORE_CORE_C2C_CDOFFS 0x0500 49 #define OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS 0x0600 50 #define OMAP54XX_CM_CORE_CORE_L3INSTR_CDOFFS 0x0700 51 #define OMAP54XX_CM_CORE_CORE_MIPIEXT_CDOFFS 0x0800 52 #define OMAP54XX_CM_CORE_CORE_L4PER_CDOFFS 0x0900 53 #define OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS 0x0a80 54 #define OMAP54XX_CM_CORE_IVA_IVA_CDOFFS 0x0000 55 #define OMAP54XX_CM_CORE_CAM_CAM_CDOFFS 0x0000 56 #define OMAP54XX_CM_CORE_DSS_DSS_CDOFFS 0x0000 57 #define OMAP54XX_CM_CORE_GPU_GPU_CDOFFS 0x0000 58 #define OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS 0x0000 59 #define OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS 0x0000 60 61 /* CM_CORE */ 62 63 /* CM_CORE.OCP_SOCKET_CM_CORE register offsets */ 64 #define OMAP54XX_REVISION_CM_CORE_OFFSET 0x0000 65 #define OMAP54XX_CM_CM_CORE_PROFILING_CLKCTRL_OFFSET 0x0040 66 #define OMAP54XX_CM_CM_CORE_PROFILING_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_OCP_SOCKET_INST, 0x0040) 67 #define OMAP54XX_CM_CORE_DEBUG_CFG_OFFSET 0x0080 68 #define OMAP54XX_CM_CORE_DEBUG_OUT_OFFSET 0x0084 69 70 /* CM_CORE.CKGEN_CM_CORE register offsets */ 71 #define OMAP54XX_CM_CLKSEL_USB_60MHZ_OFFSET 0x0004 72 #define OMAP54XX_CM_CLKSEL_USB_60MHZ OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0004) 73 #define OMAP54XX_CM_CLKMODE_DPLL_PER_OFFSET 0x0040 74 #define OMAP54XX_CM_CLKMODE_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0040) 75 #define OMAP54XX_CM_IDLEST_DPLL_PER_OFFSET 0x0044 76 #define OMAP54XX_CM_IDLEST_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0044) 77 #define OMAP54XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0048 78 #define OMAP54XX_CM_AUTOIDLE_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0048) 79 #define OMAP54XX_CM_CLKSEL_DPLL_PER_OFFSET 0x004c 80 #define OMAP54XX_CM_CLKSEL_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x004c) 81 #define OMAP54XX_CM_DIV_M2_DPLL_PER_OFFSET 0x0050 82 #define OMAP54XX_CM_DIV_M2_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0050) 83 #define OMAP54XX_CM_DIV_M3_DPLL_PER_OFFSET 0x0054 84 #define OMAP54XX_CM_DIV_M3_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0054) 85 #define OMAP54XX_CM_DIV_H11_DPLL_PER_OFFSET 0x0058 86 #define OMAP54XX_CM_DIV_H11_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0058) 87 #define OMAP54XX_CM_DIV_H12_DPLL_PER_OFFSET 0x005c 88 #define OMAP54XX_CM_DIV_H12_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x005c) 89 #define OMAP54XX_CM_DIV_H13_DPLL_PER_OFFSET 0x0060 90 #define OMAP54XX_CM_DIV_H13_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0060) 91 #define OMAP54XX_CM_DIV_H14_DPLL_PER_OFFSET 0x0064 92 #define OMAP54XX_CM_DIV_H14_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0064) 93 #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068 94 #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c 95 #define OMAP54XX_CM_CLKMODE_DPLL_USB_OFFSET 0x0080 96 #define OMAP54XX_CM_CLKMODE_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0080) 97 #define OMAP54XX_CM_IDLEST_DPLL_USB_OFFSET 0x0084 98 #define OMAP54XX_CM_IDLEST_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0084) 99 #define OMAP54XX_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0088 100 #define OMAP54XX_CM_AUTOIDLE_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0088) 101 #define OMAP54XX_CM_CLKSEL_DPLL_USB_OFFSET 0x008c 102 #define OMAP54XX_CM_CLKSEL_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x008c) 103 #define OMAP54XX_CM_DIV_M2_DPLL_USB_OFFSET 0x0090 104 #define OMAP54XX_CM_DIV_M2_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0090) 105 #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8 106 #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac 107 #define OMAP54XX_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4 108 #define OMAP54XX_CM_CLKDCOLDO_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00b4) 109 #define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2_OFFSET 0x00c0 110 #define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c0) 111 #define OMAP54XX_CM_IDLEST_DPLL_UNIPRO2_OFFSET 0x00c4 112 #define OMAP54XX_CM_IDLEST_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c4) 113 #define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2_OFFSET 0x00c8 114 #define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c8) 115 #define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2_OFFSET 0x00cc 116 #define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00cc) 117 #define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2_OFFSET 0x00d0 118 #define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00d0) 119 #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_UNIPRO2_OFFSET 0x00e8 120 #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_UNIPRO2_OFFSET 0x00ec 121 #define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2_OFFSET 0x00f4 122 #define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00f4) 123 #define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1_OFFSET 0x0100 124 #define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0100) 125 #define OMAP54XX_CM_IDLEST_DPLL_UNIPRO1_OFFSET 0x0104 126 #define OMAP54XX_CM_IDLEST_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0104) 127 #define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1_OFFSET 0x0108 128 #define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0108) 129 #define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1_OFFSET 0x010c 130 #define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x010c) 131 #define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1_OFFSET 0x0110 132 #define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0110) 133 #define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_UNIPRO1_OFFSET 0x0128 134 #define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_UNIPRO1_OFFSET 0x012c 135 #define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1_OFFSET 0x0134 136 #define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0134) 137 138 /* CM_CORE.COREAON_CM_CORE register offsets */ 139 #define OMAP54XX_CM_COREAON_CLKSTCTRL_OFFSET 0x0000 140 #define OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET 0x0028 141 #define OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0028) 142 #define OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL_OFFSET 0x0030 143 #define OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0030) 144 #define OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET 0x0038 145 #define OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0038) 146 #define OMAP54XX_CM_COREAON_USB_PHY_CORE_CLKCTRL_OFFSET 0x0040 147 #define OMAP54XX_CM_COREAON_USB_PHY_CORE_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0040) 148 #define OMAP54XX_CM_COREAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0050 149 #define OMAP54XX_CM_COREAON_IO_SRCOMP_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0050) 150 151 /* CM_CORE.CORE_CM_CORE register offsets */ 152 #define OMAP54XX_CM_L3MAIN1_CLKSTCTRL_OFFSET 0x0000 153 #define OMAP54XX_CM_L3MAIN1_DYNAMICDEP_OFFSET 0x0008 154 #define OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET 0x0020 155 #define OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0020) 156 #define OMAP54XX_CM_L3MAIN2_CLKSTCTRL_OFFSET 0x0100 157 #define OMAP54XX_CM_L3MAIN2_DYNAMICDEP_OFFSET 0x0108 158 #define OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET 0x0120 159 #define OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0120) 160 #define OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL_OFFSET 0x0128 161 #define OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0128) 162 #define OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL_OFFSET 0x0130 163 #define OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0130) 164 #define OMAP54XX_CM_IPU_CLKSTCTRL_OFFSET 0x0200 165 #define OMAP54XX_CM_IPU_STATICDEP_OFFSET 0x0204 166 #define OMAP54XX_CM_IPU_DYNAMICDEP_OFFSET 0x0208 167 #define OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET 0x0220 168 #define OMAP54XX_CM_IPU_IPU_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0220) 169 #define OMAP54XX_CM_DMA_CLKSTCTRL_OFFSET 0x0300 170 #define OMAP54XX_CM_DMA_STATICDEP_OFFSET 0x0304 171 #define OMAP54XX_CM_DMA_DYNAMICDEP_OFFSET 0x0308 172 #define OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET 0x0320 173 #define OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0320) 174 #define OMAP54XX_CM_EMIF_CLKSTCTRL_OFFSET 0x0400 175 #define OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET 0x0420 176 #define OMAP54XX_CM_EMIF_DMM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0420) 177 #define OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET 0x0428 178 #define OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0428) 179 #define OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET 0x0430 180 #define OMAP54XX_CM_EMIF_EMIF1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0430) 181 #define OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET 0x0438 182 #define OMAP54XX_CM_EMIF_EMIF2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0438) 183 #define OMAP54XX_CM_EMIF_EMIF_DLL_CLKCTRL_OFFSET 0x0440 184 #define OMAP54XX_CM_EMIF_EMIF_DLL_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0440) 185 #define OMAP54XX_CM_C2C_CLKSTCTRL_OFFSET 0x0500 186 #define OMAP54XX_CM_C2C_STATICDEP_OFFSET 0x0504 187 #define OMAP54XX_CM_C2C_DYNAMICDEP_OFFSET 0x0508 188 #define OMAP54XX_CM_C2C_C2C_CLKCTRL_OFFSET 0x0520 189 #define OMAP54XX_CM_C2C_C2C_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0520) 190 #define OMAP54XX_CM_C2C_MODEM_ICR_CLKCTRL_OFFSET 0x0528 191 #define OMAP54XX_CM_C2C_MODEM_ICR_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0528) 192 #define OMAP54XX_CM_C2C_C2C_OCP_FW_CLKCTRL_OFFSET 0x0530 193 #define OMAP54XX_CM_C2C_C2C_OCP_FW_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0530) 194 #define OMAP54XX_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600 195 #define OMAP54XX_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608 196 #define OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620 197 #define OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0620) 198 #define OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET 0x0628 199 #define OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0628) 200 #define OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET 0x0630 201 #define OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0630) 202 #define OMAP54XX_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638 203 #define OMAP54XX_CM_L4CFG_SAR_ROM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0638) 204 #define OMAP54XX_CM_L4CFG_OCP2SCP2_CLKCTRL_OFFSET 0x0640 205 #define OMAP54XX_CM_L4CFG_OCP2SCP2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0640) 206 #define OMAP54XX_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700 207 #define OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET 0x0720 208 #define OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0720) 209 #define OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728 210 #define OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0728) 211 #define OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET 0x0740 212 #define OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0740) 213 #define OMAP54XX_CM_L3INSTR_DLL_AGING_CLKCTRL_OFFSET 0x0748 214 #define OMAP54XX_CM_L3INSTR_DLL_AGING_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0748) 215 #define OMAP54XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL_OFFSET 0x0750 216 #define OMAP54XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0750) 217 #define OMAP54XX_CM_MIPIEXT_CLKSTCTRL_OFFSET 0x0800 218 #define OMAP54XX_CM_MIPIEXT_STATICDEP_OFFSET 0x0804 219 #define OMAP54XX_CM_MIPIEXT_DYNAMICDEP_OFFSET 0x0808 220 #define OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL_OFFSET 0x0820 221 #define OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0820) 222 #define OMAP54XX_CM_MIPIEXT_LLI_OCP_FW_CLKCTRL_OFFSET 0x0828 223 #define OMAP54XX_CM_MIPIEXT_LLI_OCP_FW_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0828) 224 #define OMAP54XX_CM_MIPIEXT_MPHY_CLKCTRL_OFFSET 0x0830 225 #define OMAP54XX_CM_MIPIEXT_MPHY_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0830) 226 #define OMAP54XX_CM_L4PER_CLKSTCTRL_OFFSET 0x0900 227 #define OMAP54XX_CM_L4PER_DYNAMICDEP_OFFSET 0x0908 228 #define OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET 0x0928 229 #define OMAP54XX_CM_L4PER_TIMER10_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0928) 230 #define OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET 0x0930 231 #define OMAP54XX_CM_L4PER_TIMER11_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0930) 232 #define OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET 0x0938 233 #define OMAP54XX_CM_L4PER_TIMER2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0938) 234 #define OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET 0x0940 235 #define OMAP54XX_CM_L4PER_TIMER3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0940) 236 #define OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET 0x0948 237 #define OMAP54XX_CM_L4PER_TIMER4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0948) 238 #define OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET 0x0950 239 #define OMAP54XX_CM_L4PER_TIMER9_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0950) 240 #define OMAP54XX_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0958 241 #define OMAP54XX_CM_L4PER_ELM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0958) 242 #define OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0960 243 #define OMAP54XX_CM_L4PER_GPIO2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0960) 244 #define OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0968 245 #define OMAP54XX_CM_L4PER_GPIO3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0968) 246 #define OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0970 247 #define OMAP54XX_CM_L4PER_GPIO4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0970) 248 #define OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0978 249 #define OMAP54XX_CM_L4PER_GPIO5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0978) 250 #define OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0980 251 #define OMAP54XX_CM_L4PER_GPIO6_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0980) 252 #define OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0988 253 #define OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0988) 254 #define OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x09a0 255 #define OMAP54XX_CM_L4PER_I2C1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09a0) 256 #define OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x09a8 257 #define OMAP54XX_CM_L4PER_I2C2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09a8) 258 #define OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x09b0 259 #define OMAP54XX_CM_L4PER_I2C3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09b0) 260 #define OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x09b8 261 #define OMAP54XX_CM_L4PER_I2C4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09b8) 262 #define OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET 0x09c0 263 #define OMAP54XX_CM_L4PER_L4_PER_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09c0) 264 #define OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x09f0 265 #define OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09f0) 266 #define OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x09f8 267 #define OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09f8) 268 #define OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0a00 269 #define OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a00) 270 #define OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0a08 271 #define OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a08) 272 #define OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET 0x0a10 273 #define OMAP54XX_CM_L4PER_GPIO7_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a10) 274 #define OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET 0x0a18 275 #define OMAP54XX_CM_L4PER_GPIO8_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a18) 276 #define OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET 0x0a20 277 #define OMAP54XX_CM_L4PER_MMC3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a20) 278 #define OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET 0x0a28 279 #define OMAP54XX_CM_L4PER_MMC4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a28) 280 #define OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0a40 281 #define OMAP54XX_CM_L4PER_UART1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a40) 282 #define OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0a48 283 #define OMAP54XX_CM_L4PER_UART2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a48) 284 #define OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0a50 285 #define OMAP54XX_CM_L4PER_UART3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a50) 286 #define OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0a58 287 #define OMAP54XX_CM_L4PER_UART4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a58) 288 #define OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET 0x0a60 289 #define OMAP54XX_CM_L4PER_MMC5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a60) 290 #define OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET 0x0a68 291 #define OMAP54XX_CM_L4PER_I2C5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a68) 292 #define OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET 0x0a70 293 #define OMAP54XX_CM_L4PER_UART5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a70) 294 #define OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET 0x0a78 295 #define OMAP54XX_CM_L4PER_UART6_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a78) 296 #define OMAP54XX_CM_L4SEC_CLKSTCTRL_OFFSET 0x0a80 297 #define OMAP54XX_CM_L4SEC_STATICDEP_OFFSET 0x0a84 298 #define OMAP54XX_CM_L4SEC_DYNAMICDEP_OFFSET 0x0a88 299 #define OMAP54XX_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x0aa0 300 #define OMAP54XX_CM_L4SEC_AES1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0aa0) 301 #define OMAP54XX_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x0aa8 302 #define OMAP54XX_CM_L4SEC_AES2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0aa8) 303 #define OMAP54XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x0ab0 304 #define OMAP54XX_CM_L4SEC_DES3DES_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ab0) 305 #define OMAP54XX_CM_L4SEC_FPKA_CLKCTRL_OFFSET 0x0ab8 306 #define OMAP54XX_CM_L4SEC_FPKA_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ab8) 307 #define OMAP54XX_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x0ac0 308 #define OMAP54XX_CM_L4SEC_RNG_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ac0) 309 #define OMAP54XX_CM_L4SEC_SHA2MD5_CLKCTRL_OFFSET 0x0ac8 310 #define OMAP54XX_CM_L4SEC_SHA2MD5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ac8) 311 #define OMAP54XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL_OFFSET 0x0ad8 312 #define OMAP54XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ad8) 313 314 /* CM_CORE.IVA_CM_CORE register offsets */ 315 #define OMAP54XX_CM_IVA_CLKSTCTRL_OFFSET 0x0000 316 #define OMAP54XX_CM_IVA_STATICDEP_OFFSET 0x0004 317 #define OMAP54XX_CM_IVA_DYNAMICDEP_OFFSET 0x0008 318 #define OMAP54XX_CM_IVA_IVA_CLKCTRL_OFFSET 0x0020 319 #define OMAP54XX_CM_IVA_IVA_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_IVA_INST, 0x0020) 320 #define OMAP54XX_CM_IVA_SL2_CLKCTRL_OFFSET 0x0028 321 #define OMAP54XX_CM_IVA_SL2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_IVA_INST, 0x0028) 322 323 /* CM_CORE.CAM_CM_CORE register offsets */ 324 #define OMAP54XX_CM_CAM_CLKSTCTRL_OFFSET 0x0000 325 #define OMAP54XX_CM_CAM_STATICDEP_OFFSET 0x0004 326 #define OMAP54XX_CM_CAM_DYNAMICDEP_OFFSET 0x0008 327 #define OMAP54XX_CM_CAM_ISS_CLKCTRL_OFFSET 0x0020 328 #define OMAP54XX_CM_CAM_ISS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0020) 329 #define OMAP54XX_CM_CAM_FDIF_CLKCTRL_OFFSET 0x0028 330 #define OMAP54XX_CM_CAM_FDIF_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0028) 331 #define OMAP54XX_CM_CAM_CAL_CLKCTRL_OFFSET 0x0030 332 #define OMAP54XX_CM_CAM_CAL_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0030) 333 334 /* CM_CORE.DSS_CM_CORE register offsets */ 335 #define OMAP54XX_CM_DSS_CLKSTCTRL_OFFSET 0x0000 336 #define OMAP54XX_CM_DSS_STATICDEP_OFFSET 0x0004 337 #define OMAP54XX_CM_DSS_DYNAMICDEP_OFFSET 0x0008 338 #define OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020 339 #define OMAP54XX_CM_DSS_DSS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_DSS_INST, 0x0020) 340 #define OMAP54XX_CM_DSS_BB2D_CLKCTRL_OFFSET 0x0030 341 #define OMAP54XX_CM_DSS_BB2D_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_DSS_INST, 0x0030) 342 343 /* CM_CORE.GPU_CM_CORE register offsets */ 344 #define OMAP54XX_CM_GPU_CLKSTCTRL_OFFSET 0x0000 345 #define OMAP54XX_CM_GPU_STATICDEP_OFFSET 0x0004 346 #define OMAP54XX_CM_GPU_DYNAMICDEP_OFFSET 0x0008 347 #define OMAP54XX_CM_GPU_GPU_CLKCTRL_OFFSET 0x0020 348 #define OMAP54XX_CM_GPU_GPU_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_GPU_INST, 0x0020) 349 350 /* CM_CORE.L3INIT_CM_CORE register offsets */ 351 #define OMAP54XX_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000 352 #define OMAP54XX_CM_L3INIT_STATICDEP_OFFSET 0x0004 353 #define OMAP54XX_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008 354 #define OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028 355 #define OMAP54XX_CM_L3INIT_MMC1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0028) 356 #define OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030 357 #define OMAP54XX_CM_L3INIT_MMC2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0030) 358 #define OMAP54XX_CM_L3INIT_HSI_CLKCTRL_OFFSET 0x0038 359 #define OMAP54XX_CM_L3INIT_HSI_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0038) 360 #define OMAP54XX_CM_L3INIT_UNIPRO2_CLKCTRL_OFFSET 0x0040 361 #define OMAP54XX_CM_L3INIT_UNIPRO2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0040) 362 #define OMAP54XX_CM_L3INIT_MPHY_UNIPRO2_CLKCTRL_OFFSET 0x0048 363 #define OMAP54XX_CM_L3INIT_MPHY_UNIPRO2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0048) 364 #define OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET 0x0058 365 #define OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0058) 366 #define OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET 0x0068 367 #define OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0068) 368 #define OMAP54XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL_OFFSET 0x0078 369 #define OMAP54XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0078) 370 #define OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088 371 #define OMAP54XX_CM_L3INIT_SATA_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0088) 372 #define OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET 0x00e0 373 #define OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00e0) 374 #define OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET 0x00e8 375 #define OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00e8) 376 #define OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET 0x00f0 377 #define OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00f0) 378 379 /* CM_CORE.CUSTEFUSE_CM_CORE register offsets */ 380 #define OMAP54XX_CM_CUSTEFUSE_CLKSTCTRL_OFFSET 0x0000 381 #define OMAP54XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL_OFFSET 0x0020 382 #define OMAP54XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CUSTEFUSE_INST, 0x0020) 383 384 #endif 385