1d198b514SPaul Walmsley /* 2d198b514SPaul Walmsley * OMAP44xx CM2 instance offset macros 3d198b514SPaul Walmsley * 4d198b514SPaul Walmsley * Copyright (C) 2009-2010 Texas Instruments, Inc. 5d198b514SPaul Walmsley * Copyright (C) 2009-2010 Nokia Corporation 6d198b514SPaul Walmsley * 7d198b514SPaul Walmsley * Paul Walmsley (paul@pwsan.com) 8d198b514SPaul Walmsley * Rajendra Nayak (rnayak@ti.com) 9d198b514SPaul Walmsley * Benoit Cousson (b-cousson@ti.com) 10d198b514SPaul Walmsley * 11d198b514SPaul Walmsley * This file is automatically generated from the OMAP hardware databases. 12d198b514SPaul Walmsley * We respectfully ask that any modifications to this file be coordinated 13d198b514SPaul Walmsley * with the public linux-omap@vger.kernel.org mailing list and the 14d198b514SPaul Walmsley * authors above to ensure that the autogeneration scripts are kept 15d198b514SPaul Walmsley * up-to-date with the file contents. 16d198b514SPaul Walmsley * 17d198b514SPaul Walmsley * This program is free software; you can redistribute it and/or modify 18d198b514SPaul Walmsley * it under the terms of the GNU General Public License version 2 as 19d198b514SPaul Walmsley * published by the Free Software Foundation. 20d198b514SPaul Walmsley * 21d198b514SPaul Walmsley * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX", 22d198b514SPaul Walmsley * or "OMAP4430". 23d198b514SPaul Walmsley */ 24d198b514SPaul Walmsley 25d198b514SPaul Walmsley #ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H 26d198b514SPaul Walmsley #define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H 27d198b514SPaul Walmsley 28d198b514SPaul Walmsley /* CM2 base address */ 29d198b514SPaul Walmsley #define OMAP4430_CM2_BASE 0x4a008000 30d198b514SPaul Walmsley 31cdb54c44SPaul Walmsley #define OMAP44XX_CM2_REGADDR(inst, reg) \ 32cdb54c44SPaul Walmsley OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (inst) + (reg)) 33d198b514SPaul Walmsley 34d198b514SPaul Walmsley /* CM2 instances */ 35cdb54c44SPaul Walmsley #define OMAP4430_CM2_OCP_SOCKET_INST 0x0000 36cdb54c44SPaul Walmsley #define OMAP4430_CM2_CKGEN_INST 0x0100 37cdb54c44SPaul Walmsley #define OMAP4430_CM2_ALWAYS_ON_INST 0x0600 38cdb54c44SPaul Walmsley #define OMAP4430_CM2_CORE_INST 0x0700 39cdb54c44SPaul Walmsley #define OMAP4430_CM2_IVAHD_INST 0x0f00 40cdb54c44SPaul Walmsley #define OMAP4430_CM2_CAM_INST 0x1000 41cdb54c44SPaul Walmsley #define OMAP4430_CM2_DSS_INST 0x1100 42cdb54c44SPaul Walmsley #define OMAP4430_CM2_GFX_INST 0x1200 43cdb54c44SPaul Walmsley #define OMAP4430_CM2_L3INIT_INST 0x1300 44cdb54c44SPaul Walmsley #define OMAP4430_CM2_L4PER_INST 0x1400 45cdb54c44SPaul Walmsley #define OMAP4430_CM2_CEFUSE_INST 0x1600 46cdb54c44SPaul Walmsley #define OMAP4430_CM2_RESTORE_INST 0x1e00 47cdb54c44SPaul Walmsley #define OMAP4430_CM2_INSTR_INST 0x1f00 48d198b514SPaul Walmsley 49e4156ee5SPaul Walmsley /* CM2 clockdomain register offsets (from instance start) */ 50e4156ee5SPaul Walmsley #define OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS 0x0000 51e4156ee5SPaul Walmsley #define OMAP4430_CM2_CORE_L3_1_CDOFFS 0x0000 52e4156ee5SPaul Walmsley #define OMAP4430_CM2_CORE_L3_2_CDOFFS 0x0100 53e4156ee5SPaul Walmsley #define OMAP4430_CM2_CORE_DUCATI_CDOFFS 0x0200 54e4156ee5SPaul Walmsley #define OMAP4430_CM2_CORE_SDMA_CDOFFS 0x0300 55e4156ee5SPaul Walmsley #define OMAP4430_CM2_CORE_MEMIF_CDOFFS 0x0400 56e4156ee5SPaul Walmsley #define OMAP4430_CM2_CORE_D2D_CDOFFS 0x0500 57e4156ee5SPaul Walmsley #define OMAP4430_CM2_CORE_L4CFG_CDOFFS 0x0600 58e4156ee5SPaul Walmsley #define OMAP4430_CM2_CORE_L3INSTR_CDOFFS 0x0700 59e4156ee5SPaul Walmsley #define OMAP4430_CM2_IVAHD_IVAHD_CDOFFS 0x0000 60e4156ee5SPaul Walmsley #define OMAP4430_CM2_CAM_CAM_CDOFFS 0x0000 61e4156ee5SPaul Walmsley #define OMAP4430_CM2_DSS_DSS_CDOFFS 0x0000 62e4156ee5SPaul Walmsley #define OMAP4430_CM2_GFX_GFX_CDOFFS 0x0000 63e4156ee5SPaul Walmsley #define OMAP4430_CM2_L3INIT_L3INIT_CDOFFS 0x0000 64e4156ee5SPaul Walmsley #define OMAP4430_CM2_L4PER_L4PER_CDOFFS 0x0000 65e4156ee5SPaul Walmsley #define OMAP4430_CM2_L4PER_L4SEC_CDOFFS 0x0180 66e4156ee5SPaul Walmsley #define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS 0x0000 67e4156ee5SPaul Walmsley 68d198b514SPaul Walmsley 69d198b514SPaul Walmsley /* CM2 */ 70d198b514SPaul Walmsley 71d198b514SPaul Walmsley /* CM2.OCP_SOCKET_CM2 register offsets */ 72d198b514SPaul Walmsley #define OMAP4_REVISION_CM2_OFFSET 0x0000 73cdb54c44SPaul Walmsley #define OMAP4430_REVISION_CM2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0000) 74d198b514SPaul Walmsley #define OMAP4_CM_CM2_PROFILING_CLKCTRL_OFFSET 0x0040 75cdb54c44SPaul Walmsley #define OMAP4430_CM_CM2_PROFILING_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0040) 76d198b514SPaul Walmsley 77d198b514SPaul Walmsley /* CM2.CKGEN_CM2 register offsets */ 78d198b514SPaul Walmsley #define OMAP4_CM_CLKSEL_DUCATI_ISS_ROOT_OFFSET 0x0000 79cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0000) 80d198b514SPaul Walmsley #define OMAP4_CM_CLKSEL_USB_60MHZ_OFFSET 0x0004 81cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKSEL_USB_60MHZ OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0004) 82d198b514SPaul Walmsley #define OMAP4_CM_SCALE_FCLK_OFFSET 0x0008 83cdb54c44SPaul Walmsley #define OMAP4430_CM_SCALE_FCLK OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0008) 84d198b514SPaul Walmsley #define OMAP4_CM_CORE_DVFS_PERF1_OFFSET 0x0010 85cdb54c44SPaul Walmsley #define OMAP4430_CM_CORE_DVFS_PERF1 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0010) 86d198b514SPaul Walmsley #define OMAP4_CM_CORE_DVFS_PERF2_OFFSET 0x0014 87cdb54c44SPaul Walmsley #define OMAP4430_CM_CORE_DVFS_PERF2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0014) 88d198b514SPaul Walmsley #define OMAP4_CM_CORE_DVFS_PERF3_OFFSET 0x0018 89cdb54c44SPaul Walmsley #define OMAP4430_CM_CORE_DVFS_PERF3 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0018) 90d198b514SPaul Walmsley #define OMAP4_CM_CORE_DVFS_PERF4_OFFSET 0x001c 91cdb54c44SPaul Walmsley #define OMAP4430_CM_CORE_DVFS_PERF4 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x001c) 92d198b514SPaul Walmsley #define OMAP4_CM_CORE_DVFS_CURRENT_OFFSET 0x0024 93cdb54c44SPaul Walmsley #define OMAP4430_CM_CORE_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0024) 94d198b514SPaul Walmsley #define OMAP4_CM_IVA_DVFS_PERF_TESLA_OFFSET 0x0028 95cdb54c44SPaul Walmsley #define OMAP4430_CM_IVA_DVFS_PERF_TESLA OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0028) 96d198b514SPaul Walmsley #define OMAP4_CM_IVA_DVFS_PERF_IVAHD_OFFSET 0x002c 97cdb54c44SPaul Walmsley #define OMAP4430_CM_IVA_DVFS_PERF_IVAHD OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x002c) 98d198b514SPaul Walmsley #define OMAP4_CM_IVA_DVFS_PERF_ABE_OFFSET 0x0030 99cdb54c44SPaul Walmsley #define OMAP4430_CM_IVA_DVFS_PERF_ABE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0030) 100d198b514SPaul Walmsley #define OMAP4_CM_IVA_DVFS_CURRENT_OFFSET 0x0038 101cdb54c44SPaul Walmsley #define OMAP4430_CM_IVA_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0038) 102d198b514SPaul Walmsley #define OMAP4_CM_CLKMODE_DPLL_PER_OFFSET 0x0040 103cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKMODE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0040) 104d198b514SPaul Walmsley #define OMAP4_CM_IDLEST_DPLL_PER_OFFSET 0x0044 105cdb54c44SPaul Walmsley #define OMAP4430_CM_IDLEST_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0044) 106d198b514SPaul Walmsley #define OMAP4_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0048 107cdb54c44SPaul Walmsley #define OMAP4430_CM_AUTOIDLE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0048) 108d198b514SPaul Walmsley #define OMAP4_CM_CLKSEL_DPLL_PER_OFFSET 0x004c 109cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKSEL_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x004c) 110d198b514SPaul Walmsley #define OMAP4_CM_DIV_M2_DPLL_PER_OFFSET 0x0050 111cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M2_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0050) 112d198b514SPaul Walmsley #define OMAP4_CM_DIV_M3_DPLL_PER_OFFSET 0x0054 113cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M3_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0054) 114d198b514SPaul Walmsley #define OMAP4_CM_DIV_M4_DPLL_PER_OFFSET 0x0058 115cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M4_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0058) 116d198b514SPaul Walmsley #define OMAP4_CM_DIV_M5_DPLL_PER_OFFSET 0x005c 117cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M5_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x005c) 118d198b514SPaul Walmsley #define OMAP4_CM_DIV_M6_DPLL_PER_OFFSET 0x0060 119cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M6_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0060) 120d198b514SPaul Walmsley #define OMAP4_CM_DIV_M7_DPLL_PER_OFFSET 0x0064 121cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0064) 122d198b514SPaul Walmsley #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068 123cdb54c44SPaul Walmsley #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0068) 124cdb54c44SPaul Walmsley #define OMAP4_CM_SSC_INSTFREQDIV_DPLL_PER_OFFSET 0x006c 125cdb54c44SPaul Walmsley #define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c) 126d198b514SPaul Walmsley #define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080 127cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0080) 128d198b514SPaul Walmsley #define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084 129cdb54c44SPaul Walmsley #define OMAP4430_CM_IDLEST_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0084) 130d198b514SPaul Walmsley #define OMAP4_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0088 131cdb54c44SPaul Walmsley #define OMAP4430_CM_AUTOIDLE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0088) 132d198b514SPaul Walmsley #define OMAP4_CM_CLKSEL_DPLL_USB_OFFSET 0x008c 133cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKSEL_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x008c) 134d198b514SPaul Walmsley #define OMAP4_CM_DIV_M2_DPLL_USB_OFFSET 0x0090 135cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0090) 136d198b514SPaul Walmsley #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8 137cdb54c44SPaul Walmsley #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00a8) 138cdb54c44SPaul Walmsley #define OMAP4_CM_SSC_INSTFREQDIV_DPLL_USB_OFFSET 0x00ac 139cdb54c44SPaul Walmsley #define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac) 140d198b514SPaul Walmsley #define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4 141cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00b4) 142d198b514SPaul Walmsley #define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET 0x00c0 143cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKMODE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c0) 144d198b514SPaul Walmsley #define OMAP4_CM_IDLEST_DPLL_UNIPRO_OFFSET 0x00c4 145cdb54c44SPaul Walmsley #define OMAP4430_CM_IDLEST_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c4) 146d198b514SPaul Walmsley #define OMAP4_CM_AUTOIDLE_DPLL_UNIPRO_OFFSET 0x00c8 147cdb54c44SPaul Walmsley #define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c8) 148d198b514SPaul Walmsley #define OMAP4_CM_CLKSEL_DPLL_UNIPRO_OFFSET 0x00cc 149cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKSEL_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00cc) 150d198b514SPaul Walmsley #define OMAP4_CM_DIV_M2_DPLL_UNIPRO_OFFSET 0x00d0 151cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00d0) 152d198b514SPaul Walmsley #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET 0x00e8 153cdb54c44SPaul Walmsley #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00e8) 154cdb54c44SPaul Walmsley #define OMAP4_CM_SSC_INSTFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec 155cdb54c44SPaul Walmsley #define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec) 156d198b514SPaul Walmsley 157d198b514SPaul Walmsley /* CM2.ALWAYS_ON_CM2 register offsets */ 158d198b514SPaul Walmsley #define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET 0x0000 159cdb54c44SPaul Walmsley #define OMAP4430_CM_ALWON_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0000) 160d198b514SPaul Walmsley #define OMAP4_CM_ALWON_MDMINTC_CLKCTRL_OFFSET 0x0020 161cdb54c44SPaul Walmsley #define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0020) 162d198b514SPaul Walmsley #define OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET 0x0028 163cdb54c44SPaul Walmsley #define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0028) 164d198b514SPaul Walmsley #define OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET 0x0030 165cdb54c44SPaul Walmsley #define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0030) 166d198b514SPaul Walmsley #define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET 0x0038 167cdb54c44SPaul Walmsley #define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0038) 168d198b514SPaul Walmsley #define OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET 0x0040 169cdb54c44SPaul Walmsley #define OMAP4430_CM_ALWON_USBPHY_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0040) 170d198b514SPaul Walmsley 171d198b514SPaul Walmsley /* CM2.CORE_CM2 register offsets */ 172d198b514SPaul Walmsley #define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET 0x0000 173cdb54c44SPaul Walmsley #define OMAP4430_CM_L3_1_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0000) 174d198b514SPaul Walmsley #define OMAP4_CM_L3_1_DYNAMICDEP_OFFSET 0x0008 175cdb54c44SPaul Walmsley #define OMAP4430_CM_L3_1_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0008) 176d198b514SPaul Walmsley #define OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET 0x0020 177cdb54c44SPaul Walmsley #define OMAP4430_CM_L3_1_L3_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0020) 178d198b514SPaul Walmsley #define OMAP4_CM_L3_2_CLKSTCTRL_OFFSET 0x0100 179cdb54c44SPaul Walmsley #define OMAP4430_CM_L3_2_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0100) 180d198b514SPaul Walmsley #define OMAP4_CM_L3_2_DYNAMICDEP_OFFSET 0x0108 181cdb54c44SPaul Walmsley #define OMAP4430_CM_L3_2_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0108) 182d198b514SPaul Walmsley #define OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET 0x0120 183cdb54c44SPaul Walmsley #define OMAP4430_CM_L3_2_L3_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0120) 184d198b514SPaul Walmsley #define OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET 0x0128 185cdb54c44SPaul Walmsley #define OMAP4430_CM_L3_2_GPMC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0128) 186d198b514SPaul Walmsley #define OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET 0x0130 187cdb54c44SPaul Walmsley #define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0130) 188d198b514SPaul Walmsley #define OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET 0x0200 189cdb54c44SPaul Walmsley #define OMAP4430_CM_DUCATI_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0200) 190d198b514SPaul Walmsley #define OMAP4_CM_DUCATI_STATICDEP_OFFSET 0x0204 191cdb54c44SPaul Walmsley #define OMAP4430_CM_DUCATI_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0204) 192d198b514SPaul Walmsley #define OMAP4_CM_DUCATI_DYNAMICDEP_OFFSET 0x0208 193cdb54c44SPaul Walmsley #define OMAP4430_CM_DUCATI_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0208) 194d198b514SPaul Walmsley #define OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET 0x0220 195cdb54c44SPaul Walmsley #define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0220) 196d198b514SPaul Walmsley #define OMAP4_CM_SDMA_CLKSTCTRL_OFFSET 0x0300 197cdb54c44SPaul Walmsley #define OMAP4430_CM_SDMA_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0300) 198d198b514SPaul Walmsley #define OMAP4_CM_SDMA_STATICDEP_OFFSET 0x0304 199cdb54c44SPaul Walmsley #define OMAP4430_CM_SDMA_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0304) 200d198b514SPaul Walmsley #define OMAP4_CM_SDMA_DYNAMICDEP_OFFSET 0x0308 201cdb54c44SPaul Walmsley #define OMAP4430_CM_SDMA_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0308) 202d198b514SPaul Walmsley #define OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET 0x0320 203cdb54c44SPaul Walmsley #define OMAP4430_CM_SDMA_SDMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0320) 204d198b514SPaul Walmsley #define OMAP4_CM_MEMIF_CLKSTCTRL_OFFSET 0x0400 205cdb54c44SPaul Walmsley #define OMAP4430_CM_MEMIF_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0400) 206d198b514SPaul Walmsley #define OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET 0x0420 207cdb54c44SPaul Walmsley #define OMAP4430_CM_MEMIF_DMM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0420) 208d198b514SPaul Walmsley #define OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET 0x0428 209cdb54c44SPaul Walmsley #define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0428) 210d198b514SPaul Walmsley #define OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET 0x0430 211cdb54c44SPaul Walmsley #define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0430) 212d198b514SPaul Walmsley #define OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET 0x0438 213cdb54c44SPaul Walmsley #define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0438) 214d198b514SPaul Walmsley #define OMAP4_CM_MEMIF_DLL_CLKCTRL_OFFSET 0x0440 215cdb54c44SPaul Walmsley #define OMAP4430_CM_MEMIF_DLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0440) 216d198b514SPaul Walmsley #define OMAP4_CM_MEMIF_EMIF_H1_CLKCTRL_OFFSET 0x0450 217cdb54c44SPaul Walmsley #define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0450) 218d198b514SPaul Walmsley #define OMAP4_CM_MEMIF_EMIF_H2_CLKCTRL_OFFSET 0x0458 219cdb54c44SPaul Walmsley #define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0458) 220d198b514SPaul Walmsley #define OMAP4_CM_MEMIF_DLL_H_CLKCTRL_OFFSET 0x0460 221cdb54c44SPaul Walmsley #define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0460) 222d198b514SPaul Walmsley #define OMAP4_CM_D2D_CLKSTCTRL_OFFSET 0x0500 223cdb54c44SPaul Walmsley #define OMAP4430_CM_D2D_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0500) 224d198b514SPaul Walmsley #define OMAP4_CM_D2D_STATICDEP_OFFSET 0x0504 225cdb54c44SPaul Walmsley #define OMAP4430_CM_D2D_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0504) 226d198b514SPaul Walmsley #define OMAP4_CM_D2D_DYNAMICDEP_OFFSET 0x0508 227cdb54c44SPaul Walmsley #define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0508) 228d198b514SPaul Walmsley #define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET 0x0520 229cdb54c44SPaul Walmsley #define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0520) 230cdb54c44SPaul Walmsley #define OMAP4_CM_D2D_INSTEM_ICR_CLKCTRL_OFFSET 0x0528 231cdb54c44SPaul Walmsley #define OMAP4430_CM_D2D_INSTEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528) 232d198b514SPaul Walmsley #define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET 0x0530 233cdb54c44SPaul Walmsley #define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0530) 234d198b514SPaul Walmsley #define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600 235cdb54c44SPaul Walmsley #define OMAP4430_CM_L4CFG_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0600) 236d198b514SPaul Walmsley #define OMAP4_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608 237cdb54c44SPaul Walmsley #define OMAP4430_CM_L4CFG_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0608) 238d198b514SPaul Walmsley #define OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620 239cdb54c44SPaul Walmsley #define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0620) 240d198b514SPaul Walmsley #define OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET 0x0628 241cdb54c44SPaul Walmsley #define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0628) 242d198b514SPaul Walmsley #define OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET 0x0630 243cdb54c44SPaul Walmsley #define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0630) 244d198b514SPaul Walmsley #define OMAP4_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638 245cdb54c44SPaul Walmsley #define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0638) 246d198b514SPaul Walmsley #define OMAP4_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700 247cdb54c44SPaul Walmsley #define OMAP4430_CM_L3INSTR_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0700) 248d198b514SPaul Walmsley #define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET 0x0720 249cdb54c44SPaul Walmsley #define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0720) 250d198b514SPaul Walmsley #define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728 251cdb54c44SPaul Walmsley #define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0728) 252d198b514SPaul Walmsley #define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET 0x0740 253cdb54c44SPaul Walmsley #define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0740) 254d198b514SPaul Walmsley 255d198b514SPaul Walmsley /* CM2.IVAHD_CM2 register offsets */ 256d198b514SPaul Walmsley #define OMAP4_CM_IVAHD_CLKSTCTRL_OFFSET 0x0000 257cdb54c44SPaul Walmsley #define OMAP4430_CM_IVAHD_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0000) 258d198b514SPaul Walmsley #define OMAP4_CM_IVAHD_STATICDEP_OFFSET 0x0004 259cdb54c44SPaul Walmsley #define OMAP4430_CM_IVAHD_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0004) 260d198b514SPaul Walmsley #define OMAP4_CM_IVAHD_DYNAMICDEP_OFFSET 0x0008 261cdb54c44SPaul Walmsley #define OMAP4430_CM_IVAHD_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0008) 262d198b514SPaul Walmsley #define OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET 0x0020 263cdb54c44SPaul Walmsley #define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0020) 264d198b514SPaul Walmsley #define OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET 0x0028 265cdb54c44SPaul Walmsley #define OMAP4430_CM_IVAHD_SL2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0028) 266d198b514SPaul Walmsley 267d198b514SPaul Walmsley /* CM2.CAM_CM2 register offsets */ 268d198b514SPaul Walmsley #define OMAP4_CM_CAM_CLKSTCTRL_OFFSET 0x0000 269cdb54c44SPaul Walmsley #define OMAP4430_CM_CAM_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0000) 270d198b514SPaul Walmsley #define OMAP4_CM_CAM_STATICDEP_OFFSET 0x0004 271cdb54c44SPaul Walmsley #define OMAP4430_CM_CAM_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0004) 272d198b514SPaul Walmsley #define OMAP4_CM_CAM_DYNAMICDEP_OFFSET 0x0008 273cdb54c44SPaul Walmsley #define OMAP4430_CM_CAM_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0008) 274d198b514SPaul Walmsley #define OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET 0x0020 275cdb54c44SPaul Walmsley #define OMAP4430_CM_CAM_ISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0020) 276d198b514SPaul Walmsley #define OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET 0x0028 277cdb54c44SPaul Walmsley #define OMAP4430_CM_CAM_FDIF_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0028) 278d198b514SPaul Walmsley 279d198b514SPaul Walmsley /* CM2.DSS_CM2 register offsets */ 280d198b514SPaul Walmsley #define OMAP4_CM_DSS_CLKSTCTRL_OFFSET 0x0000 281cdb54c44SPaul Walmsley #define OMAP4430_CM_DSS_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0000) 282d198b514SPaul Walmsley #define OMAP4_CM_DSS_STATICDEP_OFFSET 0x0004 283cdb54c44SPaul Walmsley #define OMAP4430_CM_DSS_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0004) 284d198b514SPaul Walmsley #define OMAP4_CM_DSS_DYNAMICDEP_OFFSET 0x0008 285cdb54c44SPaul Walmsley #define OMAP4430_CM_DSS_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0008) 286d198b514SPaul Walmsley #define OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020 287cdb54c44SPaul Walmsley #define OMAP4430_CM_DSS_DSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0020) 288d198b514SPaul Walmsley #define OMAP4_CM_DSS_DEISS_CLKCTRL_OFFSET 0x0028 289cdb54c44SPaul Walmsley #define OMAP4430_CM_DSS_DEISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0028) 290d198b514SPaul Walmsley 291d198b514SPaul Walmsley /* CM2.GFX_CM2 register offsets */ 292d198b514SPaul Walmsley #define OMAP4_CM_GFX_CLKSTCTRL_OFFSET 0x0000 293cdb54c44SPaul Walmsley #define OMAP4430_CM_GFX_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0000) 294d198b514SPaul Walmsley #define OMAP4_CM_GFX_STATICDEP_OFFSET 0x0004 295cdb54c44SPaul Walmsley #define OMAP4430_CM_GFX_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0004) 296d198b514SPaul Walmsley #define OMAP4_CM_GFX_DYNAMICDEP_OFFSET 0x0008 297cdb54c44SPaul Walmsley #define OMAP4430_CM_GFX_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0008) 298d198b514SPaul Walmsley #define OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET 0x0020 299cdb54c44SPaul Walmsley #define OMAP4430_CM_GFX_GFX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0020) 300d198b514SPaul Walmsley 301d198b514SPaul Walmsley /* CM2.L3INIT_CM2 register offsets */ 302d198b514SPaul Walmsley #define OMAP4_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000 303cdb54c44SPaul Walmsley #define OMAP4430_CM_L3INIT_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0000) 304d198b514SPaul Walmsley #define OMAP4_CM_L3INIT_STATICDEP_OFFSET 0x0004 305cdb54c44SPaul Walmsley #define OMAP4430_CM_L3INIT_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0004) 306d198b514SPaul Walmsley #define OMAP4_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008 307cdb54c44SPaul Walmsley #define OMAP4430_CM_L3INIT_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0008) 308d198b514SPaul Walmsley #define OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028 309cdb54c44SPaul Walmsley #define OMAP4430_CM_L3INIT_MMC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0028) 310d198b514SPaul Walmsley #define OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030 311cdb54c44SPaul Walmsley #define OMAP4430_CM_L3INIT_MMC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0030) 312d198b514SPaul Walmsley #define OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET 0x0038 313cdb54c44SPaul Walmsley #define OMAP4430_CM_L3INIT_HSI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0038) 314d198b514SPaul Walmsley #define OMAP4_CM_L3INIT_UNIPRO1_CLKCTRL_OFFSET 0x0040 315cdb54c44SPaul Walmsley #define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0040) 316d198b514SPaul Walmsley #define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET 0x0058 317cdb54c44SPaul Walmsley #define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0058) 318d198b514SPaul Walmsley #define OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET 0x0060 319cdb54c44SPaul Walmsley #define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0060) 320d198b514SPaul Walmsley #define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET 0x0068 321cdb54c44SPaul Walmsley #define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0068) 322d198b514SPaul Walmsley #define OMAP4_CM_L3INIT_P1500_CLKCTRL_OFFSET 0x0078 323cdb54c44SPaul Walmsley #define OMAP4430_CM_L3INIT_P1500_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0078) 324d198b514SPaul Walmsley #define OMAP4_CM_L3INIT_EMAC_CLKCTRL_OFFSET 0x0080 325cdb54c44SPaul Walmsley #define OMAP4430_CM_L3INIT_EMAC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0080) 326d198b514SPaul Walmsley #define OMAP4_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088 327cdb54c44SPaul Walmsley #define OMAP4430_CM_L3INIT_SATA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0088) 328d198b514SPaul Walmsley #define OMAP4_CM_L3INIT_TPPSS_CLKCTRL_OFFSET 0x0090 329cdb54c44SPaul Walmsley #define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0090) 330d198b514SPaul Walmsley #define OMAP4_CM_L3INIT_PCIESS_CLKCTRL_OFFSET 0x0098 331cdb54c44SPaul Walmsley #define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0098) 332d198b514SPaul Walmsley #define OMAP4_CM_L3INIT_CCPTX_CLKCTRL_OFFSET 0x00a8 333cdb54c44SPaul Walmsley #define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00a8) 334d198b514SPaul Walmsley #define OMAP4_CM_L3INIT_XHPI_CLKCTRL_OFFSET 0x00c0 335cdb54c44SPaul Walmsley #define OMAP4430_CM_L3INIT_XHPI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00c0) 336d198b514SPaul Walmsley #define OMAP4_CM_L3INIT_MMC6_CLKCTRL_OFFSET 0x00c8 337cdb54c44SPaul Walmsley #define OMAP4430_CM_L3INIT_MMC6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00c8) 338d198b514SPaul Walmsley #define OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET 0x00d0 339cdb54c44SPaul Walmsley #define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00d0) 340d198b514SPaul Walmsley #define OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET 0x00e0 341cdb54c44SPaul Walmsley #define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00e0) 342d198b514SPaul Walmsley 343d198b514SPaul Walmsley /* CM2.L4PER_CM2 register offsets */ 344d198b514SPaul Walmsley #define OMAP4_CM_L4PER_CLKSTCTRL_OFFSET 0x0000 345cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0000) 346d198b514SPaul Walmsley #define OMAP4_CM_L4PER_DYNAMICDEP_OFFSET 0x0008 347cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0008) 348d198b514SPaul Walmsley #define OMAP4_CM_L4PER_ADC_CLKCTRL_OFFSET 0x0020 349cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_ADC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0020) 350d198b514SPaul Walmsley #define OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET 0x0028 351cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0028) 352d198b514SPaul Walmsley #define OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET 0x0030 353cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0030) 354d198b514SPaul Walmsley #define OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET 0x0038 355cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0038) 356d198b514SPaul Walmsley #define OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET 0x0040 357cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0040) 358d198b514SPaul Walmsley #define OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET 0x0048 359cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0048) 360d198b514SPaul Walmsley #define OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET 0x0050 361cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0050) 362d198b514SPaul Walmsley #define OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058 363cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_ELM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0058) 364d198b514SPaul Walmsley #define OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060 365cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_GPIO2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0060) 366d198b514SPaul Walmsley #define OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068 367cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_GPIO3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0068) 368d198b514SPaul Walmsley #define OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070 369cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_GPIO4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0070) 370d198b514SPaul Walmsley #define OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078 371cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_GPIO5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0078) 372d198b514SPaul Walmsley #define OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080 373cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_GPIO6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0080) 374d198b514SPaul Walmsley #define OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088 375cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0088) 376d198b514SPaul Walmsley #define OMAP4_CM_L4PER_HECC1_CLKCTRL_OFFSET 0x0090 377cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_HECC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0090) 378d198b514SPaul Walmsley #define OMAP4_CM_L4PER_HECC2_CLKCTRL_OFFSET 0x0098 379cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_HECC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0098) 380d198b514SPaul Walmsley #define OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0 381cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_I2C1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00a0) 382d198b514SPaul Walmsley #define OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8 383cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_I2C2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00a8) 384d198b514SPaul Walmsley #define OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0 385cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_I2C3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00b0) 386d198b514SPaul Walmsley #define OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8 387cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_I2C4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00b8) 388d198b514SPaul Walmsley #define OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET 0x00c0 389cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_L4PER_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00c0) 390d198b514SPaul Walmsley #define OMAP4_CM_L4PER_MCASP2_CLKCTRL_OFFSET 0x00d0 391cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_MCASP2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00d0) 392d198b514SPaul Walmsley #define OMAP4_CM_L4PER_MCASP3_CLKCTRL_OFFSET 0x00d8 393cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_MCASP3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00d8) 394d198b514SPaul Walmsley #define OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET 0x00e0 395cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00e0) 396d198b514SPaul Walmsley #define OMAP4_CM_L4PER_MGATE_CLKCTRL_OFFSET 0x00e8 397cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_MGATE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00e8) 398d198b514SPaul Walmsley #define OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0 399cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00f0) 400d198b514SPaul Walmsley #define OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8 401cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00f8) 402d198b514SPaul Walmsley #define OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100 403cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0100) 404d198b514SPaul Walmsley #define OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108 405cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0108) 406d198b514SPaul Walmsley #define OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET 0x0120 407cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0120) 408d198b514SPaul Walmsley #define OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET 0x0128 409cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0128) 410d198b514SPaul Walmsley #define OMAP4_CM_L4PER_MSPROHG_CLKCTRL_OFFSET 0x0130 411cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0130) 412d198b514SPaul Walmsley #define OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET 0x0138 413cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0138) 414d198b514SPaul Walmsley #define OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140 415cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_UART1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0140) 416d198b514SPaul Walmsley #define OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148 417cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_UART2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0148) 418d198b514SPaul Walmsley #define OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150 419cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_UART3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0150) 420d198b514SPaul Walmsley #define OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158 421cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_UART4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0158) 422d198b514SPaul Walmsley #define OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET 0x0160 423cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0160) 424d198b514SPaul Walmsley #define OMAP4_CM_L4PER_I2C5_CLKCTRL_OFFSET 0x0168 425cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_I2C5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0168) 426d198b514SPaul Walmsley #define OMAP4_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180 427cdb54c44SPaul Walmsley #define OMAP4430_CM_L4SEC_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0180) 428d198b514SPaul Walmsley #define OMAP4_CM_L4SEC_STATICDEP_OFFSET 0x0184 429cdb54c44SPaul Walmsley #define OMAP4430_CM_L4SEC_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0184) 430d198b514SPaul Walmsley #define OMAP4_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188 431cdb54c44SPaul Walmsley #define OMAP4430_CM_L4SEC_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0188) 432d198b514SPaul Walmsley #define OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0 433cdb54c44SPaul Walmsley #define OMAP4430_CM_L4SEC_AES1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a0) 434d198b514SPaul Walmsley #define OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8 435cdb54c44SPaul Walmsley #define OMAP4430_CM_L4SEC_AES2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a8) 436d198b514SPaul Walmsley #define OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0 437cdb54c44SPaul Walmsley #define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01b0) 438d198b514SPaul Walmsley #define OMAP4_CM_L4SEC_PKAEIP29_CLKCTRL_OFFSET 0x01b8 439cdb54c44SPaul Walmsley #define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01b8) 440d198b514SPaul Walmsley #define OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0 441cdb54c44SPaul Walmsley #define OMAP4430_CM_L4SEC_RNG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01c0) 442d198b514SPaul Walmsley #define OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8 443cdb54c44SPaul Walmsley #define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01c8) 444d198b514SPaul Walmsley #define OMAP4_CM_L4SEC_CRYPTODMA_CLKCTRL_OFFSET 0x01d8 445cdb54c44SPaul Walmsley #define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01d8) 446d198b514SPaul Walmsley 447d198b514SPaul Walmsley /* CM2.CEFUSE_CM2 register offsets */ 448d198b514SPaul Walmsley #define OMAP4_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000 449cdb54c44SPaul Walmsley #define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0000) 450d198b514SPaul Walmsley #define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 451cdb54c44SPaul Walmsley #define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020) 452d198b514SPaul Walmsley 453d198b514SPaul Walmsley /* CM2.RESTORE_CM2 register offsets */ 454d198b514SPaul Walmsley #define OMAP4_CM_L3_1_CLKSTCTRL_RESTORE_OFFSET 0x0000 455cdb54c44SPaul Walmsley #define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0000) 456d198b514SPaul Walmsley #define OMAP4_CM_L3_2_CLKSTCTRL_RESTORE_OFFSET 0x0004 457cdb54c44SPaul Walmsley #define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0004) 458d198b514SPaul Walmsley #define OMAP4_CM_L4CFG_CLKSTCTRL_RESTORE_OFFSET 0x0008 459cdb54c44SPaul Walmsley #define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0008) 460d198b514SPaul Walmsley #define OMAP4_CM_MEMIF_CLKSTCTRL_RESTORE_OFFSET 0x000c 461cdb54c44SPaul Walmsley #define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x000c) 462d198b514SPaul Walmsley #define OMAP4_CM_L4PER_CLKSTCTRL_RESTORE_OFFSET 0x0010 463cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0010) 464d198b514SPaul Walmsley #define OMAP4_CM_L3INIT_CLKSTCTRL_RESTORE_OFFSET 0x0014 465cdb54c44SPaul Walmsley #define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0014) 466d198b514SPaul Walmsley #define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_RESTORE_OFFSET 0x0018 467cdb54c44SPaul Walmsley #define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0018) 468d198b514SPaul Walmsley #define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE_OFFSET 0x001c 469cdb54c44SPaul Walmsley #define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x001c) 470d198b514SPaul Walmsley #define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE_OFFSET 0x0020 471cdb54c44SPaul Walmsley #define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0020) 472d198b514SPaul Walmsley #define OMAP4_CM_CM2_PROFILING_CLKCTRL_RESTORE_OFFSET 0x0024 473cdb54c44SPaul Walmsley #define OMAP4430_CM_CM2_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0024) 474d198b514SPaul Walmsley #define OMAP4_CM_D2D_STATICDEP_RESTORE_OFFSET 0x0028 475cdb54c44SPaul Walmsley #define OMAP4430_CM_D2D_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0028) 476d198b514SPaul Walmsley #define OMAP4_CM_L3_1_DYNAMICDEP_RESTORE_OFFSET 0x002c 477cdb54c44SPaul Walmsley #define OMAP4430_CM_L3_1_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x002c) 478d198b514SPaul Walmsley #define OMAP4_CM_L3_2_DYNAMICDEP_RESTORE_OFFSET 0x0030 479cdb54c44SPaul Walmsley #define OMAP4430_CM_L3_2_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0030) 480d198b514SPaul Walmsley #define OMAP4_CM_D2D_DYNAMICDEP_RESTORE_OFFSET 0x0034 481cdb54c44SPaul Walmsley #define OMAP4430_CM_D2D_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0034) 482d198b514SPaul Walmsley #define OMAP4_CM_L4CFG_DYNAMICDEP_RESTORE_OFFSET 0x0038 483cdb54c44SPaul Walmsley #define OMAP4430_CM_L4CFG_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0038) 484d198b514SPaul Walmsley #define OMAP4_CM_L4PER_DYNAMICDEP_RESTORE_OFFSET 0x003c 485cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x003c) 486d198b514SPaul Walmsley #define OMAP4_CM_L4PER_GPIO2_CLKCTRL_RESTORE_OFFSET 0x0040 487cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0040) 488d198b514SPaul Walmsley #define OMAP4_CM_L4PER_GPIO3_CLKCTRL_RESTORE_OFFSET 0x0044 489cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0044) 490d198b514SPaul Walmsley #define OMAP4_CM_L4PER_GPIO4_CLKCTRL_RESTORE_OFFSET 0x0048 491cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0048) 492d198b514SPaul Walmsley #define OMAP4_CM_L4PER_GPIO5_CLKCTRL_RESTORE_OFFSET 0x004c 493cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x004c) 494d198b514SPaul Walmsley #define OMAP4_CM_L4PER_GPIO6_CLKCTRL_RESTORE_OFFSET 0x0050 495cdb54c44SPaul Walmsley #define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0050) 496d198b514SPaul Walmsley #define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE_OFFSET 0x0054 497cdb54c44SPaul Walmsley #define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0054) 498d198b514SPaul Walmsley #define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE_OFFSET 0x0058 499cdb54c44SPaul Walmsley #define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0058) 500d198b514SPaul Walmsley #define OMAP4_CM_SDMA_STATICDEP_RESTORE_OFFSET 0x005c 501cdb54c44SPaul Walmsley #define OMAP4430_CM_SDMA_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x005c) 5022ace831fSPaul Walmsley 5032ace831fSPaul Walmsley /* Function prototypes */ 5042ace831fSPaul Walmsley extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx); 5052ace831fSPaul Walmsley extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx); 5062ace831fSPaul Walmsley extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); 5072ace831fSPaul Walmsley 508d198b514SPaul Walmsley #endif 509