1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2d198b514SPaul Walmsley /* 3d198b514SPaul Walmsley * OMAP44xx CM2 instance offset macros 4d198b514SPaul Walmsley * 5ad98a18bSBenoit Cousson * Copyright (C) 2009-2011 Texas Instruments, Inc. 6d198b514SPaul Walmsley * Copyright (C) 2009-2010 Nokia Corporation 7d198b514SPaul Walmsley * 8d198b514SPaul Walmsley * Paul Walmsley (paul@pwsan.com) 9d198b514SPaul Walmsley * Rajendra Nayak (rnayak@ti.com) 10d198b514SPaul Walmsley * Benoit Cousson (b-cousson@ti.com) 11d198b514SPaul Walmsley * 12d198b514SPaul Walmsley * This file is automatically generated from the OMAP hardware databases. 13d198b514SPaul Walmsley * We respectfully ask that any modifications to this file be coordinated 14d198b514SPaul Walmsley * with the public linux-omap@vger.kernel.org mailing list and the 15d198b514SPaul Walmsley * authors above to ensure that the autogeneration scripts are kept 16d198b514SPaul Walmsley * up-to-date with the file contents. 17d198b514SPaul Walmsley * 18d198b514SPaul Walmsley * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX", 19d198b514SPaul Walmsley * or "OMAP4430". 20d198b514SPaul Walmsley */ 21d198b514SPaul Walmsley 22d198b514SPaul Walmsley #ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H 23d198b514SPaul Walmsley #define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H 24d198b514SPaul Walmsley 25d198b514SPaul Walmsley /* CM2 base address */ 26d198b514SPaul Walmsley #define OMAP4430_CM2_BASE 0x4a008000 27d198b514SPaul Walmsley 28cdb54c44SPaul Walmsley #define OMAP44XX_CM2_REGADDR(inst, reg) \ 29cdb54c44SPaul Walmsley OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (inst) + (reg)) 30d198b514SPaul Walmsley 31d198b514SPaul Walmsley /* CM2 instances */ 32cdb54c44SPaul Walmsley #define OMAP4430_CM2_OCP_SOCKET_INST 0x0000 33cdb54c44SPaul Walmsley #define OMAP4430_CM2_CKGEN_INST 0x0100 34cdb54c44SPaul Walmsley #define OMAP4430_CM2_ALWAYS_ON_INST 0x0600 35cdb54c44SPaul Walmsley #define OMAP4430_CM2_CORE_INST 0x0700 36cdb54c44SPaul Walmsley #define OMAP4430_CM2_IVAHD_INST 0x0f00 37cdb54c44SPaul Walmsley #define OMAP4430_CM2_CAM_INST 0x1000 38cdb54c44SPaul Walmsley #define OMAP4430_CM2_DSS_INST 0x1100 39cdb54c44SPaul Walmsley #define OMAP4430_CM2_GFX_INST 0x1200 40cdb54c44SPaul Walmsley #define OMAP4430_CM2_L3INIT_INST 0x1300 41cdb54c44SPaul Walmsley #define OMAP4430_CM2_L4PER_INST 0x1400 42cdb54c44SPaul Walmsley #define OMAP4430_CM2_CEFUSE_INST 0x1600 43d198b514SPaul Walmsley 44e4156ee5SPaul Walmsley /* CM2 clockdomain register offsets (from instance start) */ 45e4156ee5SPaul Walmsley #define OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS 0x0000 46e4156ee5SPaul Walmsley #define OMAP4430_CM2_CORE_L3_1_CDOFFS 0x0000 47e4156ee5SPaul Walmsley #define OMAP4430_CM2_CORE_L3_2_CDOFFS 0x0100 48e4156ee5SPaul Walmsley #define OMAP4430_CM2_CORE_DUCATI_CDOFFS 0x0200 49e4156ee5SPaul Walmsley #define OMAP4430_CM2_CORE_SDMA_CDOFFS 0x0300 50e4156ee5SPaul Walmsley #define OMAP4430_CM2_CORE_MEMIF_CDOFFS 0x0400 51e4156ee5SPaul Walmsley #define OMAP4430_CM2_CORE_D2D_CDOFFS 0x0500 52e4156ee5SPaul Walmsley #define OMAP4430_CM2_CORE_L4CFG_CDOFFS 0x0600 53e4156ee5SPaul Walmsley #define OMAP4430_CM2_CORE_L3INSTR_CDOFFS 0x0700 54e4156ee5SPaul Walmsley #define OMAP4430_CM2_IVAHD_IVAHD_CDOFFS 0x0000 55e4156ee5SPaul Walmsley #define OMAP4430_CM2_CAM_CAM_CDOFFS 0x0000 56e4156ee5SPaul Walmsley #define OMAP4430_CM2_DSS_DSS_CDOFFS 0x0000 57e4156ee5SPaul Walmsley #define OMAP4430_CM2_GFX_GFX_CDOFFS 0x0000 58e4156ee5SPaul Walmsley #define OMAP4430_CM2_L3INIT_L3INIT_CDOFFS 0x0000 59e4156ee5SPaul Walmsley #define OMAP4430_CM2_L4PER_L4PER_CDOFFS 0x0000 60e4156ee5SPaul Walmsley #define OMAP4430_CM2_L4PER_L4SEC_CDOFFS 0x0180 61e4156ee5SPaul Walmsley #define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS 0x0000 62e4156ee5SPaul Walmsley 63d198b514SPaul Walmsley #endif 64