1 /* 2 * OMAP44xx CM1 instance offset macros 3 * 4 * Copyright (C) 2009-2011 Texas Instruments, Inc. 5 * Copyright (C) 2009-2010 Nokia Corporation 6 * 7 * Paul Walmsley (paul@pwsan.com) 8 * Rajendra Nayak (rnayak@ti.com) 9 * Benoit Cousson (b-cousson@ti.com) 10 * 11 * This file is automatically generated from the OMAP hardware databases. 12 * We respectfully ask that any modifications to this file be coordinated 13 * with the public linux-omap@vger.kernel.org mailing list and the 14 * authors above to ensure that the autogeneration scripts are kept 15 * up-to-date with the file contents. 16 * 17 * This program is free software; you can redistribute it and/or modify 18 * it under the terms of the GNU General Public License version 2 as 19 * published by the Free Software Foundation. 20 * 21 * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX", 22 * or "OMAP4430". 23 */ 24 25 #ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H 26 #define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H 27 28 #include "cm_44xx_54xx.h" 29 30 /* CM1 base address */ 31 #define OMAP4430_CM1_BASE 0x4a004000 32 33 #define OMAP44XX_CM1_REGADDR(inst, reg) \ 34 OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (inst) + (reg)) 35 36 /* CM1 instances */ 37 #define OMAP4430_CM1_OCP_SOCKET_INST 0x0000 38 #define OMAP4430_CM1_CKGEN_INST 0x0100 39 #define OMAP4430_CM1_MPU_INST 0x0300 40 #define OMAP4430_CM1_TESLA_INST 0x0400 41 #define OMAP4430_CM1_ABE_INST 0x0500 42 #define OMAP4430_CM1_RESTORE_INST 0x0e00 43 #define OMAP4430_CM1_INSTR_INST 0x0f00 44 45 /* CM1 clockdomain register offsets (from instance start) */ 46 #define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000 47 #define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000 48 #define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000 49 50 /* CM1 */ 51 52 /* CM1.OCP_SOCKET_CM1 register offsets */ 53 #define OMAP4_REVISION_CM1_OFFSET 0x0000 54 #define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0000) 55 #define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET 0x0040 56 #define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0040) 57 58 /* CM1.CKGEN_CM1 register offsets */ 59 #define OMAP4_CM_CLKSEL_CORE_OFFSET 0x0000 60 #define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0000) 61 #define OMAP4_CM_CLKSEL_ABE_OFFSET 0x0008 62 #define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0008) 63 #define OMAP4_CM_DLL_CTRL_OFFSET 0x0010 64 #define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0010) 65 #define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020 66 #define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0020) 67 #define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET 0x0024 68 #define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0024) 69 #define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028 70 #define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0028) 71 #define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c 72 #define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x002c) 73 #define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030 74 #define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0030) 75 #define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034 76 #define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0034) 77 #define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET 0x0038 78 #define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0038) 79 #define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET 0x003c 80 #define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x003c) 81 #define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET 0x0040 82 #define OMAP4430_CM_DIV_M6_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0040) 83 #define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET 0x0044 84 #define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044) 85 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048 86 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048) 87 #define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c 88 #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c) 89 #define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050 90 #define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050) 91 #define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060 92 #define OMAP4430_CM_CLKMODE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0060) 93 #define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET 0x0064 94 #define OMAP4430_CM_IDLEST_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0064) 95 #define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068 96 #define OMAP4430_CM_AUTOIDLE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0068) 97 #define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c 98 #define OMAP4430_CM_CLKSEL_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x006c) 99 #define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070 100 #define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070) 101 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088 102 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088) 103 #define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c 104 #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c) 105 #define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c 106 #define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c) 107 #define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0 108 #define OMAP4430_CM_CLKMODE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a0) 109 #define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4 110 #define OMAP4430_CM_IDLEST_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a4) 111 #define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8 112 #define OMAP4430_CM_AUTOIDLE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a8) 113 #define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac 114 #define OMAP4430_CM_CLKSEL_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ac) 115 #define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET 0x00b8 116 #define OMAP4430_CM_DIV_M4_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00b8) 117 #define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET 0x00bc 118 #define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc) 119 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8 120 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8) 121 #define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc 122 #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc) 123 #define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc 124 #define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc) 125 #define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0 126 #define OMAP4430_CM_CLKMODE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e0) 127 #define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4 128 #define OMAP4430_CM_IDLEST_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e4) 129 #define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8 130 #define OMAP4430_CM_AUTOIDLE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e8) 131 #define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec 132 #define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ec) 133 #define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0 134 #define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f0) 135 #define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4 136 #define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4) 137 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108 138 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108) 139 #define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c 140 #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c) 141 #define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120 142 #define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120) 143 #define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124 144 #define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0124) 145 #define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET 0x0128 146 #define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0128) 147 #define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET 0x012c 148 #define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x012c) 149 #define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET 0x0130 150 #define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0130) 151 #define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET 0x0138 152 #define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0138) 153 #define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET 0x013c 154 #define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x013c) 155 #define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET 0x0140 156 #define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140) 157 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148 158 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148) 159 #define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET 0x014c 160 #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c) 161 #define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160 162 #define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160) 163 #define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164 164 #define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0164) 165 #define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET 0x0170 166 #define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0170) 167 #define OMAP4_CM_RESTORE_ST_OFFSET 0x0180 168 #define OMAP4430_CM_RESTORE_ST OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0180) 169 170 /* CM1.MPU_CM1 register offsets */ 171 #define OMAP4_CM_MPU_CLKSTCTRL_OFFSET 0x0000 172 #define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0000) 173 #define OMAP4_CM_MPU_STATICDEP_OFFSET 0x0004 174 #define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0004) 175 #define OMAP4_CM_MPU_DYNAMICDEP_OFFSET 0x0008 176 #define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0008) 177 #define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 178 #define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0020) 179 180 /* CM1.TESLA_CM1 register offsets */ 181 #define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET 0x0000 182 #define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0000) 183 #define OMAP4_CM_TESLA_STATICDEP_OFFSET 0x0004 184 #define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0004) 185 #define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET 0x0008 186 #define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0008) 187 #define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET 0x0020 188 #define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0020) 189 190 /* CM1.ABE_CM1 register offsets */ 191 #define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET 0x0000 192 #define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0000) 193 #define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET 0x0020 194 #define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0020) 195 #define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET 0x0028 196 #define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0028) 197 #define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET 0x0030 198 #define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0030) 199 #define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET 0x0038 200 #define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0038) 201 #define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET 0x0040 202 #define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0040) 203 #define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048 204 #define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0048) 205 #define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050 206 #define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0050) 207 #define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058 208 #define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0058) 209 #define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET 0x0060 210 #define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0060) 211 #define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET 0x0068 212 #define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0068) 213 #define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET 0x0070 214 #define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0070) 215 #define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET 0x0078 216 #define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0078) 217 #define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET 0x0080 218 #define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0080) 219 #define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088 220 #define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088) 221 222 #endif 223