1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2d198b514SPaul Walmsley /* 3d198b514SPaul Walmsley * OMAP44xx CM1 instance offset macros 4d198b514SPaul Walmsley * 5ad98a18bSBenoit Cousson * Copyright (C) 2009-2011 Texas Instruments, Inc. 6d198b514SPaul Walmsley * Copyright (C) 2009-2010 Nokia Corporation 7d198b514SPaul Walmsley * 8d198b514SPaul Walmsley * Paul Walmsley (paul@pwsan.com) 9d198b514SPaul Walmsley * Rajendra Nayak (rnayak@ti.com) 10d198b514SPaul Walmsley * Benoit Cousson (b-cousson@ti.com) 11d198b514SPaul Walmsley * 12d198b514SPaul Walmsley * This file is automatically generated from the OMAP hardware databases. 13d198b514SPaul Walmsley * We respectfully ask that any modifications to this file be coordinated 14d198b514SPaul Walmsley * with the public linux-omap@vger.kernel.org mailing list and the 15d198b514SPaul Walmsley * authors above to ensure that the autogeneration scripts are kept 16d198b514SPaul Walmsley * up-to-date with the file contents. 17d198b514SPaul Walmsley * 18d198b514SPaul Walmsley * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX", 19d198b514SPaul Walmsley * or "OMAP4430". 20d198b514SPaul Walmsley */ 21d198b514SPaul Walmsley 22d198b514SPaul Walmsley #ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H 23d198b514SPaul Walmsley #define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H 24d198b514SPaul Walmsley 25d198b514SPaul Walmsley /* CM1 base address */ 26d198b514SPaul Walmsley #define OMAP4430_CM1_BASE 0x4a004000 27d198b514SPaul Walmsley 28cdb54c44SPaul Walmsley #define OMAP44XX_CM1_REGADDR(inst, reg) \ 29cdb54c44SPaul Walmsley OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (inst) + (reg)) 30d198b514SPaul Walmsley 31d198b514SPaul Walmsley /* CM1 instances */ 32cdb54c44SPaul Walmsley #define OMAP4430_CM1_OCP_SOCKET_INST 0x0000 33cdb54c44SPaul Walmsley #define OMAP4430_CM1_CKGEN_INST 0x0100 34cdb54c44SPaul Walmsley #define OMAP4430_CM1_MPU_INST 0x0300 35cdb54c44SPaul Walmsley #define OMAP4430_CM1_TESLA_INST 0x0400 36cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_INST 0x0500 37cdb54c44SPaul Walmsley #define OMAP4430_CM1_RESTORE_INST 0x0e00 38cdb54c44SPaul Walmsley #define OMAP4430_CM1_INSTR_INST 0x0f00 39d198b514SPaul Walmsley 40e4156ee5SPaul Walmsley /* CM1 clockdomain register offsets (from instance start) */ 41e4156ee5SPaul Walmsley #define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000 42e4156ee5SPaul Walmsley #define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000 43ad98a18bSBenoit Cousson #define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000 44e4156ee5SPaul Walmsley 45d198b514SPaul Walmsley /* CM1 */ 46d198b514SPaul Walmsley 47d198b514SPaul Walmsley /* CM1.OCP_SOCKET_CM1 register offsets */ 48d198b514SPaul Walmsley #define OMAP4_REVISION_CM1_OFFSET 0x0000 49cdb54c44SPaul Walmsley #define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0000) 50d198b514SPaul Walmsley #define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET 0x0040 51cdb54c44SPaul Walmsley #define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0040) 52d198b514SPaul Walmsley 53d198b514SPaul Walmsley /* CM1.CKGEN_CM1 register offsets */ 54d198b514SPaul Walmsley #define OMAP4_CM_CLKSEL_CORE_OFFSET 0x0000 55cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0000) 56d198b514SPaul Walmsley #define OMAP4_CM_CLKSEL_ABE_OFFSET 0x0008 57cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0008) 58d198b514SPaul Walmsley #define OMAP4_CM_DLL_CTRL_OFFSET 0x0010 59cdb54c44SPaul Walmsley #define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0010) 60d198b514SPaul Walmsley #define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020 61cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0020) 62d198b514SPaul Walmsley #define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET 0x0024 63cdb54c44SPaul Walmsley #define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0024) 64d198b514SPaul Walmsley #define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028 65cdb54c44SPaul Walmsley #define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0028) 66d198b514SPaul Walmsley #define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c 67cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x002c) 68d198b514SPaul Walmsley #define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030 69cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0030) 70d198b514SPaul Walmsley #define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034 71cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0034) 72d198b514SPaul Walmsley #define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET 0x0038 73cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0038) 74d198b514SPaul Walmsley #define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET 0x003c 75cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x003c) 76d198b514SPaul Walmsley #define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET 0x0040 77cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M6_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0040) 78d198b514SPaul Walmsley #define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET 0x0044 79cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044) 80d198b514SPaul Walmsley #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048 81cdb54c44SPaul Walmsley #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048) 82ad98a18bSBenoit Cousson #define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c 83ad98a18bSBenoit Cousson #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c) 84d198b514SPaul Walmsley #define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050 85cdb54c44SPaul Walmsley #define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050) 86d198b514SPaul Walmsley #define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060 87cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKMODE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0060) 88d198b514SPaul Walmsley #define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET 0x0064 89cdb54c44SPaul Walmsley #define OMAP4430_CM_IDLEST_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0064) 90d198b514SPaul Walmsley #define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068 91cdb54c44SPaul Walmsley #define OMAP4430_CM_AUTOIDLE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0068) 92d198b514SPaul Walmsley #define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c 93cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKSEL_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x006c) 94d198b514SPaul Walmsley #define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070 95cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070) 96d198b514SPaul Walmsley #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088 97cdb54c44SPaul Walmsley #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088) 98ad98a18bSBenoit Cousson #define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c 99ad98a18bSBenoit Cousson #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c) 100d198b514SPaul Walmsley #define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c 101cdb54c44SPaul Walmsley #define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c) 102d198b514SPaul Walmsley #define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0 103cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKMODE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a0) 104d198b514SPaul Walmsley #define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4 105cdb54c44SPaul Walmsley #define OMAP4430_CM_IDLEST_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a4) 106d198b514SPaul Walmsley #define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8 107cdb54c44SPaul Walmsley #define OMAP4430_CM_AUTOIDLE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a8) 108d198b514SPaul Walmsley #define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac 109cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKSEL_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ac) 110d198b514SPaul Walmsley #define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET 0x00b8 111cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M4_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00b8) 112d198b514SPaul Walmsley #define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET 0x00bc 113cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc) 114d198b514SPaul Walmsley #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8 115cdb54c44SPaul Walmsley #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8) 116ad98a18bSBenoit Cousson #define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc 117ad98a18bSBenoit Cousson #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc) 118d198b514SPaul Walmsley #define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc 119cdb54c44SPaul Walmsley #define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc) 120d198b514SPaul Walmsley #define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0 121cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKMODE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e0) 122d198b514SPaul Walmsley #define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4 123cdb54c44SPaul Walmsley #define OMAP4430_CM_IDLEST_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e4) 124d198b514SPaul Walmsley #define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8 125cdb54c44SPaul Walmsley #define OMAP4430_CM_AUTOIDLE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e8) 126d198b514SPaul Walmsley #define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec 127cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ec) 128d198b514SPaul Walmsley #define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0 129cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f0) 130d198b514SPaul Walmsley #define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4 131cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4) 132d198b514SPaul Walmsley #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108 133cdb54c44SPaul Walmsley #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108) 134ad98a18bSBenoit Cousson #define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c 135ad98a18bSBenoit Cousson #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c) 136d198b514SPaul Walmsley #define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120 137cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120) 138d198b514SPaul Walmsley #define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124 139cdb54c44SPaul Walmsley #define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0124) 140d198b514SPaul Walmsley #define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET 0x0128 141cdb54c44SPaul Walmsley #define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0128) 142d198b514SPaul Walmsley #define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET 0x012c 143cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x012c) 144d198b514SPaul Walmsley #define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET 0x0130 145cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0130) 146d198b514SPaul Walmsley #define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET 0x0138 147cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0138) 148d198b514SPaul Walmsley #define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET 0x013c 149cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x013c) 150d198b514SPaul Walmsley #define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET 0x0140 151cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140) 152d198b514SPaul Walmsley #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148 153cdb54c44SPaul Walmsley #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148) 154ad98a18bSBenoit Cousson #define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET 0x014c 155ad98a18bSBenoit Cousson #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c) 156d198b514SPaul Walmsley #define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160 157cdb54c44SPaul Walmsley #define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160) 158d198b514SPaul Walmsley #define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164 159cdb54c44SPaul Walmsley #define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0164) 160d198b514SPaul Walmsley #define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET 0x0170 161cdb54c44SPaul Walmsley #define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0170) 162d198b514SPaul Walmsley #define OMAP4_CM_RESTORE_ST_OFFSET 0x0180 163cdb54c44SPaul Walmsley #define OMAP4430_CM_RESTORE_ST OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0180) 164d198b514SPaul Walmsley 165d198b514SPaul Walmsley /* CM1.MPU_CM1 register offsets */ 166d198b514SPaul Walmsley #define OMAP4_CM_MPU_CLKSTCTRL_OFFSET 0x0000 167cdb54c44SPaul Walmsley #define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0000) 168d198b514SPaul Walmsley #define OMAP4_CM_MPU_STATICDEP_OFFSET 0x0004 169cdb54c44SPaul Walmsley #define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0004) 170d198b514SPaul Walmsley #define OMAP4_CM_MPU_DYNAMICDEP_OFFSET 0x0008 171cdb54c44SPaul Walmsley #define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0008) 172d198b514SPaul Walmsley #define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 173cdb54c44SPaul Walmsley #define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0020) 174d198b514SPaul Walmsley 175d198b514SPaul Walmsley /* CM1.TESLA_CM1 register offsets */ 176d198b514SPaul Walmsley #define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET 0x0000 177cdb54c44SPaul Walmsley #define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0000) 178d198b514SPaul Walmsley #define OMAP4_CM_TESLA_STATICDEP_OFFSET 0x0004 179cdb54c44SPaul Walmsley #define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0004) 180d198b514SPaul Walmsley #define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET 0x0008 181cdb54c44SPaul Walmsley #define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0008) 182d198b514SPaul Walmsley #define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET 0x0020 183cdb54c44SPaul Walmsley #define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0020) 184d198b514SPaul Walmsley 185d198b514SPaul Walmsley /* CM1.ABE_CM1 register offsets */ 186d198b514SPaul Walmsley #define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET 0x0000 187cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0000) 188d198b514SPaul Walmsley #define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET 0x0020 189cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0020) 190d198b514SPaul Walmsley #define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET 0x0028 191cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0028) 192d198b514SPaul Walmsley #define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET 0x0030 193cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0030) 194d198b514SPaul Walmsley #define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET 0x0038 195cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0038) 196d198b514SPaul Walmsley #define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET 0x0040 197cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0040) 198d198b514SPaul Walmsley #define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048 199cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0048) 200d198b514SPaul Walmsley #define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050 201cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0050) 202d198b514SPaul Walmsley #define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058 203cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0058) 204d198b514SPaul Walmsley #define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET 0x0060 205cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0060) 206d198b514SPaul Walmsley #define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET 0x0068 207cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0068) 208d198b514SPaul Walmsley #define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET 0x0070 209cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0070) 210d198b514SPaul Walmsley #define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET 0x0078 211cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0078) 212d198b514SPaul Walmsley #define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET 0x0080 213cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0080) 214d198b514SPaul Walmsley #define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088 215cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088) 216d198b514SPaul Walmsley 217d198b514SPaul Walmsley #endif 218