1d198b514SPaul Walmsley /* 2d198b514SPaul Walmsley * OMAP44xx CM1 instance offset macros 3d198b514SPaul Walmsley * 4d198b514SPaul Walmsley * Copyright (C) 2009-2010 Texas Instruments, Inc. 5d198b514SPaul Walmsley * Copyright (C) 2009-2010 Nokia Corporation 6d198b514SPaul Walmsley * 7d198b514SPaul Walmsley * Paul Walmsley (paul@pwsan.com) 8d198b514SPaul Walmsley * Rajendra Nayak (rnayak@ti.com) 9d198b514SPaul Walmsley * Benoit Cousson (b-cousson@ti.com) 10d198b514SPaul Walmsley * 11d198b514SPaul Walmsley * This file is automatically generated from the OMAP hardware databases. 12d198b514SPaul Walmsley * We respectfully ask that any modifications to this file be coordinated 13d198b514SPaul Walmsley * with the public linux-omap@vger.kernel.org mailing list and the 14d198b514SPaul Walmsley * authors above to ensure that the autogeneration scripts are kept 15d198b514SPaul Walmsley * up-to-date with the file contents. 16d198b514SPaul Walmsley * 17d198b514SPaul Walmsley * This program is free software; you can redistribute it and/or modify 18d198b514SPaul Walmsley * it under the terms of the GNU General Public License version 2 as 19d198b514SPaul Walmsley * published by the Free Software Foundation. 20d198b514SPaul Walmsley * 21d198b514SPaul Walmsley * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX", 22d198b514SPaul Walmsley * or "OMAP4430". 23d198b514SPaul Walmsley */ 24d198b514SPaul Walmsley 25d198b514SPaul Walmsley #ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H 26d198b514SPaul Walmsley #define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H 27d198b514SPaul Walmsley 28d198b514SPaul Walmsley /* CM1 base address */ 29d198b514SPaul Walmsley #define OMAP4430_CM1_BASE 0x4a004000 30d198b514SPaul Walmsley 31cdb54c44SPaul Walmsley #define OMAP44XX_CM1_REGADDR(inst, reg) \ 32cdb54c44SPaul Walmsley OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (inst) + (reg)) 33d198b514SPaul Walmsley 34d198b514SPaul Walmsley /* CM1 instances */ 35cdb54c44SPaul Walmsley #define OMAP4430_CM1_OCP_SOCKET_INST 0x0000 36cdb54c44SPaul Walmsley #define OMAP4430_CM1_CKGEN_INST 0x0100 37cdb54c44SPaul Walmsley #define OMAP4430_CM1_MPU_INST 0x0300 38cdb54c44SPaul Walmsley #define OMAP4430_CM1_TESLA_INST 0x0400 39cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_INST 0x0500 40cdb54c44SPaul Walmsley #define OMAP4430_CM1_RESTORE_INST 0x0e00 41cdb54c44SPaul Walmsley #define OMAP4430_CM1_INSTR_INST 0x0f00 42d198b514SPaul Walmsley 43d198b514SPaul Walmsley /* CM1 */ 44d198b514SPaul Walmsley 45d198b514SPaul Walmsley /* CM1.OCP_SOCKET_CM1 register offsets */ 46d198b514SPaul Walmsley #define OMAP4_REVISION_CM1_OFFSET 0x0000 47cdb54c44SPaul Walmsley #define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0000) 48d198b514SPaul Walmsley #define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET 0x0040 49cdb54c44SPaul Walmsley #define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0040) 50d198b514SPaul Walmsley 51d198b514SPaul Walmsley /* CM1.CKGEN_CM1 register offsets */ 52d198b514SPaul Walmsley #define OMAP4_CM_CLKSEL_CORE_OFFSET 0x0000 53cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0000) 54d198b514SPaul Walmsley #define OMAP4_CM_CLKSEL_ABE_OFFSET 0x0008 55cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0008) 56d198b514SPaul Walmsley #define OMAP4_CM_DLL_CTRL_OFFSET 0x0010 57cdb54c44SPaul Walmsley #define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0010) 58d198b514SPaul Walmsley #define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020 59cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0020) 60d198b514SPaul Walmsley #define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET 0x0024 61cdb54c44SPaul Walmsley #define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0024) 62d198b514SPaul Walmsley #define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028 63cdb54c44SPaul Walmsley #define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0028) 64d198b514SPaul Walmsley #define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c 65cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x002c) 66d198b514SPaul Walmsley #define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030 67cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0030) 68d198b514SPaul Walmsley #define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034 69cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0034) 70d198b514SPaul Walmsley #define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET 0x0038 71cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0038) 72d198b514SPaul Walmsley #define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET 0x003c 73cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x003c) 74d198b514SPaul Walmsley #define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET 0x0040 75cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M6_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0040) 76d198b514SPaul Walmsley #define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET 0x0044 77cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044) 78d198b514SPaul Walmsley #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048 79cdb54c44SPaul Walmsley #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048) 80cdb54c44SPaul Walmsley #define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_OFFSET 0x004c 81cdb54c44SPaul Walmsley #define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c) 82d198b514SPaul Walmsley #define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050 83cdb54c44SPaul Walmsley #define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050) 84d198b514SPaul Walmsley #define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060 85cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKMODE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0060) 86d198b514SPaul Walmsley #define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET 0x0064 87cdb54c44SPaul Walmsley #define OMAP4430_CM_IDLEST_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0064) 88d198b514SPaul Walmsley #define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068 89cdb54c44SPaul Walmsley #define OMAP4430_CM_AUTOIDLE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0068) 90d198b514SPaul Walmsley #define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c 91cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKSEL_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x006c) 92d198b514SPaul Walmsley #define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070 93cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070) 94d198b514SPaul Walmsley #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088 95cdb54c44SPaul Walmsley #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088) 96cdb54c44SPaul Walmsley #define OMAP4_CM_SSC_INSTFREQDIV_DPLL_MPU_OFFSET 0x008c 97cdb54c44SPaul Walmsley #define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c) 98d198b514SPaul Walmsley #define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c 99cdb54c44SPaul Walmsley #define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c) 100d198b514SPaul Walmsley #define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0 101cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKMODE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a0) 102d198b514SPaul Walmsley #define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4 103cdb54c44SPaul Walmsley #define OMAP4430_CM_IDLEST_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a4) 104d198b514SPaul Walmsley #define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8 105cdb54c44SPaul Walmsley #define OMAP4430_CM_AUTOIDLE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a8) 106d198b514SPaul Walmsley #define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac 107cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKSEL_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ac) 108d198b514SPaul Walmsley #define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET 0x00b8 109cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M4_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00b8) 110d198b514SPaul Walmsley #define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET 0x00bc 111cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc) 112d198b514SPaul Walmsley #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8 113cdb54c44SPaul Walmsley #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8) 114cdb54c44SPaul Walmsley #define OMAP4_CM_SSC_INSTFREQDIV_DPLL_IVA_OFFSET 0x00cc 115cdb54c44SPaul Walmsley #define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc) 116d198b514SPaul Walmsley #define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc 117cdb54c44SPaul Walmsley #define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc) 118d198b514SPaul Walmsley #define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0 119cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKMODE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e0) 120d198b514SPaul Walmsley #define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4 121cdb54c44SPaul Walmsley #define OMAP4430_CM_IDLEST_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e4) 122d198b514SPaul Walmsley #define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8 123cdb54c44SPaul Walmsley #define OMAP4430_CM_AUTOIDLE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e8) 124d198b514SPaul Walmsley #define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec 125cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ec) 126d198b514SPaul Walmsley #define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0 127cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f0) 128d198b514SPaul Walmsley #define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4 129cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4) 130d198b514SPaul Walmsley #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108 131cdb54c44SPaul Walmsley #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108) 132cdb54c44SPaul Walmsley #define OMAP4_CM_SSC_INSTFREQDIV_DPLL_ABE_OFFSET 0x010c 133cdb54c44SPaul Walmsley #define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c) 134d198b514SPaul Walmsley #define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120 135cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120) 136d198b514SPaul Walmsley #define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124 137cdb54c44SPaul Walmsley #define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0124) 138d198b514SPaul Walmsley #define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET 0x0128 139cdb54c44SPaul Walmsley #define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0128) 140d198b514SPaul Walmsley #define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET 0x012c 141cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x012c) 142d198b514SPaul Walmsley #define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET 0x0130 143cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0130) 144d198b514SPaul Walmsley #define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET 0x0138 145cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0138) 146d198b514SPaul Walmsley #define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET 0x013c 147cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x013c) 148d198b514SPaul Walmsley #define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET 0x0140 149cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140) 150d198b514SPaul Walmsley #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148 151cdb54c44SPaul Walmsley #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148) 152cdb54c44SPaul Walmsley #define OMAP4_CM_SSC_INSTFREQDIV_DPLL_DDRPHY_OFFSET 0x014c 153cdb54c44SPaul Walmsley #define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c) 154d198b514SPaul Walmsley #define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160 155cdb54c44SPaul Walmsley #define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160) 156d198b514SPaul Walmsley #define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164 157cdb54c44SPaul Walmsley #define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0164) 158d198b514SPaul Walmsley #define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET 0x0170 159cdb54c44SPaul Walmsley #define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0170) 160d198b514SPaul Walmsley #define OMAP4_CM_RESTORE_ST_OFFSET 0x0180 161cdb54c44SPaul Walmsley #define OMAP4430_CM_RESTORE_ST OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0180) 162d198b514SPaul Walmsley 163d198b514SPaul Walmsley /* CM1.MPU_CM1 register offsets */ 164d198b514SPaul Walmsley #define OMAP4_CM_MPU_CLKSTCTRL_OFFSET 0x0000 165cdb54c44SPaul Walmsley #define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0000) 166d198b514SPaul Walmsley #define OMAP4_CM_MPU_STATICDEP_OFFSET 0x0004 167cdb54c44SPaul Walmsley #define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0004) 168d198b514SPaul Walmsley #define OMAP4_CM_MPU_DYNAMICDEP_OFFSET 0x0008 169cdb54c44SPaul Walmsley #define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0008) 170d198b514SPaul Walmsley #define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 171cdb54c44SPaul Walmsley #define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0020) 172d198b514SPaul Walmsley 173d198b514SPaul Walmsley /* CM1.TESLA_CM1 register offsets */ 174d198b514SPaul Walmsley #define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET 0x0000 175cdb54c44SPaul Walmsley #define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0000) 176d198b514SPaul Walmsley #define OMAP4_CM_TESLA_STATICDEP_OFFSET 0x0004 177cdb54c44SPaul Walmsley #define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0004) 178d198b514SPaul Walmsley #define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET 0x0008 179cdb54c44SPaul Walmsley #define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0008) 180d198b514SPaul Walmsley #define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET 0x0020 181cdb54c44SPaul Walmsley #define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0020) 182d198b514SPaul Walmsley 183d198b514SPaul Walmsley /* CM1.ABE_CM1 register offsets */ 184d198b514SPaul Walmsley #define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET 0x0000 185cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0000) 186d198b514SPaul Walmsley #define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET 0x0020 187cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0020) 188d198b514SPaul Walmsley #define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET 0x0028 189cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0028) 190d198b514SPaul Walmsley #define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET 0x0030 191cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0030) 192d198b514SPaul Walmsley #define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET 0x0038 193cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0038) 194d198b514SPaul Walmsley #define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET 0x0040 195cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0040) 196d198b514SPaul Walmsley #define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048 197cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0048) 198d198b514SPaul Walmsley #define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050 199cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0050) 200d198b514SPaul Walmsley #define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058 201cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0058) 202d198b514SPaul Walmsley #define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET 0x0060 203cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0060) 204d198b514SPaul Walmsley #define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET 0x0068 205cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0068) 206d198b514SPaul Walmsley #define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET 0x0070 207cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0070) 208d198b514SPaul Walmsley #define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET 0x0078 209cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0078) 210d198b514SPaul Walmsley #define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET 0x0080 211cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0080) 212d198b514SPaul Walmsley #define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088 213cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088) 214d198b514SPaul Walmsley 215d198b514SPaul Walmsley /* CM1.RESTORE_CM1 register offsets */ 216d198b514SPaul Walmsley #define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET 0x0000 217cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKSEL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0000) 218d198b514SPaul Walmsley #define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET 0x0004 219cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0004) 220d198b514SPaul Walmsley #define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET 0x0008 221cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0008) 222d198b514SPaul Walmsley #define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET 0x000c 223cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x000c) 224d198b514SPaul Walmsley #define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET 0x0010 225cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0010) 226d198b514SPaul Walmsley #define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET 0x0014 227cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0014) 228d198b514SPaul Walmsley #define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET 0x0018 229cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0018) 230d198b514SPaul Walmsley #define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET 0x001c 231cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x001c) 232d198b514SPaul Walmsley #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET 0x0020 233cdb54c44SPaul Walmsley #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0020) 234cdb54c44SPaul Walmsley #define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE_OFFSET 0x0024 235cdb54c44SPaul Walmsley #define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0024) 236d198b514SPaul Walmsley #define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET 0x0028 237cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0028) 238d198b514SPaul Walmsley #define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET 0x002c 239cdb54c44SPaul Walmsley #define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x002c) 240d198b514SPaul Walmsley #define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET 0x0030 241cdb54c44SPaul Walmsley #define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0030) 242d198b514SPaul Walmsley #define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET 0x0034 243cdb54c44SPaul Walmsley #define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0034) 244d198b514SPaul Walmsley #define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET 0x0038 245cdb54c44SPaul Walmsley #define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0038) 246d198b514SPaul Walmsley #define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET 0x003c 247cdb54c44SPaul Walmsley #define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x003c) 248d198b514SPaul Walmsley #define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET 0x0040 249cdb54c44SPaul Walmsley #define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0040) 250d198b514SPaul Walmsley 251d198b514SPaul Walmsley #endif 252