1d198b514SPaul Walmsley /* 2d198b514SPaul Walmsley * OMAP44xx CM1 instance offset macros 3d198b514SPaul Walmsley * 4ad98a18bSBenoit Cousson * Copyright (C) 2009-2011 Texas Instruments, Inc. 5d198b514SPaul Walmsley * Copyright (C) 2009-2010 Nokia Corporation 6d198b514SPaul Walmsley * 7d198b514SPaul Walmsley * Paul Walmsley (paul@pwsan.com) 8d198b514SPaul Walmsley * Rajendra Nayak (rnayak@ti.com) 9d198b514SPaul Walmsley * Benoit Cousson (b-cousson@ti.com) 10d198b514SPaul Walmsley * 11d198b514SPaul Walmsley * This file is automatically generated from the OMAP hardware databases. 12d198b514SPaul Walmsley * We respectfully ask that any modifications to this file be coordinated 13d198b514SPaul Walmsley * with the public linux-omap@vger.kernel.org mailing list and the 14d198b514SPaul Walmsley * authors above to ensure that the autogeneration scripts are kept 15d198b514SPaul Walmsley * up-to-date with the file contents. 16d198b514SPaul Walmsley * 17d198b514SPaul Walmsley * This program is free software; you can redistribute it and/or modify 18d198b514SPaul Walmsley * it under the terms of the GNU General Public License version 2 as 19d198b514SPaul Walmsley * published by the Free Software Foundation. 20d198b514SPaul Walmsley * 21d198b514SPaul Walmsley * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX", 22d198b514SPaul Walmsley * or "OMAP4430". 23d198b514SPaul Walmsley */ 24d198b514SPaul Walmsley 25d198b514SPaul Walmsley #ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H 26d198b514SPaul Walmsley #define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H 27d198b514SPaul Walmsley 28d198b514SPaul Walmsley /* CM1 base address */ 29d198b514SPaul Walmsley #define OMAP4430_CM1_BASE 0x4a004000 30d198b514SPaul Walmsley 31cdb54c44SPaul Walmsley #define OMAP44XX_CM1_REGADDR(inst, reg) \ 32cdb54c44SPaul Walmsley OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (inst) + (reg)) 33d198b514SPaul Walmsley 34d198b514SPaul Walmsley /* CM1 instances */ 35cdb54c44SPaul Walmsley #define OMAP4430_CM1_OCP_SOCKET_INST 0x0000 36cdb54c44SPaul Walmsley #define OMAP4430_CM1_CKGEN_INST 0x0100 37cdb54c44SPaul Walmsley #define OMAP4430_CM1_MPU_INST 0x0300 38cdb54c44SPaul Walmsley #define OMAP4430_CM1_TESLA_INST 0x0400 39cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_INST 0x0500 40cdb54c44SPaul Walmsley #define OMAP4430_CM1_RESTORE_INST 0x0e00 41cdb54c44SPaul Walmsley #define OMAP4430_CM1_INSTR_INST 0x0f00 42d198b514SPaul Walmsley 43e4156ee5SPaul Walmsley /* CM1 clockdomain register offsets (from instance start) */ 44e4156ee5SPaul Walmsley #define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000 45e4156ee5SPaul Walmsley #define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000 46ad98a18bSBenoit Cousson #define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000 47e4156ee5SPaul Walmsley 48d198b514SPaul Walmsley /* CM1 */ 49d198b514SPaul Walmsley 50d198b514SPaul Walmsley /* CM1.OCP_SOCKET_CM1 register offsets */ 51d198b514SPaul Walmsley #define OMAP4_REVISION_CM1_OFFSET 0x0000 52cdb54c44SPaul Walmsley #define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0000) 53d198b514SPaul Walmsley #define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET 0x0040 54cdb54c44SPaul Walmsley #define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0040) 55d198b514SPaul Walmsley 56d198b514SPaul Walmsley /* CM1.CKGEN_CM1 register offsets */ 57d198b514SPaul Walmsley #define OMAP4_CM_CLKSEL_CORE_OFFSET 0x0000 58cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0000) 59d198b514SPaul Walmsley #define OMAP4_CM_CLKSEL_ABE_OFFSET 0x0008 60cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0008) 61d198b514SPaul Walmsley #define OMAP4_CM_DLL_CTRL_OFFSET 0x0010 62cdb54c44SPaul Walmsley #define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0010) 63d198b514SPaul Walmsley #define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020 64cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0020) 65d198b514SPaul Walmsley #define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET 0x0024 66cdb54c44SPaul Walmsley #define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0024) 67d198b514SPaul Walmsley #define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028 68cdb54c44SPaul Walmsley #define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0028) 69d198b514SPaul Walmsley #define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c 70cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x002c) 71d198b514SPaul Walmsley #define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030 72cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0030) 73d198b514SPaul Walmsley #define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034 74cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0034) 75d198b514SPaul Walmsley #define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET 0x0038 76cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0038) 77d198b514SPaul Walmsley #define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET 0x003c 78cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x003c) 79d198b514SPaul Walmsley #define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET 0x0040 80cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M6_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0040) 81d198b514SPaul Walmsley #define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET 0x0044 82cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044) 83d198b514SPaul Walmsley #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048 84cdb54c44SPaul Walmsley #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048) 85ad98a18bSBenoit Cousson #define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c 86ad98a18bSBenoit Cousson #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c) 87d198b514SPaul Walmsley #define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050 88cdb54c44SPaul Walmsley #define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050) 89d198b514SPaul Walmsley #define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060 90cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKMODE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0060) 91d198b514SPaul Walmsley #define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET 0x0064 92cdb54c44SPaul Walmsley #define OMAP4430_CM_IDLEST_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0064) 93d198b514SPaul Walmsley #define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068 94cdb54c44SPaul Walmsley #define OMAP4430_CM_AUTOIDLE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0068) 95d198b514SPaul Walmsley #define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c 96cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKSEL_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x006c) 97d198b514SPaul Walmsley #define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070 98cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070) 99d198b514SPaul Walmsley #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088 100cdb54c44SPaul Walmsley #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088) 101ad98a18bSBenoit Cousson #define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c 102ad98a18bSBenoit Cousson #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c) 103d198b514SPaul Walmsley #define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c 104cdb54c44SPaul Walmsley #define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c) 105d198b514SPaul Walmsley #define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0 106cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKMODE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a0) 107d198b514SPaul Walmsley #define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4 108cdb54c44SPaul Walmsley #define OMAP4430_CM_IDLEST_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a4) 109d198b514SPaul Walmsley #define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8 110cdb54c44SPaul Walmsley #define OMAP4430_CM_AUTOIDLE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a8) 111d198b514SPaul Walmsley #define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac 112cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKSEL_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ac) 113d198b514SPaul Walmsley #define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET 0x00b8 114cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M4_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00b8) 115d198b514SPaul Walmsley #define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET 0x00bc 116cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc) 117d198b514SPaul Walmsley #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8 118cdb54c44SPaul Walmsley #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8) 119ad98a18bSBenoit Cousson #define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc 120ad98a18bSBenoit Cousson #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc) 121d198b514SPaul Walmsley #define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc 122cdb54c44SPaul Walmsley #define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc) 123d198b514SPaul Walmsley #define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0 124cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKMODE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e0) 125d198b514SPaul Walmsley #define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4 126cdb54c44SPaul Walmsley #define OMAP4430_CM_IDLEST_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e4) 127d198b514SPaul Walmsley #define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8 128cdb54c44SPaul Walmsley #define OMAP4430_CM_AUTOIDLE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e8) 129d198b514SPaul Walmsley #define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec 130cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ec) 131d198b514SPaul Walmsley #define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0 132cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f0) 133d198b514SPaul Walmsley #define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4 134cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4) 135d198b514SPaul Walmsley #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108 136cdb54c44SPaul Walmsley #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108) 137ad98a18bSBenoit Cousson #define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c 138ad98a18bSBenoit Cousson #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c) 139d198b514SPaul Walmsley #define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120 140cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120) 141d198b514SPaul Walmsley #define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124 142cdb54c44SPaul Walmsley #define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0124) 143d198b514SPaul Walmsley #define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET 0x0128 144cdb54c44SPaul Walmsley #define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0128) 145d198b514SPaul Walmsley #define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET 0x012c 146cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x012c) 147d198b514SPaul Walmsley #define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET 0x0130 148cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0130) 149d198b514SPaul Walmsley #define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET 0x0138 150cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0138) 151d198b514SPaul Walmsley #define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET 0x013c 152cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x013c) 153d198b514SPaul Walmsley #define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET 0x0140 154cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140) 155d198b514SPaul Walmsley #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148 156cdb54c44SPaul Walmsley #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148) 157ad98a18bSBenoit Cousson #define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET 0x014c 158ad98a18bSBenoit Cousson #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c) 159d198b514SPaul Walmsley #define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160 160cdb54c44SPaul Walmsley #define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160) 161d198b514SPaul Walmsley #define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164 162cdb54c44SPaul Walmsley #define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0164) 163d198b514SPaul Walmsley #define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET 0x0170 164cdb54c44SPaul Walmsley #define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0170) 165d198b514SPaul Walmsley #define OMAP4_CM_RESTORE_ST_OFFSET 0x0180 166cdb54c44SPaul Walmsley #define OMAP4430_CM_RESTORE_ST OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0180) 167d198b514SPaul Walmsley 168d198b514SPaul Walmsley /* CM1.MPU_CM1 register offsets */ 169d198b514SPaul Walmsley #define OMAP4_CM_MPU_CLKSTCTRL_OFFSET 0x0000 170cdb54c44SPaul Walmsley #define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0000) 171d198b514SPaul Walmsley #define OMAP4_CM_MPU_STATICDEP_OFFSET 0x0004 172cdb54c44SPaul Walmsley #define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0004) 173d198b514SPaul Walmsley #define OMAP4_CM_MPU_DYNAMICDEP_OFFSET 0x0008 174cdb54c44SPaul Walmsley #define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0008) 175d198b514SPaul Walmsley #define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 176cdb54c44SPaul Walmsley #define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0020) 177d198b514SPaul Walmsley 178d198b514SPaul Walmsley /* CM1.TESLA_CM1 register offsets */ 179d198b514SPaul Walmsley #define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET 0x0000 180cdb54c44SPaul Walmsley #define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0000) 181d198b514SPaul Walmsley #define OMAP4_CM_TESLA_STATICDEP_OFFSET 0x0004 182cdb54c44SPaul Walmsley #define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0004) 183d198b514SPaul Walmsley #define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET 0x0008 184cdb54c44SPaul Walmsley #define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0008) 185d198b514SPaul Walmsley #define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET 0x0020 186cdb54c44SPaul Walmsley #define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0020) 187d198b514SPaul Walmsley 188d198b514SPaul Walmsley /* CM1.ABE_CM1 register offsets */ 189d198b514SPaul Walmsley #define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET 0x0000 190cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0000) 191d198b514SPaul Walmsley #define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET 0x0020 192cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0020) 193d198b514SPaul Walmsley #define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET 0x0028 194cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0028) 195d198b514SPaul Walmsley #define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET 0x0030 196cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0030) 197d198b514SPaul Walmsley #define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET 0x0038 198cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0038) 199d198b514SPaul Walmsley #define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET 0x0040 200cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0040) 201d198b514SPaul Walmsley #define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048 202cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0048) 203d198b514SPaul Walmsley #define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050 204cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0050) 205d198b514SPaul Walmsley #define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058 206cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0058) 207d198b514SPaul Walmsley #define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET 0x0060 208cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0060) 209d198b514SPaul Walmsley #define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET 0x0068 210cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0068) 211d198b514SPaul Walmsley #define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET 0x0070 212cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0070) 213d198b514SPaul Walmsley #define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET 0x0078 214cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0078) 215d198b514SPaul Walmsley #define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET 0x0080 216cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0080) 217d198b514SPaul Walmsley #define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088 218cdb54c44SPaul Walmsley #define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088) 219d198b514SPaul Walmsley 220d198b514SPaul Walmsley /* CM1.RESTORE_CM1 register offsets */ 221d198b514SPaul Walmsley #define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET 0x0000 222cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKSEL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0000) 223d198b514SPaul Walmsley #define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET 0x0004 224cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0004) 225d198b514SPaul Walmsley #define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET 0x0008 226cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0008) 227d198b514SPaul Walmsley #define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET 0x000c 228cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x000c) 229d198b514SPaul Walmsley #define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET 0x0010 230cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0010) 231d198b514SPaul Walmsley #define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET 0x0014 232cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0014) 233d198b514SPaul Walmsley #define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET 0x0018 234cdb54c44SPaul Walmsley #define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0018) 235d198b514SPaul Walmsley #define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET 0x001c 236cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x001c) 237d198b514SPaul Walmsley #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET 0x0020 238cdb54c44SPaul Walmsley #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0020) 239cdb54c44SPaul Walmsley #define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE_OFFSET 0x0024 240cdb54c44SPaul Walmsley #define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0024) 241d198b514SPaul Walmsley #define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET 0x0028 242cdb54c44SPaul Walmsley #define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0028) 243d198b514SPaul Walmsley #define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET 0x002c 244cdb54c44SPaul Walmsley #define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x002c) 245d198b514SPaul Walmsley #define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET 0x0030 246cdb54c44SPaul Walmsley #define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0030) 247d198b514SPaul Walmsley #define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET 0x0034 248cdb54c44SPaul Walmsley #define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0034) 249d198b514SPaul Walmsley #define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET 0x0038 250cdb54c44SPaul Walmsley #define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0038) 251d198b514SPaul Walmsley #define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET 0x003c 252cdb54c44SPaul Walmsley #define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x003c) 253d198b514SPaul Walmsley #define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET 0x0040 254cdb54c44SPaul Walmsley #define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0040) 255d198b514SPaul Walmsley 2562ace831fSPaul Walmsley /* Function prototypes */ 2572ace831fSPaul Walmsley extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx); 2582ace831fSPaul Walmsley extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx); 2592ace831fSPaul Walmsley extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); 2602ace831fSPaul Walmsley 261d198b514SPaul Walmsley #endif 262