1 #ifndef __ARCH_ASM_MACH_OMAP2_CM_H 2 #define __ARCH_ASM_MACH_OMAP2_CM_H 3 4 /* 5 * OMAP2/3 Clock Management (CM) register definitions 6 * 7 * Copyright (C) 2007-2009 Texas Instruments, Inc. 8 * Copyright (C) 2007-2009 Nokia Corporation 9 * 10 * Written by Paul Walmsley 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License version 2 as 14 * published by the Free Software Foundation. 15 */ 16 17 #include "prcm-common.h" 18 19 #define OMAP2420_CM_REGADDR(module, reg) \ 20 OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg)) 21 #define OMAP2430_CM_REGADDR(module, reg) \ 22 OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) 23 #define OMAP34XX_CM_REGADDR(module, reg) \ 24 OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) 25 #define OMAP44XX_CM1_REGADDR(module, reg) \ 26 OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (module) + (reg)) 27 #define OMAP44XX_CM2_REGADDR(module, reg) \ 28 OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (module) + (reg)) 29 30 #include "cm44xx.h" 31 32 /* 33 * Architecture-specific global CM registers 34 * Use cm_{read,write}_reg() with these registers. 35 * These registers appear once per CM module. 36 */ 37 38 #define OMAP3430_CM_REVISION OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000) 39 #define OMAP3430_CM_SYSCONFIG OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010) 40 #define OMAP3430_CM_POLCTRL OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c) 41 42 #define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070 43 #define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070) 44 45 /* 46 * Module specific CM registers from CM_BASE + domain offset 47 * Use cm_{read,write}_mod_reg() with these registers. 48 * These register offsets generally appear in more than one PRCM submodule. 49 */ 50 51 /* Common between 24xx and 34xx */ 52 53 #define CM_FCLKEN 0x0000 54 #define CM_FCLKEN1 CM_FCLKEN 55 #define CM_CLKEN CM_FCLKEN 56 #define CM_ICLKEN 0x0010 57 #define CM_ICLKEN1 CM_ICLKEN 58 #define CM_ICLKEN2 0x0014 59 #define CM_ICLKEN3 0x0018 60 #define CM_IDLEST 0x0020 61 #define CM_IDLEST1 CM_IDLEST 62 #define CM_IDLEST2 0x0024 63 #define CM_AUTOIDLE 0x0030 64 #define CM_AUTOIDLE1 CM_AUTOIDLE 65 #define CM_AUTOIDLE2 0x0034 66 #define CM_AUTOIDLE3 0x0038 67 #define CM_CLKSEL 0x0040 68 #define CM_CLKSEL1 CM_CLKSEL 69 #define CM_CLKSEL2 0x0044 70 #define OMAP2_CM_CLKSTCTRL 0x0048 71 #define OMAP4_CM_CLKSTCTRL 0x0000 72 73 74 /* Architecture-specific registers */ 75 76 #define OMAP24XX_CM_FCLKEN2 0x0004 77 #define OMAP24XX_CM_ICLKEN4 0x001c 78 #define OMAP24XX_CM_AUTOIDLE4 0x003c 79 80 #define OMAP2430_CM_IDLEST3 0x0028 81 82 #define OMAP3430_CM_CLKEN_PLL 0x0004 83 #define OMAP3430ES2_CM_CLKEN2 0x0004 84 #define OMAP3430ES2_CM_FCLKEN3 0x0008 85 #define OMAP3430_CM_IDLEST_PLL CM_IDLEST2 86 #define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2 87 #define OMAP3430ES2_CM_AUTOIDLE2_PLL CM_AUTOIDLE2 88 #define OMAP3430_CM_CLKSEL1 CM_CLKSEL 89 #define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL 90 #define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2 91 #define OMAP3430_CM_SLEEPDEP CM_CLKSEL2 92 #define OMAP3430_CM_CLKSEL3 OMAP2_CM_CLKSTCTRL 93 #define OMAP3430_CM_CLKSTST 0x004c 94 #define OMAP3430ES2_CM_CLKSEL4 0x004c 95 #define OMAP3430ES2_CM_CLKSEL5 0x0050 96 #define OMAP3430_CM_CLKSEL2_EMU 0x0050 97 #define OMAP3430_CM_CLKSEL3_EMU 0x0054 98 99 /* CM2.CEFUSE_CM2 register offsets */ 100 101 /* OMAP4 modulemode control */ 102 #define OMAP4430_MODULEMODE_HWCTRL 0 103 #define OMAP4430_MODULEMODE_SWCTRL 1 104 105 /* Clock management domain register get/set */ 106 107 #ifndef __ASSEMBLER__ 108 109 extern u32 cm_read_mod_reg(s16 module, u16 idx); 110 extern void cm_write_mod_reg(u32 val, s16 module, u16 idx); 111 extern u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); 112 113 extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, 114 u8 idlest_shift); 115 extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg); 116 117 static inline u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) 118 { 119 return cm_rmw_mod_reg_bits(bits, bits, module, idx); 120 } 121 122 static inline u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) 123 { 124 return cm_rmw_mod_reg_bits(bits, 0x0, module, idx); 125 } 126 127 #endif 128 129 /* CM register bits shared between 24XX and 3430 */ 130 131 /* CM_CLKSEL_GFX */ 132 #define OMAP_CLKSEL_GFX_SHIFT 0 133 #define OMAP_CLKSEL_GFX_MASK (0x7 << 0) 134 135 /* CM_ICLKEN_GFX */ 136 #define OMAP_EN_GFX_SHIFT 0 137 #define OMAP_EN_GFX_MASK (1 << 0) 138 139 /* CM_IDLEST_GFX */ 140 #define OMAP_ST_GFX_MASK (1 << 0) 141 142 143 /* CM_IDLEST indicator */ 144 #define OMAP24XX_CM_IDLEST_VAL 0 145 #define OMAP34XX_CM_IDLEST_VAL 1 146 147 /* 148 * MAX_MODULE_READY_TIME: max duration in microseconds to wait for the 149 * PRCM to request that a module exit the inactive state in the case of 150 * OMAP2 & 3. 151 * In the case of OMAP4 this is the max duration in microseconds for the 152 * module to reach the functionnal state from an inactive state. 153 */ 154 #define MAX_MODULE_READY_TIME 2000 155 156 #endif 157