1 #ifndef __ARCH_ASM_MACH_OMAP2_CM_H 2 #define __ARCH_ASM_MACH_OMAP2_CM_H 3 4 /* 5 * OMAP2/3 Clock Management (CM) register definitions 6 * 7 * Copyright (C) 2007-2008 Texas Instruments, Inc. 8 * Copyright (C) 2007-2008 Nokia Corporation 9 * 10 * Written by Paul Walmsley 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License version 2 as 14 * published by the Free Software Foundation. 15 */ 16 17 #include "prcm-common.h" 18 19 #ifndef __ASSEMBLER__ 20 #define OMAP_CM_REGADDR(module, reg) \ 21 (void __iomem *)IO_ADDRESS(OMAP2_CM_BASE + (module) + (reg)) 22 #else 23 #define OMAP2420_CM_REGADDR(module, reg) \ 24 IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg)) 25 #define OMAP2430_CM_REGADDR(module, reg) \ 26 IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) 27 #define OMAP34XX_CM_REGADDR(module, reg) \ 28 IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) 29 #endif 30 31 /* 32 * Architecture-specific global CM registers 33 * Use cm_{read,write}_reg() with these registers. 34 * These registers appear once per CM module. 35 */ 36 37 #define OMAP3430_CM_REVISION OMAP_CM_REGADDR(OCP_MOD, 0x0000) 38 #define OMAP3430_CM_SYSCONFIG OMAP_CM_REGADDR(OCP_MOD, 0x0010) 39 #define OMAP3430_CM_POLCTRL OMAP_CM_REGADDR(OCP_MOD, 0x009c) 40 41 #define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070) 42 43 /* 44 * Module specific CM registers from CM_BASE + domain offset 45 * Use cm_{read,write}_mod_reg() with these registers. 46 * These register offsets generally appear in more than one PRCM submodule. 47 */ 48 49 /* Common between 24xx and 34xx */ 50 51 #define CM_FCLKEN 0x0000 52 #define CM_FCLKEN1 CM_FCLKEN 53 #define CM_CLKEN CM_FCLKEN 54 #define CM_ICLKEN 0x0010 55 #define CM_ICLKEN1 CM_ICLKEN 56 #define CM_ICLKEN2 0x0014 57 #define CM_ICLKEN3 0x0018 58 #define CM_IDLEST 0x0020 59 #define CM_IDLEST1 CM_IDLEST 60 #define CM_IDLEST2 0x0024 61 #define CM_AUTOIDLE 0x0030 62 #define CM_AUTOIDLE1 CM_AUTOIDLE 63 #define CM_AUTOIDLE2 0x0034 64 #define CM_AUTOIDLE3 0x0038 65 #define CM_CLKSEL 0x0040 66 #define CM_CLKSEL1 CM_CLKSEL 67 #define CM_CLKSEL2 0x0044 68 #define CM_CLKSTCTRL 0x0048 69 70 71 /* Architecture-specific registers */ 72 73 #define OMAP24XX_CM_FCLKEN2 0x0004 74 #define OMAP24XX_CM_ICLKEN4 0x001c 75 #define OMAP24XX_CM_AUTOIDLE4 0x003c 76 77 #define OMAP2430_CM_IDLEST3 0x0028 78 79 #define OMAP3430_CM_CLKEN_PLL 0x0004 80 #define OMAP3430ES2_CM_CLKEN2 0x0004 81 #define OMAP3430ES2_CM_FCLKEN3 0x0008 82 #define OMAP3430_CM_IDLEST_PLL CM_IDLEST2 83 #define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2 84 #define OMAP3430_CM_CLKSEL1 CM_CLKSEL 85 #define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL 86 #define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2 87 #define OMAP3430_CM_SLEEPDEP CM_CLKSEL2 88 #define OMAP3430_CM_CLKSEL3 CM_CLKSTCTRL 89 #define OMAP3430_CM_CLKSTST 0x004c 90 #define OMAP3430ES2_CM_CLKSEL4 0x004c 91 #define OMAP3430ES2_CM_CLKSEL5 0x0050 92 #define OMAP3430_CM_CLKSEL2_EMU 0x0050 93 #define OMAP3430_CM_CLKSEL3_EMU 0x0054 94 95 96 /* Clock management domain register get/set */ 97 98 #ifndef __ASSEMBLER__ 99 static inline void cm_write_mod_reg(u32 val, s16 module, s16 idx) 100 { 101 __raw_writel(val, OMAP_CM_REGADDR(module, idx)); 102 } 103 104 static inline u32 cm_read_mod_reg(s16 module, s16 idx) 105 { 106 return __raw_readl(OMAP_CM_REGADDR(module, idx)); 107 } 108 #endif 109 110 /* CM register bits shared between 24XX and 3430 */ 111 112 /* CM_CLKSEL_GFX */ 113 #define OMAP_CLKSEL_GFX_SHIFT 0 114 #define OMAP_CLKSEL_GFX_MASK (0x7 << 0) 115 116 /* CM_ICLKEN_GFX */ 117 #define OMAP_EN_GFX_SHIFT 0 118 #define OMAP_EN_GFX (1 << 0) 119 120 /* CM_IDLEST_GFX */ 121 #define OMAP_ST_GFX (1 << 0) 122 123 124 #endif 125