1dfab439fSBenoit Cousson /* 2dfab439fSBenoit Cousson * OMAP54xx Clock Management register bits 3dfab439fSBenoit Cousson * 4dfab439fSBenoit Cousson * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com 5dfab439fSBenoit Cousson * 6dfab439fSBenoit Cousson * Paul Walmsley (paul@pwsan.com) 7dfab439fSBenoit Cousson * Rajendra Nayak (rnayak@ti.com) 8dfab439fSBenoit Cousson * Benoit Cousson (b-cousson@ti.com) 9dfab439fSBenoit Cousson * 10dfab439fSBenoit Cousson * This file is automatically generated from the OMAP hardware databases. 11dfab439fSBenoit Cousson * We respectfully ask that any modifications to this file be coordinated 12dfab439fSBenoit Cousson * with the public linux-omap@vger.kernel.org mailing list and the 13dfab439fSBenoit Cousson * authors above to ensure that the autogeneration scripts are kept 14dfab439fSBenoit Cousson * up-to-date with the file contents. 15dfab439fSBenoit Cousson * 16dfab439fSBenoit Cousson * This program is free software; you can redistribute it and/or modify 17dfab439fSBenoit Cousson * it under the terms of the GNU General Public License version 2 as 18dfab439fSBenoit Cousson * published by the Free Software Foundation. 19dfab439fSBenoit Cousson */ 20dfab439fSBenoit Cousson 21dfab439fSBenoit Cousson #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H 22dfab439fSBenoit Cousson #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H 23dfab439fSBenoit Cousson 24dfab439fSBenoit Cousson /* Used by CM_DSP_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_MPU_DYNAMICDEP */ 25dfab439fSBenoit Cousson #define OMAP54XX_ABE_DYNDEP_SHIFT 3 26dfab439fSBenoit Cousson #define OMAP54XX_ABE_DYNDEP_WIDTH 0x1 27dfab439fSBenoit Cousson #define OMAP54XX_ABE_DYNDEP_MASK (1 << 3) 28dfab439fSBenoit Cousson 29dfab439fSBenoit Cousson /* 30dfab439fSBenoit Cousson * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP, 31dfab439fSBenoit Cousson * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP 32dfab439fSBenoit Cousson */ 33dfab439fSBenoit Cousson #define OMAP54XX_ABE_STATDEP_SHIFT 3 34dfab439fSBenoit Cousson #define OMAP54XX_ABE_STATDEP_WIDTH 0x1 35dfab439fSBenoit Cousson #define OMAP54XX_ABE_STATDEP_MASK (1 << 3) 36dfab439fSBenoit Cousson 37dfab439fSBenoit Cousson /* 38dfab439fSBenoit Cousson * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_IVA, 39dfab439fSBenoit Cousson * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO1, 40dfab439fSBenoit Cousson * CM_AUTOIDLE_DPLL_UNIPRO2, CM_AUTOIDLE_DPLL_USB 41dfab439fSBenoit Cousson */ 42dfab439fSBenoit Cousson #define OMAP54XX_AUTO_DPLL_MODE_SHIFT 0 43dfab439fSBenoit Cousson #define OMAP54XX_AUTO_DPLL_MODE_WIDTH 0x3 44dfab439fSBenoit Cousson #define OMAP54XX_AUTO_DPLL_MODE_MASK (0x7 << 0) 45dfab439fSBenoit Cousson 46dfab439fSBenoit Cousson /* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ 47dfab439fSBenoit Cousson #define OMAP54XX_C2C_DYNDEP_SHIFT 18 48dfab439fSBenoit Cousson #define OMAP54XX_C2C_DYNDEP_WIDTH 0x1 49dfab439fSBenoit Cousson #define OMAP54XX_C2C_DYNDEP_MASK (1 << 18) 50dfab439fSBenoit Cousson 51dfab439fSBenoit Cousson /* Used by CM_MPU_STATICDEP */ 52dfab439fSBenoit Cousson #define OMAP54XX_C2C_STATDEP_SHIFT 18 53dfab439fSBenoit Cousson #define OMAP54XX_C2C_STATDEP_WIDTH 0x1 54dfab439fSBenoit Cousson #define OMAP54XX_C2C_STATDEP_MASK (1 << 18) 55dfab439fSBenoit Cousson 56dfab439fSBenoit Cousson /* Used by CM_IPU_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ 57dfab439fSBenoit Cousson #define OMAP54XX_CAM_DYNDEP_SHIFT 9 58dfab439fSBenoit Cousson #define OMAP54XX_CAM_DYNDEP_WIDTH 0x1 59dfab439fSBenoit Cousson #define OMAP54XX_CAM_DYNDEP_MASK (1 << 9) 60dfab439fSBenoit Cousson 61dfab439fSBenoit Cousson /* 62dfab439fSBenoit Cousson * Used by CM_DMA_STATICDEP, CM_DSP_STATICDEP, CM_IPU_STATICDEP, 63dfab439fSBenoit Cousson * CM_MPU_STATICDEP 64dfab439fSBenoit Cousson */ 65dfab439fSBenoit Cousson #define OMAP54XX_CAM_STATDEP_SHIFT 9 66dfab439fSBenoit Cousson #define OMAP54XX_CAM_STATDEP_WIDTH 0x1 67dfab439fSBenoit Cousson #define OMAP54XX_CAM_STATDEP_MASK (1 << 9) 68dfab439fSBenoit Cousson 69dfab439fSBenoit Cousson /* Used by CM_ABE_CLKSTCTRL */ 70dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13 71dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_WIDTH 0x1 72dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_MASK (1 << 13) 73dfab439fSBenoit Cousson 74dfab439fSBenoit Cousson /* Used by CM_ABE_CLKSTCTRL */ 75dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_SHIFT 12 76dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_WIDTH 0x1 77dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_MASK (1 << 12) 78dfab439fSBenoit Cousson 79dfab439fSBenoit Cousson /* Used by CM_ABE_CLKSTCTRL */ 80dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_ABE_GICLK_SHIFT 9 81dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_ABE_GICLK_WIDTH 0x1 82dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_ABE_GICLK_MASK (1 << 9) 83dfab439fSBenoit Cousson 84dfab439fSBenoit Cousson /* Used by CM_WKUPAON_CLKSTCTRL */ 85dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_SHIFT 9 86dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_WIDTH 0x1 87dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9) 88dfab439fSBenoit Cousson 89dfab439fSBenoit Cousson /* Used by CM_ABE_CLKSTCTRL */ 90dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_SHIFT 11 91dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_WIDTH 0x1 92dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_MASK (1 << 11) 93dfab439fSBenoit Cousson 94dfab439fSBenoit Cousson /* Used by CM_ABE_CLKSTCTRL */ 95dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_SHIFT 8 96dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_WIDTH 0x1 97dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8) 98dfab439fSBenoit Cousson 99dfab439fSBenoit Cousson /* Used by CM_DSS_CLKSTCTRL */ 100dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_SHIFT 13 101dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_WIDTH 0x1 102dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_MASK (1 << 13) 103dfab439fSBenoit Cousson 104dfab439fSBenoit Cousson /* Used by CM_C2C_CLKSTCTRL */ 105dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_C2C_GFCLK_SHIFT 9 106dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_C2C_GFCLK_WIDTH 0x1 107dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_C2C_GFCLK_MASK (1 << 9) 108dfab439fSBenoit Cousson 109dfab439fSBenoit Cousson /* Used by CM_C2C_CLKSTCTRL */ 110dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_C2C_GICLK_SHIFT 10 111dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_C2C_GICLK_WIDTH 0x1 112dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_C2C_GICLK_MASK (1 << 10) 113dfab439fSBenoit Cousson 114dfab439fSBenoit Cousson /* Used by CM_C2C_CLKSTCTRL */ 115dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_SHIFT 8 116dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_WIDTH 0x1 117dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_MASK (1 << 8) 118dfab439fSBenoit Cousson 119dfab439fSBenoit Cousson /* Used by CM_CAM_CLKSTCTRL */ 120dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_SHIFT 11 121dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_WIDTH 0x1 122dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_MASK (1 << 11) 123dfab439fSBenoit Cousson 124dfab439fSBenoit Cousson /* Used by CM_CAM_CLKSTCTRL */ 125dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_CAM_GCLK_SHIFT 8 126dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_CAM_GCLK_WIDTH 0x1 127dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_CAM_GCLK_MASK (1 << 8) 128dfab439fSBenoit Cousson 129dfab439fSBenoit Cousson /* Used by CM_CAM_CLKSTCTRL */ 130dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_SHIFT 12 131dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_WIDTH 0x1 132dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_MASK (1 << 12) 133dfab439fSBenoit Cousson 134dfab439fSBenoit Cousson /* Used by CM_COREAON_CLKSTCTRL */ 135dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_SHIFT 12 136dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_WIDTH 0x1 137dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_MASK (1 << 12) 138dfab439fSBenoit Cousson 139dfab439fSBenoit Cousson /* Used by CM_COREAON_CLKSTCTRL */ 140dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_SHIFT 14 141dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_WIDTH 0x1 142dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_MASK (1 << 14) 143dfab439fSBenoit Cousson 144dfab439fSBenoit Cousson /* Used by CM_COREAON_CLKSTCTRL */ 145dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_SHIFT 8 146dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_WIDTH 0x1 147dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_MASK (1 << 8) 148dfab439fSBenoit Cousson 149dfab439fSBenoit Cousson /* Used by CM_CAM_CLKSTCTRL */ 150dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_SHIFT 9 151dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_WIDTH 0x1 152dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_MASK (1 << 9) 153dfab439fSBenoit Cousson 154dfab439fSBenoit Cousson /* Used by CM_CUSTEFUSE_CLKSTCTRL */ 155dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_SHIFT 8 156dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_WIDTH 0x1 157dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_MASK (1 << 8) 158dfab439fSBenoit Cousson 159dfab439fSBenoit Cousson /* Used by CM_CUSTEFUSE_CLKSTCTRL */ 160dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_SHIFT 9 161dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_WIDTH 0x1 162dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_MASK (1 << 9) 163dfab439fSBenoit Cousson 164dfab439fSBenoit Cousson /* Used by CM_EMIF_CLKSTCTRL */ 165dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_DLL_GCLK_SHIFT 9 166dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_DLL_GCLK_WIDTH 0x1 167dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_DLL_GCLK_MASK (1 << 9) 168dfab439fSBenoit Cousson 169dfab439fSBenoit Cousson /* Used by CM_DMA_CLKSTCTRL */ 170dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_SHIFT 8 171dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_WIDTH 0x1 172dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_MASK (1 << 8) 173dfab439fSBenoit Cousson 174dfab439fSBenoit Cousson /* Used by CM_DSP_CLKSTCTRL */ 175dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_DSP_GCLK_SHIFT 8 176dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_DSP_GCLK_WIDTH 0x1 177dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_DSP_GCLK_MASK (1 << 8) 178dfab439fSBenoit Cousson 179dfab439fSBenoit Cousson /* Used by CM_DSS_CLKSTCTRL */ 180dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_DSS_GFCLK_SHIFT 9 181dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_DSS_GFCLK_WIDTH 0x1 182dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_DSS_GFCLK_MASK (1 << 9) 183dfab439fSBenoit Cousson 184dfab439fSBenoit Cousson /* Used by CM_DSS_CLKSTCTRL */ 185dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_SHIFT 8 186dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_WIDTH 0x1 187dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_MASK (1 << 8) 188dfab439fSBenoit Cousson 189dfab439fSBenoit Cousson /* Used by CM_DSS_CLKSTCTRL */ 190dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_SHIFT 10 191dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_WIDTH 0x1 192dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_MASK (1 << 10) 193dfab439fSBenoit Cousson 194dfab439fSBenoit Cousson /* Used by CM_EMIF_CLKSTCTRL */ 195dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_SHIFT 8 196dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_WIDTH 0x1 197dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_MASK (1 << 8) 198dfab439fSBenoit Cousson 199dfab439fSBenoit Cousson /* Used by CM_EMIF_CLKSTCTRL */ 200dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_SHIFT 11 201dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_WIDTH 0x1 202dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_MASK (1 << 11) 203dfab439fSBenoit Cousson 204dfab439fSBenoit Cousson /* Used by CM_EMIF_CLKSTCTRL */ 205dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_SHIFT 10 206dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_WIDTH 0x1 207dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_MASK (1 << 10) 208dfab439fSBenoit Cousson 209dfab439fSBenoit Cousson /* Used by CM_EMU_CLKSTCTRL */ 210dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_SHIFT 8 211dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_WIDTH 0x1 212dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_MASK (1 << 8) 213dfab439fSBenoit Cousson 214dfab439fSBenoit Cousson /* Used by CM_CAM_CLKSTCTRL */ 215dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_FDIF_GCLK_SHIFT 10 216dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_FDIF_GCLK_WIDTH 0x1 217dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_FDIF_GCLK_MASK (1 << 10) 218dfab439fSBenoit Cousson 219dfab439fSBenoit Cousson /* Used by CM_ABE_CLKSTCTRL */ 220dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10 221dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_WIDTH 0x1 222dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_MASK (1 << 10) 223dfab439fSBenoit Cousson 224dfab439fSBenoit Cousson /* Used by CM_GPU_CLKSTCTRL */ 225dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_SHIFT 9 226dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_WIDTH 0x1 227dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_MASK (1 << 9) 228dfab439fSBenoit Cousson 229dfab439fSBenoit Cousson /* Used by CM_GPU_CLKSTCTRL */ 230dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_SHIFT 10 231dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_WIDTH 0x1 232dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_MASK (1 << 10) 233dfab439fSBenoit Cousson 234dfab439fSBenoit Cousson /* Used by CM_GPU_CLKSTCTRL */ 235dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_SHIFT 8 236dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_WIDTH 0x1 237dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_MASK (1 << 8) 238dfab439fSBenoit Cousson 239dfab439fSBenoit Cousson /* Used by CM_DSS_CLKSTCTRL */ 240dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_SHIFT 12 241dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_WIDTH 0x1 242dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_MASK (1 << 12) 243dfab439fSBenoit Cousson 244dfab439fSBenoit Cousson /* Used by CM_DSS_CLKSTCTRL */ 245dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_SHIFT 11 246dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_WIDTH 0x1 247dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_MASK (1 << 11) 248dfab439fSBenoit Cousson 249dfab439fSBenoit Cousson /* Used by CM_L3INIT_CLKSTCTRL */ 250dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20 251dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_WIDTH 0x1 252dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20) 253dfab439fSBenoit Cousson 254dfab439fSBenoit Cousson /* Used by CM_L3INIT_CLKSTCTRL */ 255dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26 256dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_WIDTH 0x1 257dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26) 258dfab439fSBenoit Cousson 259dfab439fSBenoit Cousson /* Used by CM_L3INIT_CLKSTCTRL */ 260dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21 261dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_WIDTH 0x1 262dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21) 263dfab439fSBenoit Cousson 264dfab439fSBenoit Cousson /* Used by CM_L3INIT_CLKSTCTRL */ 265dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27 266dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_WIDTH 0x1 267dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27) 268dfab439fSBenoit Cousson 269dfab439fSBenoit Cousson /* Used by CM_L3INIT_CLKSTCTRL */ 270dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_SHIFT 6 271dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_WIDTH 0x1 272dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_MASK (1 << 6) 273dfab439fSBenoit Cousson 274dfab439fSBenoit Cousson /* Used by CM_L3INIT_CLKSTCTRL */ 275dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_SHIFT 7 276dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_WIDTH 0x1 277dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_MASK (1 << 7) 278dfab439fSBenoit Cousson 279dfab439fSBenoit Cousson /* Used by CM_L3INIT_CLKSTCTRL */ 280dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_HSI_GFCLK_SHIFT 16 281dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_HSI_GFCLK_WIDTH 0x1 282dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_HSI_GFCLK_MASK (1 << 16) 283dfab439fSBenoit Cousson 284dfab439fSBenoit Cousson /* Used by CM_IPU_CLKSTCTRL */ 285dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_IPU_GCLK_SHIFT 8 286dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_IPU_GCLK_WIDTH 0x1 287dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_IPU_GCLK_MASK (1 << 8) 288dfab439fSBenoit Cousson 289dfab439fSBenoit Cousson /* Used by CM_IVA_CLKSTCTRL */ 290dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_IVA_GCLK_SHIFT 8 291dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_IVA_GCLK_WIDTH 0x1 292dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_IVA_GCLK_MASK (1 << 8) 293dfab439fSBenoit Cousson 294dfab439fSBenoit Cousson /* Used by CM_L3INIT_CLKSTCTRL */ 295dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_SHIFT 12 296dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_WIDTH 0x1 297dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_MASK (1 << 12) 298dfab439fSBenoit Cousson 299dfab439fSBenoit Cousson /* Used by CM_L3INIT_CLKSTCTRL */ 300dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_SHIFT 28 301dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_WIDTH 0x1 302dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_MASK (1 << 28) 303dfab439fSBenoit Cousson 304dfab439fSBenoit Cousson /* Used by CM_L3INIT_CLKSTCTRL */ 305dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_SHIFT 29 306dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_WIDTH 0x1 307dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_MASK (1 << 29) 308dfab439fSBenoit Cousson 309dfab439fSBenoit Cousson /* Used by CM_L3INIT_CLKSTCTRL */ 310dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_SHIFT 8 311dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_WIDTH 0x1 312dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_MASK (1 << 8) 313dfab439fSBenoit Cousson 314dfab439fSBenoit Cousson /* Used by CM_L3INIT_CLKSTCTRL */ 315dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_SHIFT 9 316dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_WIDTH 0x1 317dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_MASK (1 << 9) 318dfab439fSBenoit Cousson 319dfab439fSBenoit Cousson /* Used by CM_L3INIT_CLKSTCTRL */ 320dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_SHIFT 11 321dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_WIDTH 0x1 322dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_MASK (1 << 11) 323dfab439fSBenoit Cousson 324dfab439fSBenoit Cousson /* Used by CM_L3INSTR_CLKSTCTRL */ 325dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_SHIFT 9 326dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_WIDTH 0x1 327dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_MASK (1 << 9) 328dfab439fSBenoit Cousson 329dfab439fSBenoit Cousson /* Used by CM_L3INSTR_CLKSTCTRL */ 330dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_SHIFT 8 331dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_WIDTH 0x1 332dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_MASK (1 << 8) 333dfab439fSBenoit Cousson 334dfab439fSBenoit Cousson /* Used by CM_L3INSTR_CLKSTCTRL */ 335dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_SHIFT 10 336dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_WIDTH 0x1 337dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_MASK (1 << 10) 338dfab439fSBenoit Cousson 339dfab439fSBenoit Cousson /* Used by CM_L3MAIN1_CLKSTCTRL */ 340dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_SHIFT 8 341dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_WIDTH 0x1 342dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_MASK (1 << 8) 343dfab439fSBenoit Cousson 344dfab439fSBenoit Cousson /* Used by CM_L3MAIN2_CLKSTCTRL */ 345dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_SHIFT 8 346dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_WIDTH 0x1 347dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_MASK (1 << 8) 348dfab439fSBenoit Cousson 349dfab439fSBenoit Cousson /* Used by CM_L4CFG_CLKSTCTRL */ 350dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_SHIFT 8 351dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_WIDTH 0x1 352dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_MASK (1 << 8) 353dfab439fSBenoit Cousson 354dfab439fSBenoit Cousson /* Used by CM_L4PER_CLKSTCTRL */ 355dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_SHIFT 8 356dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_WIDTH 0x1 357dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_MASK (1 << 8) 358dfab439fSBenoit Cousson 359dfab439fSBenoit Cousson /* Used by CM_L4SEC_CLKSTCTRL */ 360dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_SHIFT 8 361dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_WIDTH 0x1 362dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_MASK (1 << 8) 363dfab439fSBenoit Cousson 364dfab439fSBenoit Cousson /* Used by CM_L4SEC_CLKSTCTRL */ 365dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_SHIFT 9 366dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_WIDTH 0x1 367dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_MASK (1 << 9) 368dfab439fSBenoit Cousson 369dfab439fSBenoit Cousson /* Used by CM_MIPIEXT_CLKSTCTRL */ 370dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_SHIFT 8 371dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_WIDTH 0x1 372dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_MASK (1 << 8) 373dfab439fSBenoit Cousson 374dfab439fSBenoit Cousson /* Used by CM_MIPIEXT_CLKSTCTRL */ 375dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_SHIFT 11 376dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_WIDTH 0x1 377dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_MASK (1 << 11) 378dfab439fSBenoit Cousson 379dfab439fSBenoit Cousson /* Used by CM_L3INIT_CLKSTCTRL */ 380dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_SHIFT 2 381dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_WIDTH 0x1 382dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_MASK (1 << 2) 383dfab439fSBenoit Cousson 384dfab439fSBenoit Cousson /* Used by CM_L3INIT_CLKSTCTRL */ 385dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_SHIFT 17 386dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_WIDTH 0x1 387dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_MASK (1 << 17) 388dfab439fSBenoit Cousson 389dfab439fSBenoit Cousson /* Used by CM_L3INIT_CLKSTCTRL */ 390dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_SHIFT 18 391dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_WIDTH 0x1 392dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_MASK (1 << 18) 393dfab439fSBenoit Cousson 394dfab439fSBenoit Cousson /* Used by CM_MPU_CLKSTCTRL */ 395dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_MPU_GCLK_SHIFT 8 396dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_MPU_GCLK_WIDTH 0x1 397dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_MPU_GCLK_MASK (1 << 8) 398dfab439fSBenoit Cousson 399dfab439fSBenoit Cousson /* Used by CM_ABE_CLKSTCTRL */ 400dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_PAD_CLKS_SHIFT 14 401dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_PAD_CLKS_WIDTH 0x1 402dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_PAD_CLKS_MASK (1 << 14) 403dfab439fSBenoit Cousson 404dfab439fSBenoit Cousson /* Used by CM_ABE_CLKSTCTRL */ 405dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_SHIFT 15 406dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_WIDTH 0x1 407dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_MASK (1 << 15) 408dfab439fSBenoit Cousson 409dfab439fSBenoit Cousson /* Used by CM_L3INIT_CLKSTCTRL */ 410dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_SHIFT 3 411dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_WIDTH 0x1 412dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_MASK (1 << 3) 413dfab439fSBenoit Cousson 414dfab439fSBenoit Cousson /* Used by CM_L3INIT_CLKSTCTRL */ 415dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_SHIFT 4 416dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_WIDTH 0x1 417dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_MASK (1 << 4) 418dfab439fSBenoit Cousson 419dfab439fSBenoit Cousson /* Used by CM_L4PER_CLKSTCTRL */ 420dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_SHIFT 15 421dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_WIDTH 0x1 422dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_MASK (1 << 15) 423dfab439fSBenoit Cousson 424dfab439fSBenoit Cousson /* Used by CM_L4PER_CLKSTCTRL */ 425dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17 426dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_WIDTH 0x1 427dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17) 428dfab439fSBenoit Cousson 429dfab439fSBenoit Cousson /* Used by CM_L4PER_CLKSTCTRL */ 430dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18 431dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_WIDTH 0x1 432dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18) 433dfab439fSBenoit Cousson 434dfab439fSBenoit Cousson /* Used by CM_L4PER_CLKSTCTRL */ 435dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19 436dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_WIDTH 0x1 437dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19) 438dfab439fSBenoit Cousson 439dfab439fSBenoit Cousson /* Used by CM_L3INIT_CLKSTCTRL */ 440dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_SHIFT 19 441dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_WIDTH 0x1 442dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_MASK (1 << 19) 443dfab439fSBenoit Cousson 444dfab439fSBenoit Cousson /* Used by CM_COREAON_CLKSTCTRL */ 445dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_SHIFT 11 446dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_WIDTH 0x1 447dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_MASK (1 << 11) 448dfab439fSBenoit Cousson 449dfab439fSBenoit Cousson /* Used by CM_COREAON_CLKSTCTRL */ 450dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_SHIFT 10 451dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_WIDTH 0x1 452dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_MASK (1 << 10) 453dfab439fSBenoit Cousson 454dfab439fSBenoit Cousson /* Used by CM_COREAON_CLKSTCTRL */ 455dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_SHIFT 9 456dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_WIDTH 0x1 457dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_MASK (1 << 9) 458dfab439fSBenoit Cousson 459dfab439fSBenoit Cousson /* Used by CM_WKUPAON_CLKSTCTRL */ 460dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_SYS_CLK_SHIFT 8 461dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_SYS_CLK_WIDTH 0x1 462dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_SYS_CLK_MASK (1 << 8) 463dfab439fSBenoit Cousson 464dfab439fSBenoit Cousson /* Used by CM_WKUPAON_CLKSTCTRL */ 465dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_SHIFT 15 466dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_WIDTH 0x1 467dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_MASK (1 << 15) 468dfab439fSBenoit Cousson 469dfab439fSBenoit Cousson /* Used by CM_WKUPAON_CLKSTCTRL */ 470dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_SHIFT 14 471dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_WIDTH 0x1 472dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_MASK (1 << 14) 473dfab439fSBenoit Cousson 474dfab439fSBenoit Cousson /* Used by CM_L4PER_CLKSTCTRL */ 475dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_SHIFT 9 476dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_WIDTH 0x1 477dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_MASK (1 << 9) 478dfab439fSBenoit Cousson 479dfab439fSBenoit Cousson /* Used by CM_L4PER_CLKSTCTRL */ 480dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_SHIFT 10 481dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_WIDTH 0x1 482dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_MASK (1 << 10) 483dfab439fSBenoit Cousson 484dfab439fSBenoit Cousson /* Used by CM_L4PER_CLKSTCTRL */ 485dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_SHIFT 11 486dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_WIDTH 0x1 487dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_MASK (1 << 11) 488dfab439fSBenoit Cousson 489dfab439fSBenoit Cousson /* Used by CM_L4PER_CLKSTCTRL */ 490dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_SHIFT 12 491dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_WIDTH 0x1 492dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_MASK (1 << 12) 493dfab439fSBenoit Cousson 494dfab439fSBenoit Cousson /* Used by CM_L4PER_CLKSTCTRL */ 495dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_SHIFT 13 496dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_WIDTH 0x1 497dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_MASK (1 << 13) 498dfab439fSBenoit Cousson 499dfab439fSBenoit Cousson /* Used by CM_L4PER_CLKSTCTRL */ 500dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_SHIFT 14 501dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_WIDTH 0x1 502dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_MASK (1 << 14) 503dfab439fSBenoit Cousson 504dfab439fSBenoit Cousson /* Used by CM_L3INIT_CLKSTCTRL */ 505dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22 506dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_WIDTH 0x1 507dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22) 508dfab439fSBenoit Cousson 509dfab439fSBenoit Cousson /* Used by CM_L3INIT_CLKSTCTRL */ 510dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23 511dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_WIDTH 0x1 512dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23) 513dfab439fSBenoit Cousson 514dfab439fSBenoit Cousson /* Used by CM_L3INIT_CLKSTCTRL */ 515dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24 516dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_WIDTH 0x1 517dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24) 518dfab439fSBenoit Cousson 519dfab439fSBenoit Cousson /* Used by CM_MIPIEXT_CLKSTCTRL */ 520dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_SHIFT 10 521dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_WIDTH 0x1 522dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_MASK (1 << 10) 523dfab439fSBenoit Cousson 524dfab439fSBenoit Cousson /* Used by CM_MIPIEXT_CLKSTCTRL */ 525dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_SHIFT 13 526dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_WIDTH 0x1 527dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_MASK (1 << 13) 528dfab439fSBenoit Cousson 529dfab439fSBenoit Cousson /* Used by CM_MIPIEXT_CLKSTCTRL */ 530dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_SHIFT 12 531dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_WIDTH 0x1 532dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_MASK (1 << 12) 533dfab439fSBenoit Cousson 534dfab439fSBenoit Cousson /* Used by CM_L3INIT_CLKSTCTRL */ 535dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_SHIFT 10 536dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_WIDTH 0x1 537dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_MASK (1 << 10) 538dfab439fSBenoit Cousson 539dfab439fSBenoit Cousson /* Used by CM_L3INIT_CLKSTCTRL */ 540dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_SHIFT 13 541dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_WIDTH 0x1 542dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_MASK (1 << 13) 543dfab439fSBenoit Cousson 544dfab439fSBenoit Cousson /* Used by CM_L3INIT_CLKSTCTRL */ 545dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_SHIFT 5 546dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_WIDTH 0x1 547dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_MASK (1 << 5) 548dfab439fSBenoit Cousson 549dfab439fSBenoit Cousson /* Used by CM_L3INIT_CLKSTCTRL */ 550dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14 551dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_WIDTH 0x1 552dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14) 553dfab439fSBenoit Cousson 554dfab439fSBenoit Cousson /* Used by CM_L3INIT_CLKSTCTRL */ 555dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15 556dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH 0x1 557dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15) 558dfab439fSBenoit Cousson 559dfab439fSBenoit Cousson /* Used by CM_L3INIT_CLKSTCTRL */ 560dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_SHIFT 31 561dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_WIDTH 0x1 562dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_MASK (1 << 31) 563dfab439fSBenoit Cousson 564dfab439fSBenoit Cousson /* Used by CM_L3INIT_CLKSTCTRL */ 565dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30 566dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_WIDTH 0x1 567dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30) 568dfab439fSBenoit Cousson 569dfab439fSBenoit Cousson /* Used by CM_L3INIT_CLKSTCTRL */ 570dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25 571dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_WIDTH 0x1 572dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25) 573dfab439fSBenoit Cousson 574dfab439fSBenoit Cousson /* Used by CM_WKUPAON_CLKSTCTRL */ 575dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_SHIFT 11 576dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_WIDTH 0x1 577dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_MASK (1 << 11) 578dfab439fSBenoit Cousson 579dfab439fSBenoit Cousson /* Used by CM_WKUPAON_CLKSTCTRL */ 580dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_SHIFT 12 581dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_WIDTH 0x1 582dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_MASK (1 << 12) 583dfab439fSBenoit Cousson 584dfab439fSBenoit Cousson /* Used by CM_WKUPAON_CLKSTCTRL */ 585dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_SHIFT 13 586dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_WIDTH 0x1 587dfab439fSBenoit Cousson #define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_MASK (1 << 13) 588dfab439fSBenoit Cousson 589dfab439fSBenoit Cousson /* Used by CM_COREAON_IO_SRCOMP_CLKCTRL, CM_WKUPAON_IO_SRCOMP_CLKCTRL */ 590dfab439fSBenoit Cousson #define OMAP54XX_CLKEN_SRCOMP_FCLK_SHIFT 8 591dfab439fSBenoit Cousson #define OMAP54XX_CLKEN_SRCOMP_FCLK_WIDTH 0x1 592dfab439fSBenoit Cousson #define OMAP54XX_CLKEN_SRCOMP_FCLK_MASK (1 << 8) 593dfab439fSBenoit Cousson 594dfab439fSBenoit Cousson /* 595dfab439fSBenoit Cousson * Used by CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL, 596dfab439fSBenoit Cousson * CM_ABE_TIMER8_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL, 597dfab439fSBenoit Cousson * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL, 598dfab439fSBenoit Cousson * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL 599dfab439fSBenoit Cousson */ 600dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_SHIFT 24 601dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_WIDTH 0x1 602dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_MASK (1 << 24) 603dfab439fSBenoit Cousson 604dfab439fSBenoit Cousson /* 605dfab439fSBenoit Cousson * Renamed from CLKSEL Used by CM_CLKSEL_ABE_DSS_SYS, CM_CLKSEL_ABE_PLL_REF, 606dfab439fSBenoit Cousson * CM_CLKSEL_USB_60MHZ, CM_CLKSEL_WKUPAON 607dfab439fSBenoit Cousson */ 608dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_0_0_SHIFT 0 609dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_0_0_WIDTH 0x1 610dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_0_0_MASK (1 << 0) 611dfab439fSBenoit Cousson 612dfab439fSBenoit Cousson /* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */ 613dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_0_1_SHIFT 0 614dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_0_1_WIDTH 0x2 615dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_0_1_MASK (0x3 << 0) 616dfab439fSBenoit Cousson 617dfab439fSBenoit Cousson /* Renamed from CLKSEL Used by CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL */ 618dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_24_25_SHIFT 24 619dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_24_25_WIDTH 0x2 620dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_24_25_MASK (0x3 << 24) 621dfab439fSBenoit Cousson 622dfab439fSBenoit Cousson /* Used by CM_MPU_MPU_CLKCTRL */ 623dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_ABE_DIV_MODE_SHIFT 26 624dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_ABE_DIV_MODE_WIDTH 0x1 625dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_ABE_DIV_MODE_MASK (1 << 26) 626dfab439fSBenoit Cousson 627dfab439fSBenoit Cousson /* Used by CM_ABE_AESS_CLKCTRL */ 628dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_AESS_FCLK_SHIFT 24 629dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_AESS_FCLK_WIDTH 0x1 630dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_AESS_FCLK_MASK (1 << 24) 631dfab439fSBenoit Cousson 632dfab439fSBenoit Cousson /* Used by CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL */ 633dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_DIV_SHIFT 25 634dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_DIV_WIDTH 0x1 635dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_DIV_MASK (1 << 25) 636dfab439fSBenoit Cousson 637dfab439fSBenoit Cousson /* Used by CM_MPU_MPU_CLKCTRL */ 638dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_EMIF_DIV_MODE_SHIFT 24 639dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_EMIF_DIV_MODE_WIDTH 0x2 640dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_EMIF_DIV_MODE_MASK (0x3 << 24) 641dfab439fSBenoit Cousson 642dfab439fSBenoit Cousson /* Used by CM_CAM_FDIF_CLKCTRL */ 643dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_FCLK_SHIFT 24 644dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_FCLK_WIDTH 0x1 645dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_FCLK_MASK (1 << 24) 646dfab439fSBenoit Cousson 647dfab439fSBenoit Cousson /* Used by CM_GPU_GPU_CLKCTRL */ 648dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT 24 649dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_GPU_CORE_GCLK_WIDTH 0x1 650dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_GPU_CORE_GCLK_MASK (1 << 24) 651dfab439fSBenoit Cousson 652dfab439fSBenoit Cousson /* Used by CM_GPU_GPU_CLKCTRL */ 653dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT 25 654dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_GPU_HYD_GCLK_WIDTH 0x1 655dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_GPU_HYD_GCLK_MASK (1 << 25) 656dfab439fSBenoit Cousson 657dfab439fSBenoit Cousson /* Used by CM_GPU_GPU_CLKCTRL */ 658dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_GPU_SYS_CLK_SHIFT 26 659dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_GPU_SYS_CLK_WIDTH 0x1 660dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_GPU_SYS_CLK_MASK (1 << 26) 661dfab439fSBenoit Cousson 662dfab439fSBenoit Cousson /* 663dfab439fSBenoit Cousson * Used by CM_ABE_DMIC_CLKCTRL, CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, 664dfab439fSBenoit Cousson * CM_ABE_MCBSP2_CLKCTRL, CM_ABE_MCBSP3_CLKCTRL 665dfab439fSBenoit Cousson */ 666dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT 26 667dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH 0x2 668dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_INTERNAL_SOURCE_MASK (0x3 << 26) 669dfab439fSBenoit Cousson 670dfab439fSBenoit Cousson /* Used by CM_CLKSEL_CORE */ 671dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_L3_SHIFT 4 672dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_L3_WIDTH 0x1 673dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_L3_MASK (1 << 4) 674dfab439fSBenoit Cousson 675dfab439fSBenoit Cousson /* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */ 676dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_L3_1_1_SHIFT 1 677dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_L3_1_1_WIDTH 0x1 678dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_L3_1_1_MASK (1 << 1) 679dfab439fSBenoit Cousson 680dfab439fSBenoit Cousson /* Used by CM_CLKSEL_CORE */ 681dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_L4_SHIFT 8 682dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_L4_WIDTH 0x1 683dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_L4_MASK (1 << 8) 684dfab439fSBenoit Cousson 685dfab439fSBenoit Cousson /* Used by CM_EMIF_EMIF1_CLKCTRL */ 686dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_LL_SHIFT 24 687dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_LL_WIDTH 0x1 688dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_LL_MASK (1 << 24) 689dfab439fSBenoit Cousson 690dfab439fSBenoit Cousson /* Used by CM_CLKSEL_ABE */ 691dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_OPP_SHIFT 0 692dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_OPP_WIDTH 0x2 693dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_OPP_MASK (0x3 << 0) 694dfab439fSBenoit Cousson 695dfab439fSBenoit Cousson /* Renamed from CLKSEL_OPP Used by CM_L3INIT_UNIPRO2_CLKCTRL */ 696dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_OPP_24_24_SHIFT 24 697dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_OPP_24_24_WIDTH 0x1 698dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_OPP_24_24_MASK (1 << 24) 699dfab439fSBenoit Cousson 700dfab439fSBenoit Cousson /* 701dfab439fSBenoit Cousson * Used by CM_ABE_DMIC_CLKCTRL, CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, 702dfab439fSBenoit Cousson * CM_ABE_MCBSP2_CLKCTRL, CM_ABE_MCBSP3_CLKCTRL 703dfab439fSBenoit Cousson */ 704dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_SOURCE_SHIFT 24 705dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_SOURCE_WIDTH 0x2 706dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_SOURCE_MASK (0x3 << 24) 707dfab439fSBenoit Cousson 708dfab439fSBenoit Cousson /* 709dfab439fSBenoit Cousson * Renamed from CLKSEL_SOURCE Used by CM_L3INIT_MMC1_CLKCTRL, 710dfab439fSBenoit Cousson * CM_L3INIT_MMC2_CLKCTRL 711dfab439fSBenoit Cousson */ 712dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT 24 713dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH 0x1 714dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_MASK (1 << 24) 715dfab439fSBenoit Cousson 716dfab439fSBenoit Cousson /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ 717dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_UTMI_P1_SHIFT 24 718dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_UTMI_P1_WIDTH 0x1 719dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_UTMI_P1_MASK (1 << 24) 720dfab439fSBenoit Cousson 721dfab439fSBenoit Cousson /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ 722dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_UTMI_P2_SHIFT 25 723dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_UTMI_P2_WIDTH 0x1 724dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_UTMI_P2_MASK (1 << 25) 725dfab439fSBenoit Cousson 726dfab439fSBenoit Cousson /* 727dfab439fSBenoit Cousson * Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_IVA, CM_DIV_H11_DPLL_PER, 728dfab439fSBenoit Cousson * CM_DIV_H12_DPLL_CORE, CM_DIV_H12_DPLL_IVA, CM_DIV_H12_DPLL_PER, 729dfab439fSBenoit Cousson * CM_DIV_H13_DPLL_CORE, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE, 730dfab439fSBenoit Cousson * CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE, CM_DIV_H22_DPLL_CORE, 731dfab439fSBenoit Cousson * CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE, CM_DIV_M2_DPLL_ABE, 732dfab439fSBenoit Cousson * CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, 733dfab439fSBenoit Cousson * CM_DIV_M2_DPLL_UNIPRO1, CM_DIV_M2_DPLL_UNIPRO2, CM_DIV_M2_DPLL_USB, 734dfab439fSBenoit Cousson * CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER 735dfab439fSBenoit Cousson */ 736dfab439fSBenoit Cousson #define OMAP54XX_CLKST_SHIFT 9 737dfab439fSBenoit Cousson #define OMAP54XX_CLKST_WIDTH 0x1 738dfab439fSBenoit Cousson #define OMAP54XX_CLKST_MASK (1 << 9) 739dfab439fSBenoit Cousson 740dfab439fSBenoit Cousson /* 741dfab439fSBenoit Cousson * Used by CM_ABE_CLKSTCTRL, CM_C2C_CLKSTCTRL, CM_CAM_CLKSTCTRL, 742dfab439fSBenoit Cousson * CM_COREAON_CLKSTCTRL, CM_CUSTEFUSE_CLKSTCTRL, CM_DMA_CLKSTCTRL, 743dfab439fSBenoit Cousson * CM_DSP_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_EMIF_CLKSTCTRL, CM_EMU_CLKSTCTRL, 744dfab439fSBenoit Cousson * CM_GPU_CLKSTCTRL, CM_IPU_CLKSTCTRL, CM_IVA_CLKSTCTRL, CM_L3INIT_CLKSTCTRL, 745dfab439fSBenoit Cousson * CM_L3INSTR_CLKSTCTRL, CM_L3MAIN1_CLKSTCTRL, CM_L3MAIN2_CLKSTCTRL, 746dfab439fSBenoit Cousson * CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL, CM_L4SEC_CLKSTCTRL, 747dfab439fSBenoit Cousson * CM_MIPIEXT_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_WKUPAON_CLKSTCTRL 748dfab439fSBenoit Cousson */ 749dfab439fSBenoit Cousson #define OMAP54XX_CLKTRCTRL_SHIFT 0 750dfab439fSBenoit Cousson #define OMAP54XX_CLKTRCTRL_WIDTH 0x2 751dfab439fSBenoit Cousson #define OMAP54XX_CLKTRCTRL_MASK (0x3 << 0) 752dfab439fSBenoit Cousson 753dfab439fSBenoit Cousson /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER */ 754dfab439fSBenoit Cousson #define OMAP54XX_CLKX2ST_SHIFT 11 755dfab439fSBenoit Cousson #define OMAP54XX_CLKX2ST_WIDTH 0x1 756dfab439fSBenoit Cousson #define OMAP54XX_CLKX2ST_MASK (1 << 11) 757dfab439fSBenoit Cousson 758dfab439fSBenoit Cousson /* Used by CM_L4CFG_DYNAMICDEP */ 759dfab439fSBenoit Cousson #define OMAP54XX_COREAON_DYNDEP_SHIFT 16 760dfab439fSBenoit Cousson #define OMAP54XX_COREAON_DYNDEP_WIDTH 0x1 761dfab439fSBenoit Cousson #define OMAP54XX_COREAON_DYNDEP_MASK (1 << 16) 762dfab439fSBenoit Cousson 763dfab439fSBenoit Cousson /* Used by CM_DSP_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */ 764dfab439fSBenoit Cousson #define OMAP54XX_COREAON_STATDEP_SHIFT 16 765dfab439fSBenoit Cousson #define OMAP54XX_COREAON_STATDEP_WIDTH 0x1 766dfab439fSBenoit Cousson #define OMAP54XX_COREAON_STATDEP_MASK (1 << 16) 767dfab439fSBenoit Cousson 768dfab439fSBenoit Cousson /* Used by CM_L4CFG_DYNAMICDEP */ 769dfab439fSBenoit Cousson #define OMAP54XX_CUSTEFUSE_DYNDEP_SHIFT 17 770dfab439fSBenoit Cousson #define OMAP54XX_CUSTEFUSE_DYNDEP_WIDTH 0x1 771dfab439fSBenoit Cousson #define OMAP54XX_CUSTEFUSE_DYNDEP_MASK (1 << 17) 772dfab439fSBenoit Cousson 773dfab439fSBenoit Cousson /* Used by CM_DSP_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */ 774dfab439fSBenoit Cousson #define OMAP54XX_CUSTEFUSE_STATDEP_SHIFT 17 775dfab439fSBenoit Cousson #define OMAP54XX_CUSTEFUSE_STATDEP_WIDTH 0x1 776dfab439fSBenoit Cousson #define OMAP54XX_CUSTEFUSE_STATDEP_MASK (1 << 17) 777dfab439fSBenoit Cousson 778dfab439fSBenoit Cousson /* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ 779dfab439fSBenoit Cousson #define OMAP54XX_CUSTOM_SHIFT 6 780dfab439fSBenoit Cousson #define OMAP54XX_CUSTOM_WIDTH 0x2 781dfab439fSBenoit Cousson #define OMAP54XX_CUSTOM_MASK (0x3 << 6) 782dfab439fSBenoit Cousson 783dfab439fSBenoit Cousson /* 784dfab439fSBenoit Cousson * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA, 785dfab439fSBenoit Cousson * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO1, 786dfab439fSBenoit Cousson * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB 787dfab439fSBenoit Cousson */ 788dfab439fSBenoit Cousson #define OMAP54XX_DCC_EN_SHIFT 22 789dfab439fSBenoit Cousson #define OMAP54XX_DCC_EN_WIDTH 0x1 790dfab439fSBenoit Cousson #define OMAP54XX_DCC_EN_MASK (1 << 22) 791dfab439fSBenoit Cousson 792dfab439fSBenoit Cousson /* 793dfab439fSBenoit Cousson * Used by CM_CORE_AON_DEBUG_CM_CORE_AON_FD_TRANS, 794dfab439fSBenoit Cousson * CM_CORE_AON_DEBUG_DSS_FD_TRANS, CM_CORE_AON_DEBUG_EMIF_FD_TRANS, 795dfab439fSBenoit Cousson * CM_CORE_AON_DEBUG_L4SEC_FD_TRANS 796dfab439fSBenoit Cousson */ 797dfab439fSBenoit Cousson #define OMAP54XX_CM_DEBUG_OUT_SHIFT 0 798dfab439fSBenoit Cousson #define OMAP54XX_CM_DEBUG_OUT_WIDTH 0xd 799dfab439fSBenoit Cousson #define OMAP54XX_CM_DEBUG_OUT_MASK (0x1fff << 0) 800dfab439fSBenoit Cousson 801dfab439fSBenoit Cousson /* 802dfab439fSBenoit Cousson * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_ABE_FD_TRANS, 803dfab439fSBenoit Cousson * CM_CORE_AON_DEBUG_L3INIT_FD_TRANS, CM_CORE_AON_DEBUG_L4PER_FD_TRANS 804dfab439fSBenoit Cousson */ 805dfab439fSBenoit Cousson #define OMAP54XX_DEBUG_OUT_0_31_SHIFT 0 806dfab439fSBenoit Cousson #define OMAP54XX_DEBUG_OUT_0_31_WIDTH 0x20 807dfab439fSBenoit Cousson #define OMAP54XX_DEBUG_OUT_0_31_MASK (0xffffffff << 0) 808dfab439fSBenoit Cousson 809dfab439fSBenoit Cousson /* 810dfab439fSBenoit Cousson * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_C2C_FD_TRANS, 811dfab439fSBenoit Cousson * CM_CORE_AON_DEBUG_COREAON_FD_TRANS, CM_CORE_AON_DEBUG_L4CFG_FD_TRANS 812dfab439fSBenoit Cousson */ 813dfab439fSBenoit Cousson #define OMAP54XX_DEBUG_OUT_0_8_SHIFT 0 814dfab439fSBenoit Cousson #define OMAP54XX_DEBUG_OUT_0_8_WIDTH 0x9 815dfab439fSBenoit Cousson #define OMAP54XX_DEBUG_OUT_0_8_MASK (0x1ff << 0) 816dfab439fSBenoit Cousson 817dfab439fSBenoit Cousson /* 818dfab439fSBenoit Cousson * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_CUSTEFUSE_FD_TRANS, 819dfab439fSBenoit Cousson * CM_CORE_AON_DEBUG_DMA_FD_TRANS, CM_CORE_AON_DEBUG_L3MAIN1_FD_TRANS 820dfab439fSBenoit Cousson */ 821dfab439fSBenoit Cousson #define OMAP54XX_DEBUG_OUT_0_4_SHIFT 0 822dfab439fSBenoit Cousson #define OMAP54XX_DEBUG_OUT_0_4_WIDTH 0x5 823dfab439fSBenoit Cousson #define OMAP54XX_DEBUG_OUT_0_4_MASK (0x1f << 0) 824dfab439fSBenoit Cousson 825dfab439fSBenoit Cousson /* 826dfab439fSBenoit Cousson * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_DSP_FD_TRANS, 827dfab439fSBenoit Cousson * CM_CORE_AON_DEBUG_IPU_FD_TRANS, CM_CORE_AON_DEBUG_MPU_FD_TRANS 828dfab439fSBenoit Cousson */ 829dfab439fSBenoit Cousson #define OMAP54XX_DEBUG_OUT_0_5_SHIFT 0 830dfab439fSBenoit Cousson #define OMAP54XX_DEBUG_OUT_0_5_WIDTH 0x6 831dfab439fSBenoit Cousson #define OMAP54XX_DEBUG_OUT_0_5_MASK (0x3f << 0) 832dfab439fSBenoit Cousson 833dfab439fSBenoit Cousson /* 834dfab439fSBenoit Cousson * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_CAM_FD_TRANS, 835dfab439fSBenoit Cousson * CM_CORE_AON_DEBUG_MIPIEXT_FD_TRANS 836dfab439fSBenoit Cousson */ 837dfab439fSBenoit Cousson #define OMAP54XX_DEBUG_OUT_0_10_SHIFT 0 838dfab439fSBenoit Cousson #define OMAP54XX_DEBUG_OUT_0_10_WIDTH 0xb 839dfab439fSBenoit Cousson #define OMAP54XX_DEBUG_OUT_0_10_MASK (0x7ff << 0) 840dfab439fSBenoit Cousson 841dfab439fSBenoit Cousson /* 842dfab439fSBenoit Cousson * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_IVA_FD_TRANS, 843dfab439fSBenoit Cousson * CM_CORE_AON_DEBUG_L3MAIN2_FD_TRANS 844dfab439fSBenoit Cousson */ 845dfab439fSBenoit Cousson #define OMAP54XX_DEBUG_OUT_0_6_SHIFT 0 846dfab439fSBenoit Cousson #define OMAP54XX_DEBUG_OUT_0_6_WIDTH 0x7 847dfab439fSBenoit Cousson #define OMAP54XX_DEBUG_OUT_0_6_MASK (0x7f << 0) 848dfab439fSBenoit Cousson 849dfab439fSBenoit Cousson /* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_ABE_FD_TRANS2 */ 850dfab439fSBenoit Cousson #define OMAP54XX_DEBUG_OUT_0_19_SHIFT 0 851dfab439fSBenoit Cousson #define OMAP54XX_DEBUG_OUT_0_19_WIDTH 0x14 852dfab439fSBenoit Cousson #define OMAP54XX_DEBUG_OUT_0_19_MASK (0xfffff << 0) 853dfab439fSBenoit Cousson 854dfab439fSBenoit Cousson /* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_GPU_FD_TRANS */ 855dfab439fSBenoit Cousson #define OMAP54XX_DEBUG_OUT_0_9_SHIFT 0 856dfab439fSBenoit Cousson #define OMAP54XX_DEBUG_OUT_0_9_WIDTH 0xa 857dfab439fSBenoit Cousson #define OMAP54XX_DEBUG_OUT_0_9_MASK (0x3ff << 0) 858dfab439fSBenoit Cousson 859dfab439fSBenoit Cousson /* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L3INIT_FD_TRANS2 */ 860dfab439fSBenoit Cousson #define OMAP54XX_DEBUG_OUT_0_26_SHIFT 0 861dfab439fSBenoit Cousson #define OMAP54XX_DEBUG_OUT_0_26_WIDTH 0x1b 862dfab439fSBenoit Cousson #define OMAP54XX_DEBUG_OUT_0_26_MASK (0x7ffffff << 0) 863dfab439fSBenoit Cousson 864dfab439fSBenoit Cousson /* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L3INSTR_FD_TRANS */ 865dfab439fSBenoit Cousson #define OMAP54XX_DEBUG_OUT_0_13_SHIFT 0 866dfab439fSBenoit Cousson #define OMAP54XX_DEBUG_OUT_0_13_WIDTH 0xe 867dfab439fSBenoit Cousson #define OMAP54XX_DEBUG_OUT_0_13_MASK (0x3fff << 0) 868dfab439fSBenoit Cousson 869dfab439fSBenoit Cousson /* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L4PER_FD_TRANS2 */ 870dfab439fSBenoit Cousson #define OMAP54XX_DEBUG_OUT_0_21_SHIFT 0 871dfab439fSBenoit Cousson #define OMAP54XX_DEBUG_OUT_0_21_WIDTH 0x16 872dfab439fSBenoit Cousson #define OMAP54XX_DEBUG_OUT_0_21_MASK (0x3fffff << 0) 873dfab439fSBenoit Cousson 874dfab439fSBenoit Cousson /* 875dfab439fSBenoit Cousson * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE, 876dfab439fSBenoit Cousson * CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU, 877dfab439fSBenoit Cousson * CM_SSC_DELTAMSTEP_DPLL_PER 878dfab439fSBenoit Cousson */ 879dfab439fSBenoit Cousson #define OMAP54XX_DELTAMSTEP_SHIFT 0 880dfab439fSBenoit Cousson #define OMAP54XX_DELTAMSTEP_WIDTH 0x14 881dfab439fSBenoit Cousson #define OMAP54XX_DELTAMSTEP_MASK (0xfffff << 0) 882dfab439fSBenoit Cousson 883dfab439fSBenoit Cousson /* 884dfab439fSBenoit Cousson * Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_UNIPRO1, 885dfab439fSBenoit Cousson * CM_SSC_DELTAMSTEP_DPLL_UNIPRO2, CM_SSC_DELTAMSTEP_DPLL_USB 886dfab439fSBenoit Cousson */ 887dfab439fSBenoit Cousson #define OMAP54XX_DELTAMSTEP_0_20_SHIFT 0 888dfab439fSBenoit Cousson #define OMAP54XX_DELTAMSTEP_0_20_WIDTH 0x15 889dfab439fSBenoit Cousson #define OMAP54XX_DELTAMSTEP_0_20_MASK (0x1fffff << 0) 890dfab439fSBenoit Cousson 891dfab439fSBenoit Cousson /* 892dfab439fSBenoit Cousson * Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_IVA, CM_DIV_H11_DPLL_PER, 893dfab439fSBenoit Cousson * CM_DIV_H12_DPLL_CORE, CM_DIV_H12_DPLL_IVA, CM_DIV_H12_DPLL_PER, 894dfab439fSBenoit Cousson * CM_DIV_H13_DPLL_CORE, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE, 895dfab439fSBenoit Cousson * CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE, CM_DIV_H22_DPLL_CORE, 896dfab439fSBenoit Cousson * CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE 897dfab439fSBenoit Cousson */ 898dfab439fSBenoit Cousson #define OMAP54XX_DIVHS_SHIFT 0 899dfab439fSBenoit Cousson #define OMAP54XX_DIVHS_WIDTH 0x6 900dfab439fSBenoit Cousson #define OMAP54XX_DIVHS_MASK (0x3f << 0) 901dfab439fSBenoit Cousson 902dfab439fSBenoit Cousson /* 903dfab439fSBenoit Cousson * Renamed from DIVHS Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, 904dfab439fSBenoit Cousson * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M3_DPLL_ABE, 905dfab439fSBenoit Cousson * CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER 906dfab439fSBenoit Cousson */ 907dfab439fSBenoit Cousson #define OMAP54XX_DIVHS_0_4_SHIFT 0 908dfab439fSBenoit Cousson #define OMAP54XX_DIVHS_0_4_WIDTH 0x5 909dfab439fSBenoit Cousson #define OMAP54XX_DIVHS_0_4_MASK (0x1f << 0) 910dfab439fSBenoit Cousson 911dfab439fSBenoit Cousson /* 912dfab439fSBenoit Cousson * Renamed from DIVHS Used by CM_DIV_M2_DPLL_UNIPRO1, CM_DIV_M2_DPLL_UNIPRO2, 913dfab439fSBenoit Cousson * CM_DIV_M2_DPLL_USB 914dfab439fSBenoit Cousson */ 915dfab439fSBenoit Cousson #define OMAP54XX_DIVHS_0_6_SHIFT 0 916dfab439fSBenoit Cousson #define OMAP54XX_DIVHS_0_6_WIDTH 0x7 917dfab439fSBenoit Cousson #define OMAP54XX_DIVHS_0_6_MASK (0x7f << 0) 918dfab439fSBenoit Cousson 919dfab439fSBenoit Cousson /* Used by CM_DLL_CTRL */ 920dfab439fSBenoit Cousson #define OMAP54XX_DLL_OVERRIDE_SHIFT 0 921dfab439fSBenoit Cousson #define OMAP54XX_DLL_OVERRIDE_WIDTH 0x1 922dfab439fSBenoit Cousson #define OMAP54XX_DLL_OVERRIDE_MASK (1 << 0) 923dfab439fSBenoit Cousson 924dfab439fSBenoit Cousson /* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */ 925dfab439fSBenoit Cousson #define OMAP54XX_DLL_OVERRIDE_2_2_SHIFT 2 926dfab439fSBenoit Cousson #define OMAP54XX_DLL_OVERRIDE_2_2_WIDTH 0x1 927dfab439fSBenoit Cousson #define OMAP54XX_DLL_OVERRIDE_2_2_MASK (1 << 2) 928dfab439fSBenoit Cousson 929dfab439fSBenoit Cousson /* Used by CM_SHADOW_FREQ_CONFIG1 */ 930dfab439fSBenoit Cousson #define OMAP54XX_DLL_RESET_SHIFT 3 931dfab439fSBenoit Cousson #define OMAP54XX_DLL_RESET_WIDTH 0x1 932dfab439fSBenoit Cousson #define OMAP54XX_DLL_RESET_MASK (1 << 3) 933dfab439fSBenoit Cousson 934dfab439fSBenoit Cousson /* 935dfab439fSBenoit Cousson * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA, 936dfab439fSBenoit Cousson * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO1, 937dfab439fSBenoit Cousson * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB 938dfab439fSBenoit Cousson */ 939dfab439fSBenoit Cousson #define OMAP54XX_DPLL_BYP_CLKSEL_SHIFT 23 940dfab439fSBenoit Cousson #define OMAP54XX_DPLL_BYP_CLKSEL_WIDTH 0x1 941dfab439fSBenoit Cousson #define OMAP54XX_DPLL_BYP_CLKSEL_MASK (1 << 23) 942dfab439fSBenoit Cousson 943dfab439fSBenoit Cousson /* Used by CM_CLKSEL_DPLL_CORE */ 944dfab439fSBenoit Cousson #define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20 945dfab439fSBenoit Cousson #define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_WIDTH 0x1 946dfab439fSBenoit Cousson #define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20) 947dfab439fSBenoit Cousson 948dfab439fSBenoit Cousson /* Used by CM_SHADOW_FREQ_CONFIG1 */ 949dfab439fSBenoit Cousson #define OMAP54XX_DPLL_CORE_DPLL_EN_SHIFT 8 950dfab439fSBenoit Cousson #define OMAP54XX_DPLL_CORE_DPLL_EN_WIDTH 0x3 951dfab439fSBenoit Cousson #define OMAP54XX_DPLL_CORE_DPLL_EN_MASK (0x7 << 8) 952dfab439fSBenoit Cousson 953dfab439fSBenoit Cousson /* Used by CM_SHADOW_FREQ_CONFIG2 */ 954dfab439fSBenoit Cousson #define OMAP54XX_DPLL_CORE_H12_DIV_SHIFT 2 955dfab439fSBenoit Cousson #define OMAP54XX_DPLL_CORE_H12_DIV_WIDTH 0x6 956dfab439fSBenoit Cousson #define OMAP54XX_DPLL_CORE_H12_DIV_MASK (0x3f << 2) 957dfab439fSBenoit Cousson 958dfab439fSBenoit Cousson /* Used by CM_SHADOW_FREQ_CONFIG1 */ 959dfab439fSBenoit Cousson #define OMAP54XX_DPLL_CORE_M2_DIV_SHIFT 11 960dfab439fSBenoit Cousson #define OMAP54XX_DPLL_CORE_M2_DIV_WIDTH 0x5 961dfab439fSBenoit Cousson #define OMAP54XX_DPLL_CORE_M2_DIV_MASK (0x1f << 11) 962dfab439fSBenoit Cousson 963dfab439fSBenoit Cousson /* 964dfab439fSBenoit Cousson * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA, 965dfab439fSBenoit Cousson * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER 966dfab439fSBenoit Cousson */ 967dfab439fSBenoit Cousson #define OMAP54XX_DPLL_DIV_SHIFT 0 968dfab439fSBenoit Cousson #define OMAP54XX_DPLL_DIV_WIDTH 0x7 969dfab439fSBenoit Cousson #define OMAP54XX_DPLL_DIV_MASK (0x7f << 0) 970dfab439fSBenoit Cousson 971dfab439fSBenoit Cousson /* 972dfab439fSBenoit Cousson * Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_UNIPRO1, 973dfab439fSBenoit Cousson * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB 974dfab439fSBenoit Cousson */ 975dfab439fSBenoit Cousson #define OMAP54XX_DPLL_DIV_0_7_SHIFT 0 976dfab439fSBenoit Cousson #define OMAP54XX_DPLL_DIV_0_7_WIDTH 0x8 977dfab439fSBenoit Cousson #define OMAP54XX_DPLL_DIV_0_7_MASK (0xff << 0) 978dfab439fSBenoit Cousson 979dfab439fSBenoit Cousson /* 980dfab439fSBenoit Cousson * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, 981dfab439fSBenoit Cousson * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER 982dfab439fSBenoit Cousson */ 983dfab439fSBenoit Cousson #define OMAP54XX_DPLL_DRIFTGUARD_EN_SHIFT 8 984dfab439fSBenoit Cousson #define OMAP54XX_DPLL_DRIFTGUARD_EN_WIDTH 0x1 985dfab439fSBenoit Cousson #define OMAP54XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8) 986dfab439fSBenoit Cousson 987dfab439fSBenoit Cousson /* 988dfab439fSBenoit Cousson * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, 989dfab439fSBenoit Cousson * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1, 990dfab439fSBenoit Cousson * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB 991dfab439fSBenoit Cousson */ 992dfab439fSBenoit Cousson #define OMAP54XX_DPLL_EN_SHIFT 0 993dfab439fSBenoit Cousson #define OMAP54XX_DPLL_EN_WIDTH 0x3 994dfab439fSBenoit Cousson #define OMAP54XX_DPLL_EN_MASK (0x7 << 0) 995dfab439fSBenoit Cousson 996dfab439fSBenoit Cousson /* 997dfab439fSBenoit Cousson * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, 998dfab439fSBenoit Cousson * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER 999dfab439fSBenoit Cousson */ 1000dfab439fSBenoit Cousson #define OMAP54XX_DPLL_LPMODE_EN_SHIFT 10 1001dfab439fSBenoit Cousson #define OMAP54XX_DPLL_LPMODE_EN_WIDTH 0x1 1002dfab439fSBenoit Cousson #define OMAP54XX_DPLL_LPMODE_EN_MASK (1 << 10) 1003dfab439fSBenoit Cousson 1004dfab439fSBenoit Cousson /* 1005dfab439fSBenoit Cousson * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA, 1006dfab439fSBenoit Cousson * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER 1007dfab439fSBenoit Cousson */ 1008dfab439fSBenoit Cousson #define OMAP54XX_DPLL_MULT_SHIFT 8 1009dfab439fSBenoit Cousson #define OMAP54XX_DPLL_MULT_WIDTH 0xb 1010dfab439fSBenoit Cousson #define OMAP54XX_DPLL_MULT_MASK (0x7ff << 8) 1011dfab439fSBenoit Cousson 1012dfab439fSBenoit Cousson /* 1013dfab439fSBenoit Cousson * Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_UNIPRO1, 1014dfab439fSBenoit Cousson * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB 1015dfab439fSBenoit Cousson */ 1016dfab439fSBenoit Cousson #define OMAP54XX_DPLL_MULT_UNIPRO1_SHIFT 8 1017dfab439fSBenoit Cousson #define OMAP54XX_DPLL_MULT_UNIPRO1_WIDTH 0xc 1018dfab439fSBenoit Cousson #define OMAP54XX_DPLL_MULT_UNIPRO1_MASK (0xfff << 8) 1019dfab439fSBenoit Cousson 1020dfab439fSBenoit Cousson /* 1021dfab439fSBenoit Cousson * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, 1022dfab439fSBenoit Cousson * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER 1023dfab439fSBenoit Cousson */ 1024dfab439fSBenoit Cousson #define OMAP54XX_DPLL_REGM4XEN_SHIFT 11 1025dfab439fSBenoit Cousson #define OMAP54XX_DPLL_REGM4XEN_WIDTH 0x1 1026dfab439fSBenoit Cousson #define OMAP54XX_DPLL_REGM4XEN_MASK (1 << 11) 1027dfab439fSBenoit Cousson 1028dfab439fSBenoit Cousson /* Used by CM_CLKSEL_DPLL_UNIPRO1, CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB */ 1029dfab439fSBenoit Cousson #define OMAP54XX_DPLL_SD_DIV_SHIFT 24 1030dfab439fSBenoit Cousson #define OMAP54XX_DPLL_SD_DIV_WIDTH 0x8 1031dfab439fSBenoit Cousson #define OMAP54XX_DPLL_SD_DIV_MASK (0xff << 24) 1032dfab439fSBenoit Cousson 1033dfab439fSBenoit Cousson /* Used by CM_CLKSEL_DPLL_UNIPRO1, CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB */ 1034dfab439fSBenoit Cousson #define OMAP54XX_DPLL_SELFREQDCO_SHIFT 21 1035dfab439fSBenoit Cousson #define OMAP54XX_DPLL_SELFREQDCO_WIDTH 0x1 1036dfab439fSBenoit Cousson #define OMAP54XX_DPLL_SELFREQDCO_MASK (1 << 21) 1037dfab439fSBenoit Cousson 1038dfab439fSBenoit Cousson /* 1039dfab439fSBenoit Cousson * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, 1040dfab439fSBenoit Cousson * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1, 1041dfab439fSBenoit Cousson * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB 1042dfab439fSBenoit Cousson */ 1043dfab439fSBenoit Cousson #define OMAP54XX_DPLL_SSC_ACK_SHIFT 13 1044dfab439fSBenoit Cousson #define OMAP54XX_DPLL_SSC_ACK_WIDTH 0x1 1045dfab439fSBenoit Cousson #define OMAP54XX_DPLL_SSC_ACK_MASK (1 << 13) 1046dfab439fSBenoit Cousson 1047dfab439fSBenoit Cousson /* 1048dfab439fSBenoit Cousson * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, 1049dfab439fSBenoit Cousson * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1, 1050dfab439fSBenoit Cousson * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB 1051dfab439fSBenoit Cousson */ 1052dfab439fSBenoit Cousson #define OMAP54XX_DPLL_SSC_DOWNSPREAD_SHIFT 14 1053dfab439fSBenoit Cousson #define OMAP54XX_DPLL_SSC_DOWNSPREAD_WIDTH 0x1 1054dfab439fSBenoit Cousson #define OMAP54XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) 1055dfab439fSBenoit Cousson 1056dfab439fSBenoit Cousson /* 1057dfab439fSBenoit Cousson * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, 1058dfab439fSBenoit Cousson * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1, 1059dfab439fSBenoit Cousson * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB 1060dfab439fSBenoit Cousson */ 1061dfab439fSBenoit Cousson #define OMAP54XX_DPLL_SSC_EN_SHIFT 12 1062dfab439fSBenoit Cousson #define OMAP54XX_DPLL_SSC_EN_WIDTH 0x1 1063dfab439fSBenoit Cousson #define OMAP54XX_DPLL_SSC_EN_MASK (1 << 12) 1064dfab439fSBenoit Cousson 1065dfab439fSBenoit Cousson /* Used by CM_L4CFG_DYNAMICDEP */ 1066dfab439fSBenoit Cousson #define OMAP54XX_DSP_DYNDEP_SHIFT 1 1067dfab439fSBenoit Cousson #define OMAP54XX_DSP_DYNDEP_WIDTH 0x1 1068dfab439fSBenoit Cousson #define OMAP54XX_DSP_DYNDEP_MASK (1 << 1) 1069dfab439fSBenoit Cousson 1070dfab439fSBenoit Cousson /* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */ 1071dfab439fSBenoit Cousson #define OMAP54XX_DSP_STATDEP_SHIFT 1 1072dfab439fSBenoit Cousson #define OMAP54XX_DSP_STATDEP_WIDTH 0x1 1073dfab439fSBenoit Cousson #define OMAP54XX_DSP_STATDEP_MASK (1 << 1) 1074dfab439fSBenoit Cousson 1075dfab439fSBenoit Cousson /* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ 1076dfab439fSBenoit Cousson #define OMAP54XX_DSS_DYNDEP_SHIFT 8 1077dfab439fSBenoit Cousson #define OMAP54XX_DSS_DYNDEP_WIDTH 0x1 1078dfab439fSBenoit Cousson #define OMAP54XX_DSS_DYNDEP_MASK (1 << 8) 1079dfab439fSBenoit Cousson 1080dfab439fSBenoit Cousson /* Used by CM_DMA_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */ 1081dfab439fSBenoit Cousson #define OMAP54XX_DSS_STATDEP_SHIFT 8 1082dfab439fSBenoit Cousson #define OMAP54XX_DSS_STATDEP_WIDTH 0x1 1083dfab439fSBenoit Cousson #define OMAP54XX_DSS_STATDEP_MASK (1 << 8) 1084dfab439fSBenoit Cousson 1085dfab439fSBenoit Cousson /* 1086dfab439fSBenoit Cousson * Used by CM_C2C_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, 1087dfab439fSBenoit Cousson * CM_MIPIEXT_DYNAMICDEP, CM_MPU_DYNAMICDEP 1088dfab439fSBenoit Cousson */ 1089dfab439fSBenoit Cousson #define OMAP54XX_EMIF_DYNDEP_SHIFT 4 1090dfab439fSBenoit Cousson #define OMAP54XX_EMIF_DYNDEP_WIDTH 0x1 1091dfab439fSBenoit Cousson #define OMAP54XX_EMIF_DYNDEP_MASK (1 << 4) 1092dfab439fSBenoit Cousson 1093dfab439fSBenoit Cousson /* 1094dfab439fSBenoit Cousson * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP, 1095dfab439fSBenoit Cousson * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP, 1096dfab439fSBenoit Cousson * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, 1097dfab439fSBenoit Cousson * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP 1098dfab439fSBenoit Cousson */ 1099dfab439fSBenoit Cousson #define OMAP54XX_EMIF_STATDEP_SHIFT 4 1100dfab439fSBenoit Cousson #define OMAP54XX_EMIF_STATDEP_WIDTH 0x1 1101dfab439fSBenoit Cousson #define OMAP54XX_EMIF_STATDEP_MASK (1 << 4) 1102dfab439fSBenoit Cousson 1103dfab439fSBenoit Cousson /* Used by CM_SHADOW_FREQ_CONFIG1 */ 1104dfab439fSBenoit Cousson #define OMAP54XX_FREQ_UPDATE_SHIFT 0 1105dfab439fSBenoit Cousson #define OMAP54XX_FREQ_UPDATE_WIDTH 0x1 1106dfab439fSBenoit Cousson #define OMAP54XX_FREQ_UPDATE_MASK (1 << 0) 1107dfab439fSBenoit Cousson 1108dfab439fSBenoit Cousson /* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ 1109dfab439fSBenoit Cousson #define OMAP54XX_FUNC_SHIFT 16 1110dfab439fSBenoit Cousson #define OMAP54XX_FUNC_WIDTH 0xc 1111dfab439fSBenoit Cousson #define OMAP54XX_FUNC_MASK (0xfff << 16) 1112dfab439fSBenoit Cousson 1113dfab439fSBenoit Cousson /* Used by CM_SHADOW_FREQ_CONFIG2 */ 1114dfab439fSBenoit Cousson #define OMAP54XX_GPMC_FREQ_UPDATE_SHIFT 0 1115dfab439fSBenoit Cousson #define OMAP54XX_GPMC_FREQ_UPDATE_WIDTH 0x1 1116dfab439fSBenoit Cousson #define OMAP54XX_GPMC_FREQ_UPDATE_MASK (1 << 0) 1117dfab439fSBenoit Cousson 1118dfab439fSBenoit Cousson /* Used by CM_L3MAIN2_DYNAMICDEP */ 1119dfab439fSBenoit Cousson #define OMAP54XX_GPU_DYNDEP_SHIFT 10 1120dfab439fSBenoit Cousson #define OMAP54XX_GPU_DYNDEP_WIDTH 0x1 1121dfab439fSBenoit Cousson #define OMAP54XX_GPU_DYNDEP_MASK (1 << 10) 1122dfab439fSBenoit Cousson 1123dfab439fSBenoit Cousson /* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */ 1124dfab439fSBenoit Cousson #define OMAP54XX_GPU_STATDEP_SHIFT 10 1125dfab439fSBenoit Cousson #define OMAP54XX_GPU_STATDEP_WIDTH 0x1 1126dfab439fSBenoit Cousson #define OMAP54XX_GPU_STATDEP_MASK (1 << 10) 1127dfab439fSBenoit Cousson 1128dfab439fSBenoit Cousson /* 1129dfab439fSBenoit Cousson * Used by CM_ABE_AESS_CLKCTRL, CM_ABE_DMIC_CLKCTRL, CM_ABE_L4_ABE_CLKCTRL, 1130dfab439fSBenoit Cousson * CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, CM_ABE_MCBSP2_CLKCTRL, 1131dfab439fSBenoit Cousson * CM_ABE_MCBSP3_CLKCTRL, CM_ABE_MCPDM_CLKCTRL, CM_ABE_SLIMBUS1_CLKCTRL, 1132dfab439fSBenoit Cousson * CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL, 1133dfab439fSBenoit Cousson * CM_ABE_TIMER8_CLKCTRL, CM_ABE_WD_TIMER3_CLKCTRL, CM_C2C_C2C_CLKCTRL, 1134dfab439fSBenoit Cousson * CM_C2C_C2C_OCP_FW_CLKCTRL, CM_C2C_MODEM_ICR_CLKCTRL, CM_CAM_CAL_CLKCTRL, 1135dfab439fSBenoit Cousson * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL, 1136dfab439fSBenoit Cousson * CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL, 1137dfab439fSBenoit Cousson * CM_COREAON_SMARTREFLEX_MM_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL, 1138dfab439fSBenoit Cousson * CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL, 1139dfab439fSBenoit Cousson * CM_DSP_DSP_CLKCTRL, CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, 1140dfab439fSBenoit Cousson * CM_EMIF_DMM_CLKCTRL, CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL, 1141dfab439fSBenoit Cousson * CM_EMIF_EMIF_OCP_FW_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, 1142dfab439fSBenoit Cousson * CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL, 1143dfab439fSBenoit Cousson * CM_IVA_IVA_CLKCTRL, CM_IVA_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, 1144dfab439fSBenoit Cousson * CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, 1145dfab439fSBenoit Cousson * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MPHY_UNIPRO2_CLKCTRL, 1146dfab439fSBenoit Cousson * CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL, 1147dfab439fSBenoit Cousson * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_UNIPRO2_CLKCTRL, 1148dfab439fSBenoit Cousson * CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_OTG_SS_CLKCTRL, 1149dfab439fSBenoit Cousson * CM_L3INIT_USB_TLL_HS_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL, 1150dfab439fSBenoit Cousson * CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, 1151dfab439fSBenoit Cousson * CM_L3INSTR_L3_MAIN_3_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL, 1152dfab439fSBenoit Cousson * CM_L3MAIN1_L3_MAIN_1_CLKCTRL, CM_L3MAIN2_GPMC_CLKCTRL, 1153dfab439fSBenoit Cousson * CM_L3MAIN2_L3_MAIN_2_CLKCTRL, CM_L3MAIN2_OCMC_RAM_CLKCTRL, 1154dfab439fSBenoit Cousson * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, 1155dfab439fSBenoit Cousson * CM_L4CFG_OCP2SCP2_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, 1156dfab439fSBenoit Cousson * CM_L4CFG_SPINLOCK_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, 1157dfab439fSBenoit Cousson * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, 1158dfab439fSBenoit Cousson * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL, 1159dfab439fSBenoit Cousson * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, 1160dfab439fSBenoit Cousson * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, 1161dfab439fSBenoit Cousson * CM_L4PER_L4_PER_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, 1162dfab439fSBenoit Cousson * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL, 1163dfab439fSBenoit Cousson * CM_L4PER_MMC4_CLKCTRL, CM_L4PER_MMC5_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL, 1164dfab439fSBenoit Cousson * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL, 1165dfab439fSBenoit Cousson * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_L4PER_UART1_CLKCTRL, 1166dfab439fSBenoit Cousson * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, 1167dfab439fSBenoit Cousson * CM_L4PER_UART5_CLKCTRL, CM_L4PER_UART6_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, 1168dfab439fSBenoit Cousson * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, 1169dfab439fSBenoit Cousson * CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, 1170dfab439fSBenoit Cousson * CM_L4SEC_SHA2MD5_CLKCTRL, CM_MIPIEXT_LLI_CLKCTRL, 1171dfab439fSBenoit Cousson * CM_MIPIEXT_LLI_OCP_FW_CLKCTRL, CM_MIPIEXT_MPHY_CLKCTRL, CM_MPU_MPU_CLKCTRL, 1172dfab439fSBenoit Cousson * CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL, 1173dfab439fSBenoit Cousson * CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL, 1174dfab439fSBenoit Cousson * CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL, 1175dfab439fSBenoit Cousson * CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL, 1176dfab439fSBenoit Cousson * CM_WKUPAON_WD_TIMER1_CLKCTRL, CM_WKUPAON_WD_TIMER2_CLKCTRL 1177dfab439fSBenoit Cousson */ 1178dfab439fSBenoit Cousson #define OMAP54XX_IDLEST_SHIFT 16 1179dfab439fSBenoit Cousson #define OMAP54XX_IDLEST_WIDTH 0x2 1180dfab439fSBenoit Cousson #define OMAP54XX_IDLEST_MASK (0x3 << 16) 1181dfab439fSBenoit Cousson 1182dfab439fSBenoit Cousson /* Used by CM_L3MAIN2_DYNAMICDEP */ 1183dfab439fSBenoit Cousson #define OMAP54XX_IPU_DYNDEP_SHIFT 0 1184dfab439fSBenoit Cousson #define OMAP54XX_IPU_DYNDEP_WIDTH 0x1 1185dfab439fSBenoit Cousson #define OMAP54XX_IPU_DYNDEP_MASK (1 << 0) 1186dfab439fSBenoit Cousson 1187dfab439fSBenoit Cousson /* Used by CM_DMA_STATICDEP, CM_MPU_STATICDEP */ 1188dfab439fSBenoit Cousson #define OMAP54XX_IPU_STATDEP_SHIFT 0 1189dfab439fSBenoit Cousson #define OMAP54XX_IPU_STATDEP_WIDTH 0x1 1190dfab439fSBenoit Cousson #define OMAP54XX_IPU_STATDEP_MASK (1 << 0) 1191dfab439fSBenoit Cousson 1192dfab439fSBenoit Cousson /* Used by CM_DSP_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP */ 1193dfab439fSBenoit Cousson #define OMAP54XX_IVA_DYNDEP_SHIFT 2 1194dfab439fSBenoit Cousson #define OMAP54XX_IVA_DYNDEP_WIDTH 0x1 1195dfab439fSBenoit Cousson #define OMAP54XX_IVA_DYNDEP_MASK (1 << 2) 1196dfab439fSBenoit Cousson 1197dfab439fSBenoit Cousson /* 1198dfab439fSBenoit Cousson * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP, 1199dfab439fSBenoit Cousson * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP, 1200dfab439fSBenoit Cousson * CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP 1201dfab439fSBenoit Cousson */ 1202dfab439fSBenoit Cousson #define OMAP54XX_IVA_STATDEP_SHIFT 2 1203dfab439fSBenoit Cousson #define OMAP54XX_IVA_STATDEP_WIDTH 0x1 1204dfab439fSBenoit Cousson #define OMAP54XX_IVA_STATDEP_MASK (1 << 2) 1205dfab439fSBenoit Cousson 1206dfab439fSBenoit Cousson /* Used by CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ 1207dfab439fSBenoit Cousson #define OMAP54XX_L3INIT_DYNDEP_SHIFT 7 1208dfab439fSBenoit Cousson #define OMAP54XX_L3INIT_DYNDEP_WIDTH 0x1 1209dfab439fSBenoit Cousson #define OMAP54XX_L3INIT_DYNDEP_MASK (1 << 7) 1210dfab439fSBenoit Cousson 1211dfab439fSBenoit Cousson /* 1212dfab439fSBenoit Cousson * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP, 1213dfab439fSBenoit Cousson * CM_IPU_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP 1214dfab439fSBenoit Cousson */ 1215dfab439fSBenoit Cousson #define OMAP54XX_L3INIT_STATDEP_SHIFT 7 1216dfab439fSBenoit Cousson #define OMAP54XX_L3INIT_STATDEP_WIDTH 0x1 1217dfab439fSBenoit Cousson #define OMAP54XX_L3INIT_STATDEP_MASK (1 << 7) 1218dfab439fSBenoit Cousson 1219dfab439fSBenoit Cousson /* 1220dfab439fSBenoit Cousson * Used by CM_DSP_DYNAMICDEP, CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, 1221dfab439fSBenoit Cousson * CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP 1222dfab439fSBenoit Cousson */ 1223dfab439fSBenoit Cousson #define OMAP54XX_L3MAIN1_DYNDEP_SHIFT 5 1224dfab439fSBenoit Cousson #define OMAP54XX_L3MAIN1_DYNDEP_WIDTH 0x1 1225dfab439fSBenoit Cousson #define OMAP54XX_L3MAIN1_DYNDEP_MASK (1 << 5) 1226dfab439fSBenoit Cousson 1227dfab439fSBenoit Cousson /* 1228dfab439fSBenoit Cousson * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP, 1229dfab439fSBenoit Cousson * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP, 1230dfab439fSBenoit Cousson * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, 1231dfab439fSBenoit Cousson * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP 1232dfab439fSBenoit Cousson */ 1233dfab439fSBenoit Cousson #define OMAP54XX_L3MAIN1_STATDEP_SHIFT 5 1234dfab439fSBenoit Cousson #define OMAP54XX_L3MAIN1_STATDEP_WIDTH 0x1 1235dfab439fSBenoit Cousson #define OMAP54XX_L3MAIN1_STATDEP_MASK (1 << 5) 1236dfab439fSBenoit Cousson 1237dfab439fSBenoit Cousson /* 1238dfab439fSBenoit Cousson * Used by CM_C2C_DYNAMICDEP, CM_CAM_DYNAMICDEP, CM_DMA_DYNAMICDEP, 1239dfab439fSBenoit Cousson * CM_DSS_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GPU_DYNAMICDEP, CM_IPU_DYNAMICDEP, 1240dfab439fSBenoit Cousson * CM_IVA_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, 1241dfab439fSBenoit Cousson * CM_L4CFG_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_MIPIEXT_DYNAMICDEP 1242dfab439fSBenoit Cousson */ 1243dfab439fSBenoit Cousson #define OMAP54XX_L3MAIN2_DYNDEP_SHIFT 6 1244dfab439fSBenoit Cousson #define OMAP54XX_L3MAIN2_DYNDEP_WIDTH 0x1 1245dfab439fSBenoit Cousson #define OMAP54XX_L3MAIN2_DYNDEP_MASK (1 << 6) 1246dfab439fSBenoit Cousson 1247dfab439fSBenoit Cousson /* 1248dfab439fSBenoit Cousson * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP, 1249dfab439fSBenoit Cousson * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP, 1250dfab439fSBenoit Cousson * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, 1251dfab439fSBenoit Cousson * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP 1252dfab439fSBenoit Cousson */ 1253dfab439fSBenoit Cousson #define OMAP54XX_L3MAIN2_STATDEP_SHIFT 6 1254dfab439fSBenoit Cousson #define OMAP54XX_L3MAIN2_STATDEP_WIDTH 0x1 1255dfab439fSBenoit Cousson #define OMAP54XX_L3MAIN2_STATDEP_MASK (1 << 6) 1256dfab439fSBenoit Cousson 1257dfab439fSBenoit Cousson /* Used by CM_L3MAIN1_DYNAMICDEP */ 1258dfab439fSBenoit Cousson #define OMAP54XX_L4CFG_DYNDEP_SHIFT 12 1259dfab439fSBenoit Cousson #define OMAP54XX_L4CFG_DYNDEP_WIDTH 0x1 1260dfab439fSBenoit Cousson #define OMAP54XX_L4CFG_DYNDEP_MASK (1 << 12) 1261dfab439fSBenoit Cousson 1262dfab439fSBenoit Cousson /* 1263dfab439fSBenoit Cousson * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP, 1264dfab439fSBenoit Cousson * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP 1265dfab439fSBenoit Cousson */ 1266dfab439fSBenoit Cousson #define OMAP54XX_L4CFG_STATDEP_SHIFT 12 1267dfab439fSBenoit Cousson #define OMAP54XX_L4CFG_STATDEP_WIDTH 0x1 1268dfab439fSBenoit Cousson #define OMAP54XX_L4CFG_STATDEP_MASK (1 << 12) 1269dfab439fSBenoit Cousson 1270dfab439fSBenoit Cousson /* Used by CM_L3MAIN2_DYNAMICDEP */ 1271dfab439fSBenoit Cousson #define OMAP54XX_L4PER_DYNDEP_SHIFT 13 1272dfab439fSBenoit Cousson #define OMAP54XX_L4PER_DYNDEP_WIDTH 0x1 1273dfab439fSBenoit Cousson #define OMAP54XX_L4PER_DYNDEP_MASK (1 << 13) 1274dfab439fSBenoit Cousson 1275dfab439fSBenoit Cousson /* 1276dfab439fSBenoit Cousson * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP, 1277dfab439fSBenoit Cousson * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, 1278dfab439fSBenoit Cousson * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP 1279dfab439fSBenoit Cousson */ 1280dfab439fSBenoit Cousson #define OMAP54XX_L4PER_STATDEP_SHIFT 13 1281dfab439fSBenoit Cousson #define OMAP54XX_L4PER_STATDEP_WIDTH 0x1 1282dfab439fSBenoit Cousson #define OMAP54XX_L4PER_STATDEP_MASK (1 << 13) 1283dfab439fSBenoit Cousson 1284dfab439fSBenoit Cousson /* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ 1285dfab439fSBenoit Cousson #define OMAP54XX_L4SEC_DYNDEP_SHIFT 14 1286dfab439fSBenoit Cousson #define OMAP54XX_L4SEC_DYNDEP_WIDTH 0x1 1287dfab439fSBenoit Cousson #define OMAP54XX_L4SEC_DYNDEP_MASK (1 << 14) 1288dfab439fSBenoit Cousson 1289dfab439fSBenoit Cousson /* 1290dfab439fSBenoit Cousson * Used by CM_DMA_STATICDEP, CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, 1291dfab439fSBenoit Cousson * CM_MPU_STATICDEP 1292dfab439fSBenoit Cousson */ 1293dfab439fSBenoit Cousson #define OMAP54XX_L4SEC_STATDEP_SHIFT 14 1294dfab439fSBenoit Cousson #define OMAP54XX_L4SEC_STATDEP_WIDTH 0x1 1295dfab439fSBenoit Cousson #define OMAP54XX_L4SEC_STATDEP_MASK (1 << 14) 1296dfab439fSBenoit Cousson 1297dfab439fSBenoit Cousson /* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ 1298dfab439fSBenoit Cousson #define OMAP54XX_MIPIEXT_DYNDEP_SHIFT 21 1299dfab439fSBenoit Cousson #define OMAP54XX_MIPIEXT_DYNDEP_WIDTH 0x1 1300dfab439fSBenoit Cousson #define OMAP54XX_MIPIEXT_DYNDEP_MASK (1 << 21) 1301dfab439fSBenoit Cousson 1302dfab439fSBenoit Cousson /* Used by CM_MPU_STATICDEP */ 1303dfab439fSBenoit Cousson #define OMAP54XX_MIPIEXT_STATDEP_SHIFT 21 1304dfab439fSBenoit Cousson #define OMAP54XX_MIPIEXT_STATDEP_WIDTH 0x1 1305dfab439fSBenoit Cousson #define OMAP54XX_MIPIEXT_STATDEP_MASK (1 << 21) 1306dfab439fSBenoit Cousson 1307dfab439fSBenoit Cousson /* 1308dfab439fSBenoit Cousson * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, 1309dfab439fSBenoit Cousson * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU, 1310dfab439fSBenoit Cousson * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO1, 1311dfab439fSBenoit Cousson * CM_SSC_MODFREQDIV_DPLL_UNIPRO2, CM_SSC_MODFREQDIV_DPLL_USB 1312dfab439fSBenoit Cousson */ 1313dfab439fSBenoit Cousson #define OMAP54XX_MODFREQDIV_EXPONENT_SHIFT 8 1314dfab439fSBenoit Cousson #define OMAP54XX_MODFREQDIV_EXPONENT_WIDTH 0x3 1315dfab439fSBenoit Cousson #define OMAP54XX_MODFREQDIV_EXPONENT_MASK (0x7 << 8) 1316dfab439fSBenoit Cousson 1317dfab439fSBenoit Cousson /* 1318dfab439fSBenoit Cousson * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, 1319dfab439fSBenoit Cousson * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU, 1320dfab439fSBenoit Cousson * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO1, 1321dfab439fSBenoit Cousson * CM_SSC_MODFREQDIV_DPLL_UNIPRO2, CM_SSC_MODFREQDIV_DPLL_USB 1322dfab439fSBenoit Cousson */ 1323dfab439fSBenoit Cousson #define OMAP54XX_MODFREQDIV_MANTISSA_SHIFT 0 1324dfab439fSBenoit Cousson #define OMAP54XX_MODFREQDIV_MANTISSA_WIDTH 0x7 1325dfab439fSBenoit Cousson #define OMAP54XX_MODFREQDIV_MANTISSA_MASK (0x7f << 0) 1326dfab439fSBenoit Cousson 1327dfab439fSBenoit Cousson /* 1328dfab439fSBenoit Cousson * Used by CM_ABE_AESS_CLKCTRL, CM_ABE_DMIC_CLKCTRL, CM_ABE_L4_ABE_CLKCTRL, 1329dfab439fSBenoit Cousson * CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, CM_ABE_MCBSP2_CLKCTRL, 1330dfab439fSBenoit Cousson * CM_ABE_MCBSP3_CLKCTRL, CM_ABE_MCPDM_CLKCTRL, CM_ABE_SLIMBUS1_CLKCTRL, 1331dfab439fSBenoit Cousson * CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL, 1332dfab439fSBenoit Cousson * CM_ABE_TIMER8_CLKCTRL, CM_ABE_WD_TIMER3_CLKCTRL, CM_C2C_C2C_CLKCTRL, 1333dfab439fSBenoit Cousson * CM_C2C_C2C_OCP_FW_CLKCTRL, CM_C2C_MODEM_ICR_CLKCTRL, CM_CAM_CAL_CLKCTRL, 1334dfab439fSBenoit Cousson * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL, 1335dfab439fSBenoit Cousson * CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL, 1336dfab439fSBenoit Cousson * CM_COREAON_SMARTREFLEX_MM_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL, 1337dfab439fSBenoit Cousson * CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL, 1338dfab439fSBenoit Cousson * CM_DSP_DSP_CLKCTRL, CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, 1339dfab439fSBenoit Cousson * CM_EMIF_DMM_CLKCTRL, CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL, 1340dfab439fSBenoit Cousson * CM_EMIF_EMIF_OCP_FW_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, 1341dfab439fSBenoit Cousson * CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL, 1342dfab439fSBenoit Cousson * CM_IVA_IVA_CLKCTRL, CM_IVA_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, 1343dfab439fSBenoit Cousson * CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, 1344dfab439fSBenoit Cousson * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MPHY_UNIPRO2_CLKCTRL, 1345dfab439fSBenoit Cousson * CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL, 1346dfab439fSBenoit Cousson * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_UNIPRO2_CLKCTRL, 1347dfab439fSBenoit Cousson * CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_OTG_SS_CLKCTRL, 1348dfab439fSBenoit Cousson * CM_L3INIT_USB_TLL_HS_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL, 1349dfab439fSBenoit Cousson * CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, 1350dfab439fSBenoit Cousson * CM_L3INSTR_L3_MAIN_3_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL, 1351dfab439fSBenoit Cousson * CM_L3MAIN1_L3_MAIN_1_CLKCTRL, CM_L3MAIN2_GPMC_CLKCTRL, 1352dfab439fSBenoit Cousson * CM_L3MAIN2_L3_MAIN_2_CLKCTRL, CM_L3MAIN2_OCMC_RAM_CLKCTRL, 1353dfab439fSBenoit Cousson * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, 1354dfab439fSBenoit Cousson * CM_L4CFG_OCP2SCP2_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, 1355dfab439fSBenoit Cousson * CM_L4CFG_SPINLOCK_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, 1356dfab439fSBenoit Cousson * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, 1357dfab439fSBenoit Cousson * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL, 1358dfab439fSBenoit Cousson * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, 1359dfab439fSBenoit Cousson * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, 1360dfab439fSBenoit Cousson * CM_L4PER_L4_PER_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, 1361dfab439fSBenoit Cousson * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL, 1362dfab439fSBenoit Cousson * CM_L4PER_MMC4_CLKCTRL, CM_L4PER_MMC5_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL, 1363dfab439fSBenoit Cousson * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL, 1364dfab439fSBenoit Cousson * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_L4PER_UART1_CLKCTRL, 1365dfab439fSBenoit Cousson * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, 1366dfab439fSBenoit Cousson * CM_L4PER_UART5_CLKCTRL, CM_L4PER_UART6_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, 1367dfab439fSBenoit Cousson * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, 1368dfab439fSBenoit Cousson * CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, 1369dfab439fSBenoit Cousson * CM_L4SEC_SHA2MD5_CLKCTRL, CM_MIPIEXT_LLI_CLKCTRL, 1370dfab439fSBenoit Cousson * CM_MIPIEXT_LLI_OCP_FW_CLKCTRL, CM_MIPIEXT_MPHY_CLKCTRL, CM_MPU_MPU_CLKCTRL, 1371dfab439fSBenoit Cousson * CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL, 1372dfab439fSBenoit Cousson * CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL, 1373dfab439fSBenoit Cousson * CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL, 1374dfab439fSBenoit Cousson * CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL, 1375dfab439fSBenoit Cousson * CM_WKUPAON_WD_TIMER1_CLKCTRL, CM_WKUPAON_WD_TIMER2_CLKCTRL 1376dfab439fSBenoit Cousson */ 1377dfab439fSBenoit Cousson #define OMAP54XX_MODULEMODE_SHIFT 0 1378dfab439fSBenoit Cousson #define OMAP54XX_MODULEMODE_WIDTH 0x2 1379dfab439fSBenoit Cousson #define OMAP54XX_MODULEMODE_MASK (0x3 << 0) 1380dfab439fSBenoit Cousson 1381dfab439fSBenoit Cousson /* Used by CM_L4CFG_DYNAMICDEP */ 1382dfab439fSBenoit Cousson #define OMAP54XX_MPU_DYNDEP_SHIFT 19 1383dfab439fSBenoit Cousson #define OMAP54XX_MPU_DYNDEP_WIDTH 0x1 1384dfab439fSBenoit Cousson #define OMAP54XX_MPU_DYNDEP_MASK (1 << 19) 1385dfab439fSBenoit Cousson 1386dfab439fSBenoit Cousson /* Used by CM_DSS_DSS_CLKCTRL */ 1387dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_SHIFT 11 1388dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_WIDTH 0x1 1389dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_MASK (1 << 11) 1390dfab439fSBenoit Cousson 1391dfab439fSBenoit Cousson /* Renamed from OPTFCLKEN_32KHZ_CLK Used by CM_L3INIT_MMC1_CLKCTRL */ 1392dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_SHIFT 8 1393dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_WIDTH 0x1 1394dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_MASK (1 << 8) 1395dfab439fSBenoit Cousson 1396dfab439fSBenoit Cousson /* Used by CM_DSS_DSS_CLKCTRL */ 1397dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_48MHZ_CLK_SHIFT 9 1398dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_48MHZ_CLK_WIDTH 0x1 1399dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9) 1400dfab439fSBenoit Cousson 1401dfab439fSBenoit Cousson /* Used by CM_COREAON_USB_PHY_CORE_CLKCTRL */ 1402dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_CLK32K_SHIFT 8 1403dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_CLK32K_WIDTH 0x1 1404dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_CLK32K_MASK (1 << 8) 1405dfab439fSBenoit Cousson 1406dfab439fSBenoit Cousson /* Used by CM_CAM_ISS_CLKCTRL */ 1407dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_CTRLCLK_SHIFT 8 1408dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_CTRLCLK_WIDTH 0x1 1409dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_CTRLCLK_MASK (1 << 8) 1410dfab439fSBenoit Cousson 1411dfab439fSBenoit Cousson /* 1412dfab439fSBenoit Cousson * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, 1413dfab439fSBenoit Cousson * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, 1414dfab439fSBenoit Cousson * CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL, CM_WKUPAON_GPIO1_CLKCTRL 1415dfab439fSBenoit Cousson */ 1416dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_DBCLK_SHIFT 8 1417dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_DBCLK_WIDTH 0x1 1418dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_DBCLK_MASK (1 << 8) 1419dfab439fSBenoit Cousson 1420dfab439fSBenoit Cousson /* Used by CM_EMIF_EMIF_DLL_CLKCTRL */ 1421dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_DLL_CLK_SHIFT 8 1422dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_DLL_CLK_WIDTH 0x1 1423dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_DLL_CLK_MASK (1 << 8) 1424dfab439fSBenoit Cousson 1425dfab439fSBenoit Cousson /* Used by CM_DSS_DSS_CLKCTRL */ 1426dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_DSSCLK_SHIFT 8 1427dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_DSSCLK_WIDTH 0x1 1428dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_DSSCLK_MASK (1 << 8) 1429dfab439fSBenoit Cousson 1430dfab439fSBenoit Cousson /* Used by CM_ABE_SLIMBUS1_CLKCTRL */ 1431dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_FCLK0_SHIFT 8 1432dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_FCLK0_WIDTH 0x1 1433dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_FCLK0_MASK (1 << 8) 1434dfab439fSBenoit Cousson 1435dfab439fSBenoit Cousson /* Used by CM_ABE_SLIMBUS1_CLKCTRL */ 1436dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_FCLK1_SHIFT 9 1437dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_FCLK1_WIDTH 0x1 1438dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_FCLK1_MASK (1 << 9) 1439dfab439fSBenoit Cousson 1440dfab439fSBenoit Cousson /* Used by CM_ABE_SLIMBUS1_CLKCTRL */ 1441dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_FCLK2_SHIFT 10 1442dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_FCLK2_WIDTH 0x1 1443dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_FCLK2_MASK (1 << 10) 1444dfab439fSBenoit Cousson 1445dfab439fSBenoit Cousson /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ 1446dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_SHIFT 15 1447dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_WIDTH 0x1 1448dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_MASK (1 << 15) 1449dfab439fSBenoit Cousson 1450dfab439fSBenoit Cousson /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ 1451dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 1452dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_WIDTH 0x1 1453dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13) 1454dfab439fSBenoit Cousson 1455dfab439fSBenoit Cousson /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ 1456dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 1457dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_WIDTH 0x1 1458dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14) 1459dfab439fSBenoit Cousson 1460dfab439fSBenoit Cousson /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ 1461dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_SHIFT 7 1462dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_WIDTH 0x1 1463dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_MASK (1 << 7) 1464dfab439fSBenoit Cousson 1465dfab439fSBenoit Cousson /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ 1466dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 1467dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_WIDTH 0x1 1468dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11) 1469dfab439fSBenoit Cousson 1470dfab439fSBenoit Cousson /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ 1471dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 1472dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_WIDTH 0x1 1473dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12) 1474dfab439fSBenoit Cousson 1475dfab439fSBenoit Cousson /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ 1476dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_SHIFT 6 1477dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_WIDTH 0x1 1478dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_MASK (1 << 6) 1479dfab439fSBenoit Cousson 1480dfab439fSBenoit Cousson /* Used by CM_L3INIT_USB_OTG_SS_CLKCTRL */ 1481dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_REFCLK960M_SHIFT 8 1482dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_REFCLK960M_WIDTH 0x1 1483dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_REFCLK960M_MASK (1 << 8) 1484dfab439fSBenoit Cousson 1485dfab439fSBenoit Cousson /* Used by CM_L3INIT_SATA_CLKCTRL */ 1486dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_REF_CLK_SHIFT 8 1487dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_REF_CLK_WIDTH 0x1 1488dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_REF_CLK_MASK (1 << 8) 1489dfab439fSBenoit Cousson 1490dfab439fSBenoit Cousson /* Used by CM_WKUPAON_SCRM_CLKCTRL */ 1491dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_SCRM_CORE_SHIFT 8 1492dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_SCRM_CORE_WIDTH 0x1 1493dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_SCRM_CORE_MASK (1 << 8) 1494dfab439fSBenoit Cousson 1495dfab439fSBenoit Cousson /* Used by CM_WKUPAON_SCRM_CLKCTRL */ 1496dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_SCRM_PER_SHIFT 9 1497dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_SCRM_PER_WIDTH 0x1 1498dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_SCRM_PER_MASK (1 << 9) 1499dfab439fSBenoit Cousson 1500dfab439fSBenoit Cousson /* Used by CM_ABE_SLIMBUS1_CLKCTRL */ 1501dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_SHIFT 11 1502dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_WIDTH 0x1 1503dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_MASK (1 << 11) 1504dfab439fSBenoit Cousson 1505dfab439fSBenoit Cousson /* Used by CM_DSS_DSS_CLKCTRL */ 1506dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_SYS_CLK_SHIFT 10 1507dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_SYS_CLK_WIDTH 0x1 1508dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_SYS_CLK_MASK (1 << 10) 1509dfab439fSBenoit Cousson 1510dfab439fSBenoit Cousson /* Used by CM_MIPIEXT_LLI_CLKCTRL */ 1511dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_TXPHY_CLK_SHIFT 8 1512dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_TXPHY_CLK_WIDTH 0x1 1513dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_TXPHY_CLK_MASK (1 << 8) 1514dfab439fSBenoit Cousson 1515dfab439fSBenoit Cousson /* Used by CM_MIPIEXT_LLI_CLKCTRL */ 1516dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_SHIFT 9 1517dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_WIDTH 0x1 1518dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_MASK (1 << 9) 1519dfab439fSBenoit Cousson 1520dfab439fSBenoit Cousson /* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */ 1521dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 1522dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_WIDTH 0x1 1523dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8) 1524dfab439fSBenoit Cousson 1525dfab439fSBenoit Cousson /* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */ 1526dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 1527dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_WIDTH 0x1 1528dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9) 1529dfab439fSBenoit Cousson 1530dfab439fSBenoit Cousson /* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */ 1531dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 1532dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_WIDTH 0x1 1533dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10) 1534dfab439fSBenoit Cousson 1535dfab439fSBenoit Cousson /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ 1536dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 1537dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_WIDTH 0x1 1538dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8) 1539dfab439fSBenoit Cousson 1540dfab439fSBenoit Cousson /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ 1541dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 1542dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_WIDTH 0x1 1543dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9) 1544dfab439fSBenoit Cousson 1545dfab439fSBenoit Cousson /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ 1546dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 1547dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_WIDTH 0x1 1548dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10) 1549dfab439fSBenoit Cousson 1550dfab439fSBenoit Cousson /* Used by CM_CORE_AON_DEBUG_OUT, CM_CORE_DEBUG_OUT */ 1551dfab439fSBenoit Cousson #define OMAP54XX_OUTPUT_SHIFT 0 1552dfab439fSBenoit Cousson #define OMAP54XX_OUTPUT_WIDTH 0x20 1553dfab439fSBenoit Cousson #define OMAP54XX_OUTPUT_MASK (0xffffffff << 0) 1554dfab439fSBenoit Cousson 1555dfab439fSBenoit Cousson /* Used by CM_CLKSEL_ABE */ 1556dfab439fSBenoit Cousson #define OMAP54XX_PAD_CLKS_GATE_SHIFT 8 1557dfab439fSBenoit Cousson #define OMAP54XX_PAD_CLKS_GATE_WIDTH 0x1 1558dfab439fSBenoit Cousson #define OMAP54XX_PAD_CLKS_GATE_MASK (1 << 8) 1559dfab439fSBenoit Cousson 1560dfab439fSBenoit Cousson /* Used by CM_RESTORE_ST */ 1561dfab439fSBenoit Cousson #define OMAP54XX_PHASE1_COMPLETED_SHIFT 0 1562dfab439fSBenoit Cousson #define OMAP54XX_PHASE1_COMPLETED_WIDTH 0x1 1563dfab439fSBenoit Cousson #define OMAP54XX_PHASE1_COMPLETED_MASK (1 << 0) 1564dfab439fSBenoit Cousson 1565dfab439fSBenoit Cousson /* Used by CM_RESTORE_ST */ 1566dfab439fSBenoit Cousson #define OMAP54XX_PHASE2A_COMPLETED_SHIFT 1 1567dfab439fSBenoit Cousson #define OMAP54XX_PHASE2A_COMPLETED_WIDTH 0x1 1568dfab439fSBenoit Cousson #define OMAP54XX_PHASE2A_COMPLETED_MASK (1 << 1) 1569dfab439fSBenoit Cousson 1570dfab439fSBenoit Cousson /* Used by CM_RESTORE_ST */ 1571dfab439fSBenoit Cousson #define OMAP54XX_PHASE2B_COMPLETED_SHIFT 2 1572dfab439fSBenoit Cousson #define OMAP54XX_PHASE2B_COMPLETED_WIDTH 0x1 1573dfab439fSBenoit Cousson #define OMAP54XX_PHASE2B_COMPLETED_MASK (1 << 2) 1574dfab439fSBenoit Cousson 1575dfab439fSBenoit Cousson /* Used by CM_DYN_DEP_PRESCAL */ 1576dfab439fSBenoit Cousson #define OMAP54XX_PRESCAL_SHIFT 0 1577dfab439fSBenoit Cousson #define OMAP54XX_PRESCAL_WIDTH 0x6 1578dfab439fSBenoit Cousson #define OMAP54XX_PRESCAL_MASK (0x3f << 0) 1579dfab439fSBenoit Cousson 1580dfab439fSBenoit Cousson /* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ 1581dfab439fSBenoit Cousson #define OMAP54XX_R_RTL_SHIFT 11 1582dfab439fSBenoit Cousson #define OMAP54XX_R_RTL_WIDTH 0x5 1583dfab439fSBenoit Cousson #define OMAP54XX_R_RTL_MASK (0x1f << 11) 1584dfab439fSBenoit Cousson 1585dfab439fSBenoit Cousson /* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_TLL_HS_CLKCTRL */ 1586dfab439fSBenoit Cousson #define OMAP54XX_SAR_MODE_SHIFT 4 1587dfab439fSBenoit Cousson #define OMAP54XX_SAR_MODE_WIDTH 0x1 1588dfab439fSBenoit Cousson #define OMAP54XX_SAR_MODE_MASK (1 << 4) 1589dfab439fSBenoit Cousson 1590dfab439fSBenoit Cousson /* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ 1591dfab439fSBenoit Cousson #define OMAP54XX_SCHEME_SHIFT 30 1592dfab439fSBenoit Cousson #define OMAP54XX_SCHEME_WIDTH 0x2 1593dfab439fSBenoit Cousson #define OMAP54XX_SCHEME_MASK (0x3 << 30) 1594dfab439fSBenoit Cousson 1595dfab439fSBenoit Cousson /* Used by CM_L4CFG_DYNAMICDEP */ 1596dfab439fSBenoit Cousson #define OMAP54XX_SDMA_DYNDEP_SHIFT 11 1597dfab439fSBenoit Cousson #define OMAP54XX_SDMA_DYNDEP_WIDTH 0x1 1598dfab439fSBenoit Cousson #define OMAP54XX_SDMA_DYNDEP_MASK (1 << 11) 1599dfab439fSBenoit Cousson 1600dfab439fSBenoit Cousson /* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */ 1601dfab439fSBenoit Cousson #define OMAP54XX_SDMA_STATDEP_SHIFT 11 1602dfab439fSBenoit Cousson #define OMAP54XX_SDMA_STATDEP_WIDTH 0x1 1603dfab439fSBenoit Cousson #define OMAP54XX_SDMA_STATDEP_MASK (1 << 11) 1604dfab439fSBenoit Cousson 1605dfab439fSBenoit Cousson /* Used by CM_CORE_AON_DEBUG_CFG */ 1606dfab439fSBenoit Cousson #define OMAP54XX_SEL0_SHIFT 0 1607dfab439fSBenoit Cousson #define OMAP54XX_SEL0_WIDTH 0x7 1608dfab439fSBenoit Cousson #define OMAP54XX_SEL0_MASK (0x7f << 0) 1609dfab439fSBenoit Cousson 1610dfab439fSBenoit Cousson /* Renamed from SEL0 Used by CM_CORE_DEBUG_CFG */ 1611dfab439fSBenoit Cousson #define OMAP54XX_SEL0_0_7_SHIFT 0 1612dfab439fSBenoit Cousson #define OMAP54XX_SEL0_0_7_WIDTH 0x8 1613dfab439fSBenoit Cousson #define OMAP54XX_SEL0_0_7_MASK (0xff << 0) 1614dfab439fSBenoit Cousson 1615dfab439fSBenoit Cousson /* Used by CM_CORE_AON_DEBUG_CFG */ 1616dfab439fSBenoit Cousson #define OMAP54XX_SEL1_SHIFT 8 1617dfab439fSBenoit Cousson #define OMAP54XX_SEL1_WIDTH 0x7 1618dfab439fSBenoit Cousson #define OMAP54XX_SEL1_MASK (0x7f << 8) 1619dfab439fSBenoit Cousson 1620dfab439fSBenoit Cousson /* Renamed from SEL1 Used by CM_CORE_DEBUG_CFG */ 1621dfab439fSBenoit Cousson #define OMAP54XX_SEL1_CORE_DEBUG_CFG_SHIFT 8 1622dfab439fSBenoit Cousson #define OMAP54XX_SEL1_CORE_DEBUG_CFG_WIDTH 0x8 1623dfab439fSBenoit Cousson #define OMAP54XX_SEL1_CORE_DEBUG_CFG_MASK (0xff << 8) 1624dfab439fSBenoit Cousson 1625dfab439fSBenoit Cousson /* Used by CM_CORE_AON_DEBUG_CFG */ 1626dfab439fSBenoit Cousson #define OMAP54XX_SEL2_SHIFT 16 1627dfab439fSBenoit Cousson #define OMAP54XX_SEL2_WIDTH 0x7 1628dfab439fSBenoit Cousson #define OMAP54XX_SEL2_MASK (0x7f << 16) 1629dfab439fSBenoit Cousson 1630dfab439fSBenoit Cousson /* Renamed from SEL2 Used by CM_CORE_DEBUG_CFG */ 1631dfab439fSBenoit Cousson #define OMAP54XX_SEL2_CORE_DEBUG_CFG_SHIFT 16 1632dfab439fSBenoit Cousson #define OMAP54XX_SEL2_CORE_DEBUG_CFG_WIDTH 0x8 1633dfab439fSBenoit Cousson #define OMAP54XX_SEL2_CORE_DEBUG_CFG_MASK (0xff << 16) 1634dfab439fSBenoit Cousson 1635dfab439fSBenoit Cousson /* Used by CM_CORE_AON_DEBUG_CFG */ 1636dfab439fSBenoit Cousson #define OMAP54XX_SEL3_SHIFT 24 1637dfab439fSBenoit Cousson #define OMAP54XX_SEL3_WIDTH 0x7 1638dfab439fSBenoit Cousson #define OMAP54XX_SEL3_MASK (0x7f << 24) 1639dfab439fSBenoit Cousson 1640dfab439fSBenoit Cousson /* Renamed from SEL3 Used by CM_CORE_DEBUG_CFG */ 1641dfab439fSBenoit Cousson #define OMAP54XX_SEL3_CORE_DEBUG_CFG_SHIFT 24 1642dfab439fSBenoit Cousson #define OMAP54XX_SEL3_CORE_DEBUG_CFG_WIDTH 0x8 1643dfab439fSBenoit Cousson #define OMAP54XX_SEL3_CORE_DEBUG_CFG_MASK (0xff << 24) 1644dfab439fSBenoit Cousson 1645dfab439fSBenoit Cousson /* Used by CM_CLKSEL_ABE */ 1646dfab439fSBenoit Cousson #define OMAP54XX_SLIMBUS1_CLK_GATE_SHIFT 10 1647dfab439fSBenoit Cousson #define OMAP54XX_SLIMBUS1_CLK_GATE_WIDTH 0x1 1648dfab439fSBenoit Cousson #define OMAP54XX_SLIMBUS1_CLK_GATE_MASK (1 << 10) 1649dfab439fSBenoit Cousson 1650dfab439fSBenoit Cousson /* 1651dfab439fSBenoit Cousson * Used by CM_ABE_AESS_CLKCTRL, CM_C2C_C2C_CLKCTRL, CM_CAM_FDIF_CLKCTRL, 1652dfab439fSBenoit Cousson * CM_CAM_ISS_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL, CM_DSP_DSP_CLKCTRL, 1653dfab439fSBenoit Cousson * CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, 1654dfab439fSBenoit Cousson * CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL, CM_IVA_IVA_CLKCTRL, 1655dfab439fSBenoit Cousson * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, 1656dfab439fSBenoit Cousson * CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_SATA_CLKCTRL, 1657dfab439fSBenoit Cousson * CM_L3INIT_UNIPRO2_CLKCTRL, CM_L3INIT_USB_HOST_HS_CLKCTRL, 1658dfab439fSBenoit Cousson * CM_L3INIT_USB_OTG_SS_CLKCTRL, CM_L4SEC_DMA_CRYPTO_CLKCTRL, 1659dfab439fSBenoit Cousson * CM_MIPIEXT_LLI_CLKCTRL, CM_MPU_MPU_CLKCTRL 1660dfab439fSBenoit Cousson */ 1661dfab439fSBenoit Cousson #define OMAP54XX_STBYST_SHIFT 18 1662dfab439fSBenoit Cousson #define OMAP54XX_STBYST_WIDTH 0x1 1663dfab439fSBenoit Cousson #define OMAP54XX_STBYST_MASK (1 << 18) 1664dfab439fSBenoit Cousson 1665dfab439fSBenoit Cousson /* 1666dfab439fSBenoit Cousson * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA, 1667dfab439fSBenoit Cousson * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1, 1668dfab439fSBenoit Cousson * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB 1669dfab439fSBenoit Cousson */ 1670dfab439fSBenoit Cousson #define OMAP54XX_ST_DPLL_CLK_SHIFT 0 1671dfab439fSBenoit Cousson #define OMAP54XX_ST_DPLL_CLK_WIDTH 0x1 1672dfab439fSBenoit Cousson #define OMAP54XX_ST_DPLL_CLK_MASK (1 << 0) 1673dfab439fSBenoit Cousson 1674dfab439fSBenoit Cousson /* 1675dfab439fSBenoit Cousson * Used by CM_CLKDCOLDO_DPLL_UNIPRO1, CM_CLKDCOLDO_DPLL_UNIPRO2, 1676dfab439fSBenoit Cousson * CM_CLKDCOLDO_DPLL_USB 1677dfab439fSBenoit Cousson */ 1678dfab439fSBenoit Cousson #define OMAP54XX_ST_DPLL_CLKDCOLDO_SHIFT 9 1679dfab439fSBenoit Cousson #define OMAP54XX_ST_DPLL_CLKDCOLDO_WIDTH 0x1 1680dfab439fSBenoit Cousson #define OMAP54XX_ST_DPLL_CLKDCOLDO_MASK (1 << 9) 1681dfab439fSBenoit Cousson 1682dfab439fSBenoit Cousson /* 1683dfab439fSBenoit Cousson * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA, 1684dfab439fSBenoit Cousson * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1, 1685dfab439fSBenoit Cousson * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB 1686dfab439fSBenoit Cousson */ 1687dfab439fSBenoit Cousson #define OMAP54XX_ST_DPLL_INIT_SHIFT 4 1688dfab439fSBenoit Cousson #define OMAP54XX_ST_DPLL_INIT_WIDTH 0x1 1689dfab439fSBenoit Cousson #define OMAP54XX_ST_DPLL_INIT_MASK (1 << 4) 1690dfab439fSBenoit Cousson 1691dfab439fSBenoit Cousson /* 1692dfab439fSBenoit Cousson * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA, 1693dfab439fSBenoit Cousson * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1, 1694dfab439fSBenoit Cousson * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB 1695dfab439fSBenoit Cousson */ 1696dfab439fSBenoit Cousson #define OMAP54XX_ST_DPLL_MODE_SHIFT 1 1697dfab439fSBenoit Cousson #define OMAP54XX_ST_DPLL_MODE_WIDTH 0x3 1698dfab439fSBenoit Cousson #define OMAP54XX_ST_DPLL_MODE_MASK (0x7 << 1) 1699dfab439fSBenoit Cousson 1700dfab439fSBenoit Cousson /* Used by CM_CLKSEL_SYS */ 1701dfab439fSBenoit Cousson #define OMAP54XX_SYS_CLKSEL_SHIFT 0 1702dfab439fSBenoit Cousson #define OMAP54XX_SYS_CLKSEL_WIDTH 0x3 1703dfab439fSBenoit Cousson #define OMAP54XX_SYS_CLKSEL_MASK (0x7 << 0) 1704dfab439fSBenoit Cousson 1705dfab439fSBenoit Cousson /* 1706dfab439fSBenoit Cousson * Used by CM_C2C_DYNAMICDEP, CM_DSP_DYNAMICDEP, CM_EMU_DYNAMICDEP, 1707dfab439fSBenoit Cousson * CM_IPU_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP, 1708dfab439fSBenoit Cousson * CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP, CM_MIPIEXT_DYNAMICDEP, 1709dfab439fSBenoit Cousson * CM_MPU_DYNAMICDEP 1710dfab439fSBenoit Cousson */ 1711dfab439fSBenoit Cousson #define OMAP54XX_WINDOWSIZE_SHIFT 24 1712dfab439fSBenoit Cousson #define OMAP54XX_WINDOWSIZE_WIDTH 0x4 1713dfab439fSBenoit Cousson #define OMAP54XX_WINDOWSIZE_MASK (0xf << 24) 1714dfab439fSBenoit Cousson 1715dfab439fSBenoit Cousson /* Used by CM_L3MAIN1_DYNAMICDEP */ 1716dfab439fSBenoit Cousson #define OMAP54XX_WKUPAON_DYNDEP_SHIFT 15 1717dfab439fSBenoit Cousson #define OMAP54XX_WKUPAON_DYNDEP_WIDTH 0x1 1718dfab439fSBenoit Cousson #define OMAP54XX_WKUPAON_DYNDEP_MASK (1 << 15) 1719dfab439fSBenoit Cousson 1720dfab439fSBenoit Cousson /* 1721dfab439fSBenoit Cousson * Used by CM_DMA_STATICDEP, CM_DSP_STATICDEP, CM_IPU_STATICDEP, 1722dfab439fSBenoit Cousson * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP 1723dfab439fSBenoit Cousson */ 1724dfab439fSBenoit Cousson #define OMAP54XX_WKUPAON_STATDEP_SHIFT 15 1725dfab439fSBenoit Cousson #define OMAP54XX_WKUPAON_STATDEP_WIDTH 0x1 1726dfab439fSBenoit Cousson #define OMAP54XX_WKUPAON_STATDEP_MASK (1 << 15) 1727dfab439fSBenoit Cousson 1728dfab439fSBenoit Cousson /* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ 1729dfab439fSBenoit Cousson #define OMAP54XX_X_MAJOR_SHIFT 8 1730dfab439fSBenoit Cousson #define OMAP54XX_X_MAJOR_WIDTH 0x3 1731dfab439fSBenoit Cousson #define OMAP54XX_X_MAJOR_MASK (0x7 << 8) 1732dfab439fSBenoit Cousson 1733dfab439fSBenoit Cousson /* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ 1734dfab439fSBenoit Cousson #define OMAP54XX_Y_MINOR_SHIFT 0 1735dfab439fSBenoit Cousson #define OMAP54XX_Y_MINOR_WIDTH 0x6 1736dfab439fSBenoit Cousson #define OMAP54XX_Y_MINOR_MASK (0x3f << 0) 1737dfab439fSBenoit Cousson #endif 1738