1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2dfab439fSBenoit Cousson /* 3dfab439fSBenoit Cousson * OMAP54xx Clock Management register bits 4dfab439fSBenoit Cousson * 583bf6db0SAlexander A. Klimov * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com 6dfab439fSBenoit Cousson * 7dfab439fSBenoit Cousson * Paul Walmsley (paul@pwsan.com) 8dfab439fSBenoit Cousson * Rajendra Nayak (rnayak@ti.com) 9dfab439fSBenoit Cousson * Benoit Cousson (b-cousson@ti.com) 10dfab439fSBenoit Cousson * 11dfab439fSBenoit Cousson * This file is automatically generated from the OMAP hardware databases. 12dfab439fSBenoit Cousson * We respectfully ask that any modifications to this file be coordinated 13dfab439fSBenoit Cousson * with the public linux-omap@vger.kernel.org mailing list and the 14dfab439fSBenoit Cousson * authors above to ensure that the autogeneration scripts are kept 15dfab439fSBenoit Cousson * up-to-date with the file contents. 16dfab439fSBenoit Cousson */ 17dfab439fSBenoit Cousson 18dfab439fSBenoit Cousson #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H 19dfab439fSBenoit Cousson #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H 20dfab439fSBenoit Cousson 21dfab439fSBenoit Cousson #define OMAP54XX_ABE_STATDEP_SHIFT 3 22dfab439fSBenoit Cousson #define OMAP54XX_AUTO_DPLL_MODE_MASK (0x7 << 0) 23dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_SHIFT 24 24dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_WIDTH 0x1 25dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_0_0_SHIFT 0 26dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_0_0_WIDTH 0x1 27dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_AESS_FCLK_SHIFT 24 28dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_AESS_FCLK_WIDTH 0x1 29dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_DIV_SHIFT 25 30dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_DIV_WIDTH 0x1 31dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_FCLK_SHIFT 24 32dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_FCLK_WIDTH 0x1 33dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT 24 34dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_GPU_CORE_GCLK_WIDTH 0x1 35dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT 25 36dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_GPU_HYD_GCLK_WIDTH 0x1 37dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT 26 38dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH 0x2 39dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_OPP_SHIFT 0 40dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_OPP_WIDTH 0x2 41dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_SOURCE_SHIFT 24 42dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_SOURCE_WIDTH 0x2 43dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT 24 44dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH 0x1 45dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_UTMI_P1_SHIFT 24 46dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_UTMI_P1_WIDTH 0x1 47dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_UTMI_P2_SHIFT 25 48dfab439fSBenoit Cousson #define OMAP54XX_CLKSEL_UTMI_P2_WIDTH 0x1 49dfab439fSBenoit Cousson #define OMAP54XX_DIVHS_MASK (0x3f << 0) 50dfab439fSBenoit Cousson #define OMAP54XX_DIVHS_0_4_MASK (0x1f << 0) 51dfab439fSBenoit Cousson #define OMAP54XX_DIVHS_0_6_MASK (0x7f << 0) 52dfab439fSBenoit Cousson #define OMAP54XX_DPLL_DIV_MASK (0x7f << 0) 53dfab439fSBenoit Cousson #define OMAP54XX_DPLL_EN_MASK (0x7 << 0) 54dfab439fSBenoit Cousson #define OMAP54XX_DPLL_LPMODE_EN_MASK (1 << 10) 55dfab439fSBenoit Cousson #define OMAP54XX_DPLL_MULT_MASK (0x7ff << 8) 56dfab439fSBenoit Cousson #define OMAP54XX_DPLL_REGM4XEN_MASK (1 << 11) 57dfab439fSBenoit Cousson #define OMAP54XX_DPLL_SD_DIV_MASK (0xff << 24) 58dfab439fSBenoit Cousson #define OMAP54XX_DSP_STATDEP_SHIFT 1 59dfab439fSBenoit Cousson #define OMAP54XX_DSS_STATDEP_SHIFT 8 60dfab439fSBenoit Cousson #define OMAP54XX_EMIF_STATDEP_SHIFT 4 61dfab439fSBenoit Cousson #define OMAP54XX_GPU_STATDEP_SHIFT 10 62dfab439fSBenoit Cousson #define OMAP54XX_IPU_STATDEP_SHIFT 0 63dfab439fSBenoit Cousson #define OMAP54XX_IVA_STATDEP_SHIFT 2 64dfab439fSBenoit Cousson #define OMAP54XX_L3INIT_STATDEP_SHIFT 7 65dfab439fSBenoit Cousson #define OMAP54XX_L3MAIN1_STATDEP_SHIFT 5 66dfab439fSBenoit Cousson #define OMAP54XX_L3MAIN2_STATDEP_SHIFT 6 67dfab439fSBenoit Cousson #define OMAP54XX_L4CFG_STATDEP_SHIFT 12 68dfab439fSBenoit Cousson #define OMAP54XX_L4PER_STATDEP_SHIFT 13 69dfab439fSBenoit Cousson #define OMAP54XX_L4SEC_STATDEP_SHIFT 14 70dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_SHIFT 11 71dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_SHIFT 8 72dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_48MHZ_CLK_SHIFT 9 73dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_CLK32K_SHIFT 8 74dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_CTRLCLK_SHIFT 8 75dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_DBCLK_SHIFT 8 76dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_DSSCLK_SHIFT 8 77dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 78dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 79dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_SHIFT 7 80dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 81dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 82dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_SHIFT 6 83dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_REFCLK960M_SHIFT 8 84dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_REF_CLK_SHIFT 8 85dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_SHIFT 11 86dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_SYS_CLK_SHIFT 10 87dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_TXPHY_CLK_SHIFT 8 88dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_SHIFT 9 89dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 90dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 91dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 92dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 93dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 94dfab439fSBenoit Cousson #define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 95dfab439fSBenoit Cousson #define OMAP54XX_PAD_CLKS_GATE_SHIFT 8 96dfab439fSBenoit Cousson #define OMAP54XX_SLIMBUS1_CLK_GATE_SHIFT 10 97dfab439fSBenoit Cousson #define OMAP54XX_ST_DPLL_CLK_MASK (1 << 0) 98dfab439fSBenoit Cousson #define OMAP54XX_SYS_CLKSEL_SHIFT 0 99dfab439fSBenoit Cousson #define OMAP54XX_SYS_CLKSEL_WIDTH 0x3 100dfab439fSBenoit Cousson #define OMAP54XX_WKUPAON_STATDEP_SHIFT 15 101dfab439fSBenoit Cousson #endif 102