1 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H 2 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H 3 4 /* 5 * OMAP3430 Clock Management register bits 6 * 7 * Copyright (C) 2007-2008 Texas Instruments, Inc. 8 * Copyright (C) 2007-2008 Nokia Corporation 9 * 10 * Written by Paul Walmsley 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License version 2 as 14 * published by the Free Software Foundation. 15 */ 16 17 #include "cm.h" 18 19 /* Bits shared between registers */ 20 21 /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ 22 #define OMAP3430ES2_EN_MMC3_MASK (1 << 30) 23 #define OMAP3430ES2_EN_MMC3_SHIFT 30 24 #define OMAP3430_EN_MSPRO (1 << 23) 25 #define OMAP3430_EN_MSPRO_SHIFT 23 26 #define OMAP3430_EN_HDQ (1 << 22) 27 #define OMAP3430_EN_HDQ_SHIFT 22 28 #define OMAP3430ES1_EN_FSHOSTUSB (1 << 5) 29 #define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5 30 #define OMAP3430ES1_EN_D2D (1 << 3) 31 #define OMAP3430ES1_EN_D2D_SHIFT 3 32 #define OMAP3430_EN_SSI (1 << 0) 33 #define OMAP3430_EN_SSI_SHIFT 0 34 35 /* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */ 36 #define OMAP3430ES2_EN_USBTLL_SHIFT 2 37 #define OMAP3430ES2_EN_USBTLL_MASK (1 << 2) 38 39 /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ 40 #define OMAP3430_EN_WDT2 (1 << 5) 41 #define OMAP3430_EN_WDT2_SHIFT 5 42 43 /* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */ 44 #define OMAP3430_EN_CAM (1 << 0) 45 #define OMAP3430_EN_CAM_SHIFT 0 46 47 /* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */ 48 #define OMAP3430_EN_WDT3 (1 << 12) 49 #define OMAP3430_EN_WDT3_SHIFT 12 50 51 /* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */ 52 #define OMAP3430_OVERRIDE_ENABLE (1 << 19) 53 54 55 /* Bits specific to each register */ 56 57 /* CM_FCLKEN_IVA2 */ 58 #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2 (1 << 0) 59 #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0 60 61 /* CM_CLKEN_PLL_IVA2 */ 62 #define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8 63 #define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8) 64 #define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4 65 #define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4) 66 #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3 67 #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3) 68 #define OMAP3430_EN_IVA2_DPLL_SHIFT 0 69 #define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0) 70 71 /* CM_IDLEST_IVA2 */ 72 #define OMAP3430_ST_IVA2 (1 << 0) 73 74 /* CM_IDLEST_PLL_IVA2 */ 75 #define OMAP3430_ST_IVA2_CLK_SHIFT 0 76 #define OMAP3430_ST_IVA2_CLK_MASK (1 << 0) 77 78 /* CM_AUTOIDLE_PLL_IVA2 */ 79 #define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0 80 #define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0) 81 82 /* CM_CLKSEL1_PLL_IVA2 */ 83 #define OMAP3430_IVA2_CLK_SRC_SHIFT 19 84 #define OMAP3430_IVA2_CLK_SRC_MASK (0x3 << 19) 85 #define OMAP3430_IVA2_DPLL_MULT_SHIFT 8 86 #define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) 87 #define OMAP3430_IVA2_DPLL_DIV_SHIFT 0 88 #define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0) 89 90 /* CM_CLKSEL2_PLL_IVA2 */ 91 #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0 92 #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0) 93 94 /* CM_CLKSTCTRL_IVA2 */ 95 #define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0 96 #define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0) 97 98 /* CM_CLKSTST_IVA2 */ 99 #define OMAP3430_CLKACTIVITY_IVA2_SHIFT 0 100 #define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0) 101 102 /* CM_REVISION specific bits */ 103 104 /* CM_SYSCONFIG specific bits */ 105 106 /* CM_CLKEN_PLL_MPU */ 107 #define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8 108 #define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8) 109 #define OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4 110 #define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4) 111 #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3 112 #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3) 113 #define OMAP3430_EN_MPU_DPLL_SHIFT 0 114 #define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0) 115 116 /* CM_IDLEST_MPU */ 117 #define OMAP3430_ST_MPU (1 << 0) 118 119 /* CM_IDLEST_PLL_MPU */ 120 #define OMAP3430_ST_MPU_CLK_SHIFT 0 121 #define OMAP3430_ST_MPU_CLK_MASK (1 << 0) 122 123 /* CM_AUTOIDLE_PLL_MPU */ 124 #define OMAP3430_AUTO_MPU_DPLL_SHIFT 0 125 #define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0) 126 127 /* CM_CLKSEL1_PLL_MPU */ 128 #define OMAP3430_MPU_CLK_SRC_SHIFT 19 129 #define OMAP3430_MPU_CLK_SRC_MASK (0x3 << 19) 130 #define OMAP3430_MPU_DPLL_MULT_SHIFT 8 131 #define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) 132 #define OMAP3430_MPU_DPLL_DIV_SHIFT 0 133 #define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0) 134 135 /* CM_CLKSEL2_PLL_MPU */ 136 #define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0 137 #define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0) 138 139 /* CM_CLKSTCTRL_MPU */ 140 #define OMAP3430_CLKTRCTRL_MPU_SHIFT 0 141 #define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0) 142 143 /* CM_CLKSTST_MPU */ 144 #define OMAP3430_CLKACTIVITY_MPU_SHIFT 0 145 #define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0) 146 147 /* CM_FCLKEN1_CORE specific bits */ 148 149 /* CM_ICLKEN1_CORE specific bits */ 150 #define OMAP3430_EN_ICR (1 << 29) 151 #define OMAP3430_EN_ICR_SHIFT 29 152 #define OMAP3430_EN_AES2 (1 << 28) 153 #define OMAP3430_EN_AES2_SHIFT 28 154 #define OMAP3430_EN_SHA12 (1 << 27) 155 #define OMAP3430_EN_SHA12_SHIFT 27 156 #define OMAP3430_EN_DES2 (1 << 26) 157 #define OMAP3430_EN_DES2_SHIFT 26 158 #define OMAP3430ES1_EN_FAC (1 << 8) 159 #define OMAP3430ES1_EN_FAC_SHIFT 8 160 #define OMAP3430_EN_MAILBOXES (1 << 7) 161 #define OMAP3430_EN_MAILBOXES_SHIFT 7 162 #define OMAP3430_EN_OMAPCTRL (1 << 6) 163 #define OMAP3430_EN_OMAPCTRL_SHIFT 6 164 #define OMAP3430_EN_SDRC (1 << 1) 165 #define OMAP3430_EN_SDRC_SHIFT 1 166 167 /* CM_ICLKEN2_CORE */ 168 #define OMAP3430_EN_PKA (1 << 4) 169 #define OMAP3430_EN_PKA_SHIFT 4 170 #define OMAP3430_EN_AES1 (1 << 3) 171 #define OMAP3430_EN_AES1_SHIFT 3 172 #define OMAP3430_EN_RNG (1 << 2) 173 #define OMAP3430_EN_RNG_SHIFT 2 174 #define OMAP3430_EN_SHA11 (1 << 1) 175 #define OMAP3430_EN_SHA11_SHIFT 1 176 #define OMAP3430_EN_DES1 (1 << 0) 177 #define OMAP3430_EN_DES1_SHIFT 0 178 179 /* CM_FCLKEN3_CORE specific bits */ 180 #define OMAP3430ES2_EN_TS_SHIFT 1 181 #define OMAP3430ES2_EN_TS_MASK (1 << 1) 182 #define OMAP3430ES2_EN_CPEFUSE_SHIFT 0 183 #define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0) 184 185 /* CM_IDLEST1_CORE specific bits */ 186 #define OMAP3430ES2_ST_MMC3_SHIFT 30 187 #define OMAP3430ES2_ST_MMC3_MASK (1 << 30) 188 #define OMAP3430_ST_ICR_SHIFT 29 189 #define OMAP3430_ST_ICR_MASK (1 << 29) 190 #define OMAP3430_ST_AES2_SHIFT 28 191 #define OMAP3430_ST_AES2_MASK (1 << 28) 192 #define OMAP3430_ST_SHA12_SHIFT 27 193 #define OMAP3430_ST_SHA12_MASK (1 << 27) 194 #define OMAP3430_ST_DES2_SHIFT 26 195 #define OMAP3430_ST_DES2_MASK (1 << 26) 196 #define OMAP3430_ST_MSPRO_SHIFT 23 197 #define OMAP3430_ST_MSPRO_MASK (1 << 23) 198 #define OMAP3430_ST_HDQ_SHIFT 22 199 #define OMAP3430_ST_HDQ_MASK (1 << 22) 200 #define OMAP3430ES1_ST_FAC_SHIFT 8 201 #define OMAP3430ES1_ST_FAC_MASK (1 << 8) 202 #define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8 203 #define OMAP3430ES2_ST_SSI_IDLE_MASK (1 << 8) 204 #define OMAP3430_ST_MAILBOXES_SHIFT 7 205 #define OMAP3430_ST_MAILBOXES_MASK (1 << 7) 206 #define OMAP3430_ST_OMAPCTRL_SHIFT 6 207 #define OMAP3430_ST_OMAPCTRL_MASK (1 << 6) 208 #define OMAP3430_ST_SDMA_SHIFT 2 209 #define OMAP3430_ST_SDMA_MASK (1 << 2) 210 #define OMAP3430_ST_SDRC_SHIFT 1 211 #define OMAP3430_ST_SDRC_MASK (1 << 1) 212 #define OMAP3430_ST_SSI_STDBY_SHIFT 0 213 #define OMAP3430_ST_SSI_STDBY_MASK (1 << 0) 214 215 /* CM_IDLEST2_CORE */ 216 #define OMAP3430_ST_PKA_SHIFT 4 217 #define OMAP3430_ST_PKA_MASK (1 << 4) 218 #define OMAP3430_ST_AES1_SHIFT 3 219 #define OMAP3430_ST_AES1_MASK (1 << 3) 220 #define OMAP3430_ST_RNG_SHIFT 2 221 #define OMAP3430_ST_RNG_MASK (1 << 2) 222 #define OMAP3430_ST_SHA11_SHIFT 1 223 #define OMAP3430_ST_SHA11_MASK (1 << 1) 224 #define OMAP3430_ST_DES1_SHIFT 0 225 #define OMAP3430_ST_DES1_MASK (1 << 0) 226 227 /* CM_IDLEST3_CORE */ 228 #define OMAP3430ES2_ST_USBTLL_SHIFT 2 229 #define OMAP3430ES2_ST_USBTLL_MASK (1 << 2) 230 #define OMAP3430ES2_ST_CPEFUSE_SHIFT 0 231 #define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0) 232 233 /* CM_AUTOIDLE1_CORE */ 234 #define OMAP3430ES2_AUTO_MMC3 (1 << 30) 235 #define OMAP3430ES2_AUTO_MMC3_SHIFT 30 236 #define OMAP3430ES2_AUTO_ICR (1 << 29) 237 #define OMAP3430ES2_AUTO_ICR_SHIFT 29 238 #define OMAP3430_AUTO_AES2 (1 << 28) 239 #define OMAP3430_AUTO_AES2_SHIFT 28 240 #define OMAP3430_AUTO_SHA12 (1 << 27) 241 #define OMAP3430_AUTO_SHA12_SHIFT 27 242 #define OMAP3430_AUTO_DES2 (1 << 26) 243 #define OMAP3430_AUTO_DES2_SHIFT 26 244 #define OMAP3430_AUTO_MMC2 (1 << 25) 245 #define OMAP3430_AUTO_MMC2_SHIFT 25 246 #define OMAP3430_AUTO_MMC1 (1 << 24) 247 #define OMAP3430_AUTO_MMC1_SHIFT 24 248 #define OMAP3430_AUTO_MSPRO (1 << 23) 249 #define OMAP3430_AUTO_MSPRO_SHIFT 23 250 #define OMAP3430_AUTO_HDQ (1 << 22) 251 #define OMAP3430_AUTO_HDQ_SHIFT 22 252 #define OMAP3430_AUTO_MCSPI4 (1 << 21) 253 #define OMAP3430_AUTO_MCSPI4_SHIFT 21 254 #define OMAP3430_AUTO_MCSPI3 (1 << 20) 255 #define OMAP3430_AUTO_MCSPI3_SHIFT 20 256 #define OMAP3430_AUTO_MCSPI2 (1 << 19) 257 #define OMAP3430_AUTO_MCSPI2_SHIFT 19 258 #define OMAP3430_AUTO_MCSPI1 (1 << 18) 259 #define OMAP3430_AUTO_MCSPI1_SHIFT 18 260 #define OMAP3430_AUTO_I2C3 (1 << 17) 261 #define OMAP3430_AUTO_I2C3_SHIFT 17 262 #define OMAP3430_AUTO_I2C2 (1 << 16) 263 #define OMAP3430_AUTO_I2C2_SHIFT 16 264 #define OMAP3430_AUTO_I2C1 (1 << 15) 265 #define OMAP3430_AUTO_I2C1_SHIFT 15 266 #define OMAP3430_AUTO_UART2 (1 << 14) 267 #define OMAP3430_AUTO_UART2_SHIFT 14 268 #define OMAP3430_AUTO_UART1 (1 << 13) 269 #define OMAP3430_AUTO_UART1_SHIFT 13 270 #define OMAP3430_AUTO_GPT11 (1 << 12) 271 #define OMAP3430_AUTO_GPT11_SHIFT 12 272 #define OMAP3430_AUTO_GPT10 (1 << 11) 273 #define OMAP3430_AUTO_GPT10_SHIFT 11 274 #define OMAP3430_AUTO_MCBSP5 (1 << 10) 275 #define OMAP3430_AUTO_MCBSP5_SHIFT 10 276 #define OMAP3430_AUTO_MCBSP1 (1 << 9) 277 #define OMAP3430_AUTO_MCBSP1_SHIFT 9 278 #define OMAP3430ES1_AUTO_FAC (1 << 8) 279 #define OMAP3430ES1_AUTO_FAC_SHIFT 8 280 #define OMAP3430_AUTO_MAILBOXES (1 << 7) 281 #define OMAP3430_AUTO_MAILBOXES_SHIFT 7 282 #define OMAP3430_AUTO_OMAPCTRL (1 << 6) 283 #define OMAP3430_AUTO_OMAPCTRL_SHIFT 6 284 #define OMAP3430ES1_AUTO_FSHOSTUSB (1 << 5) 285 #define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5 286 #define OMAP3430_AUTO_HSOTGUSB (1 << 4) 287 #define OMAP3430_AUTO_HSOTGUSB_SHIFT 4 288 #define OMAP3430ES1_AUTO_D2D (1 << 3) 289 #define OMAP3430ES1_AUTO_D2D_SHIFT 3 290 #define OMAP3430_AUTO_SSI (1 << 0) 291 #define OMAP3430_AUTO_SSI_SHIFT 0 292 293 /* CM_AUTOIDLE2_CORE */ 294 #define OMAP3430_AUTO_PKA (1 << 4) 295 #define OMAP3430_AUTO_PKA_SHIFT 4 296 #define OMAP3430_AUTO_AES1 (1 << 3) 297 #define OMAP3430_AUTO_AES1_SHIFT 3 298 #define OMAP3430_AUTO_RNG (1 << 2) 299 #define OMAP3430_AUTO_RNG_SHIFT 2 300 #define OMAP3430_AUTO_SHA11 (1 << 1) 301 #define OMAP3430_AUTO_SHA11_SHIFT 1 302 #define OMAP3430_AUTO_DES1 (1 << 0) 303 #define OMAP3430_AUTO_DES1_SHIFT 0 304 305 /* CM_AUTOIDLE3_CORE */ 306 #define OMAP3430ES2_AUTO_USBHOST (1 << 0) 307 #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 308 #define OMAP3430ES2_AUTO_USBTLL (1 << 2) 309 #define OMAP3430ES2_AUTO_USBTLL_SHIFT 2 310 #define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2) 311 312 /* CM_CLKSEL_CORE */ 313 #define OMAP3430_CLKSEL_SSI_SHIFT 8 314 #define OMAP3430_CLKSEL_SSI_MASK (0xf << 8) 315 #define OMAP3430_CLKSEL_GPT11_MASK (1 << 7) 316 #define OMAP3430_CLKSEL_GPT11_SHIFT 7 317 #define OMAP3430_CLKSEL_GPT10_MASK (1 << 6) 318 #define OMAP3430_CLKSEL_GPT10_SHIFT 6 319 #define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4 320 #define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4) 321 #define OMAP3430_CLKSEL_L4_SHIFT 2 322 #define OMAP3430_CLKSEL_L4_MASK (0x3 << 2) 323 #define OMAP3430_CLKSEL_L3_SHIFT 0 324 #define OMAP3430_CLKSEL_L3_MASK (0x3 << 0) 325 326 /* CM_CLKSTCTRL_CORE */ 327 #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4 328 #define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4) 329 #define OMAP3430_CLKTRCTRL_L4_SHIFT 2 330 #define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2) 331 #define OMAP3430_CLKTRCTRL_L3_SHIFT 0 332 #define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0) 333 334 /* CM_CLKSTST_CORE */ 335 #define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT 2 336 #define OMAP3430ES1_CLKACTIVITY_D2D_MASK (1 << 2) 337 #define OMAP3430_CLKACTIVITY_L4_SHIFT 1 338 #define OMAP3430_CLKACTIVITY_L4_MASK (1 << 1) 339 #define OMAP3430_CLKACTIVITY_L3_SHIFT 0 340 #define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0) 341 342 /* CM_FCLKEN_GFX */ 343 #define OMAP3430ES1_EN_3D (1 << 2) 344 #define OMAP3430ES1_EN_3D_SHIFT 2 345 #define OMAP3430ES1_EN_2D (1 << 1) 346 #define OMAP3430ES1_EN_2D_SHIFT 1 347 348 /* CM_ICLKEN_GFX specific bits */ 349 350 /* CM_IDLEST_GFX specific bits */ 351 352 /* CM_CLKSEL_GFX specific bits */ 353 354 /* CM_SLEEPDEP_GFX specific bits */ 355 356 /* CM_CLKSTCTRL_GFX */ 357 #define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0 358 #define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0) 359 360 /* CM_CLKSTST_GFX */ 361 #define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT 0 362 #define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0) 363 364 /* CM_FCLKEN_SGX */ 365 #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1 366 #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1) 367 368 /* CM_ICLKEN_SGX */ 369 #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0 370 #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0) 371 372 /* CM_CLKSEL_SGX */ 373 #define OMAP3430ES2_CLKSEL_SGX_SHIFT 0 374 #define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0) 375 376 /* CM_CLKSTCTRL_SGX */ 377 #define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT 0 378 #define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0) 379 380 /* CM_CLKSTST_SGX */ 381 #define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT 0 382 #define OMAP3430ES2_CLKACTIVITY_SGX_MASK (1 << 0) 383 384 /* CM_FCLKEN_WKUP specific bits */ 385 #define OMAP3430ES2_EN_USIMOCP_SHIFT 9 386 #define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9) 387 388 /* CM_ICLKEN_WKUP specific bits */ 389 #define OMAP3430_EN_WDT1 (1 << 4) 390 #define OMAP3430_EN_WDT1_SHIFT 4 391 #define OMAP3430_EN_32KSYNC (1 << 2) 392 #define OMAP3430_EN_32KSYNC_SHIFT 2 393 394 /* CM_IDLEST_WKUP specific bits */ 395 #define OMAP3430ES2_ST_USIMOCP_SHIFT 9 396 #define OMAP3430ES2_ST_USIMOCP_MASK (1 << 9) 397 #define OMAP3430_ST_WDT2_SHIFT 5 398 #define OMAP3430_ST_WDT2_MASK (1 << 5) 399 #define OMAP3430_ST_WDT1_SHIFT 4 400 #define OMAP3430_ST_WDT1_MASK (1 << 4) 401 #define OMAP3430_ST_32KSYNC_SHIFT 2 402 #define OMAP3430_ST_32KSYNC_MASK (1 << 2) 403 404 /* CM_AUTOIDLE_WKUP */ 405 #define OMAP3430ES2_AUTO_USIMOCP (1 << 9) 406 #define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9 407 #define OMAP3430_AUTO_WDT2 (1 << 5) 408 #define OMAP3430_AUTO_WDT2_SHIFT 5 409 #define OMAP3430_AUTO_WDT1 (1 << 4) 410 #define OMAP3430_AUTO_WDT1_SHIFT 4 411 #define OMAP3430_AUTO_GPIO1 (1 << 3) 412 #define OMAP3430_AUTO_GPIO1_SHIFT 3 413 #define OMAP3430_AUTO_32KSYNC (1 << 2) 414 #define OMAP3430_AUTO_32KSYNC_SHIFT 2 415 #define OMAP3430_AUTO_GPT12 (1 << 1) 416 #define OMAP3430_AUTO_GPT12_SHIFT 1 417 #define OMAP3430_AUTO_GPT1 (1 << 0) 418 #define OMAP3430_AUTO_GPT1_SHIFT 0 419 420 /* CM_CLKSEL_WKUP */ 421 #define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3) 422 #define OMAP3430_CLKSEL_RM_SHIFT 1 423 #define OMAP3430_CLKSEL_RM_MASK (0x3 << 1) 424 #define OMAP3430_CLKSEL_GPT1_SHIFT 0 425 #define OMAP3430_CLKSEL_GPT1_MASK (1 << 0) 426 427 /* CM_CLKEN_PLL */ 428 #define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31 429 #define OMAP3430_PWRDN_CAM_SHIFT 30 430 #define OMAP3430_PWRDN_DSS1_SHIFT 29 431 #define OMAP3430_PWRDN_TV_SHIFT 28 432 #define OMAP3430_PWRDN_96M_SHIFT 27 433 #define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24 434 #define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24) 435 #define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20 436 #define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20) 437 #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19 438 #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19) 439 #define OMAP3430_EN_PERIPH_DPLL_SHIFT 16 440 #define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16) 441 #define OMAP3430_PWRDN_EMU_CORE_SHIFT 12 442 #define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8 443 #define OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8) 444 #define OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4 445 #define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4) 446 #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3 447 #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3) 448 #define OMAP3430_EN_CORE_DPLL_SHIFT 0 449 #define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0) 450 451 /* CM_CLKEN2_PLL */ 452 #define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10 453 #define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8) 454 #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4 455 #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4) 456 #define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3 457 #define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0 458 #define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0) 459 460 /* CM_IDLEST_CKGEN */ 461 #define OMAP3430_ST_54M_CLK (1 << 5) 462 #define OMAP3430_ST_12M_CLK (1 << 4) 463 #define OMAP3430_ST_48M_CLK (1 << 3) 464 #define OMAP3430_ST_96M_CLK (1 << 2) 465 #define OMAP3430_ST_PERIPH_CLK_SHIFT 1 466 #define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1) 467 #define OMAP3430_ST_CORE_CLK_SHIFT 0 468 #define OMAP3430_ST_CORE_CLK_MASK (1 << 0) 469 470 /* CM_IDLEST2_CKGEN */ 471 #define OMAP3430ES2_ST_USIM_CLK_SHIFT 2 472 #define OMAP3430ES2_ST_USIM_CLK_MASK (1 << 2) 473 #define OMAP3430ES2_ST_120M_CLK_SHIFT 1 474 #define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1) 475 #define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0 476 #define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0) 477 478 /* CM_AUTOIDLE_PLL */ 479 #define OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3 480 #define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3) 481 #define OMAP3430_AUTO_CORE_DPLL_SHIFT 0 482 #define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0) 483 484 /* CM_AUTOIDLE2_PLL */ 485 #define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT 0 486 #define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0) 487 488 /* CM_CLKSEL1_PLL */ 489 /* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */ 490 #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27 491 #define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27) 492 #define OMAP3430_CORE_DPLL_MULT_SHIFT 16 493 #define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) 494 #define OMAP3430_CORE_DPLL_DIV_SHIFT 8 495 #define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8) 496 #define OMAP3430_SOURCE_96M_SHIFT 6 497 #define OMAP3430_SOURCE_96M_MASK (1 << 6) 498 #define OMAP3430_SOURCE_54M_SHIFT 5 499 #define OMAP3430_SOURCE_54M_MASK (1 << 5) 500 #define OMAP3430_SOURCE_48M_SHIFT 3 501 #define OMAP3430_SOURCE_48M_MASK (1 << 3) 502 503 /* CM_CLKSEL2_PLL */ 504 #define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8 505 #define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8) 506 #define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0 507 #define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0) 508 509 /* CM_CLKSEL3_PLL */ 510 #define OMAP3430_DIV_96M_SHIFT 0 511 #define OMAP3430_DIV_96M_MASK (0x1f << 0) 512 513 /* CM_CLKSEL4_PLL */ 514 #define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8 515 #define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8) 516 #define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0 517 #define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0) 518 519 /* CM_CLKSEL5_PLL */ 520 #define OMAP3430ES2_DIV_120M_SHIFT 0 521 #define OMAP3430ES2_DIV_120M_MASK (0x1f << 0) 522 523 /* CM_CLKOUT_CTRL */ 524 #define OMAP3430_CLKOUT2_EN_SHIFT 7 525 #define OMAP3430_CLKOUT2_EN (1 << 7) 526 #define OMAP3430_CLKOUT2_DIV_SHIFT 3 527 #define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3) 528 #define OMAP3430_CLKOUT2SOURCE_SHIFT 0 529 #define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0) 530 531 /* CM_FCLKEN_DSS */ 532 #define OMAP3430_EN_TV (1 << 2) 533 #define OMAP3430_EN_TV_SHIFT 2 534 #define OMAP3430_EN_DSS2 (1 << 1) 535 #define OMAP3430_EN_DSS2_SHIFT 1 536 #define OMAP3430_EN_DSS1 (1 << 0) 537 #define OMAP3430_EN_DSS1_SHIFT 0 538 539 /* CM_ICLKEN_DSS */ 540 #define OMAP3430_CM_ICLKEN_DSS_EN_DSS (1 << 0) 541 #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 542 543 /* CM_IDLEST_DSS */ 544 #define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1 545 #define OMAP3430ES2_ST_DSS_IDLE_MASK (1 << 1) 546 #define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0 547 #define OMAP3430ES2_ST_DSS_STDBY_MASK (1 << 0) 548 #define OMAP3430ES1_ST_DSS_SHIFT 0 549 #define OMAP3430ES1_ST_DSS_MASK (1 << 0) 550 551 /* CM_AUTOIDLE_DSS */ 552 #define OMAP3430_AUTO_DSS (1 << 0) 553 #define OMAP3430_AUTO_DSS_SHIFT 0 554 555 /* CM_CLKSEL_DSS */ 556 #define OMAP3430_CLKSEL_TV_SHIFT 8 557 #define OMAP3430_CLKSEL_TV_MASK (0x1f << 8) 558 #define OMAP3430_CLKSEL_DSS1_SHIFT 0 559 #define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0) 560 561 /* CM_SLEEPDEP_DSS specific bits */ 562 563 /* CM_CLKSTCTRL_DSS */ 564 #define OMAP3430_CLKTRCTRL_DSS_SHIFT 0 565 #define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0) 566 567 /* CM_CLKSTST_DSS */ 568 #define OMAP3430_CLKACTIVITY_DSS_SHIFT 0 569 #define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0) 570 571 /* CM_FCLKEN_CAM specific bits */ 572 #define OMAP3430_EN_CSI2 (1 << 1) 573 #define OMAP3430_EN_CSI2_SHIFT 1 574 575 /* CM_ICLKEN_CAM specific bits */ 576 577 /* CM_IDLEST_CAM */ 578 #define OMAP3430_ST_CAM (1 << 0) 579 580 /* CM_AUTOIDLE_CAM */ 581 #define OMAP3430_AUTO_CAM (1 << 0) 582 #define OMAP3430_AUTO_CAM_SHIFT 0 583 584 /* CM_CLKSEL_CAM */ 585 #define OMAP3430_CLKSEL_CAM_SHIFT 0 586 #define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0) 587 588 /* CM_SLEEPDEP_CAM specific bits */ 589 590 /* CM_CLKSTCTRL_CAM */ 591 #define OMAP3430_CLKTRCTRL_CAM_SHIFT 0 592 #define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0) 593 594 /* CM_CLKSTST_CAM */ 595 #define OMAP3430_CLKACTIVITY_CAM_SHIFT 0 596 #define OMAP3430_CLKACTIVITY_CAM_MASK (1 << 0) 597 598 /* CM_FCLKEN_PER specific bits */ 599 600 /* CM_ICLKEN_PER specific bits */ 601 602 /* CM_IDLEST_PER */ 603 #define OMAP3430_ST_WDT3_SHIFT 12 604 #define OMAP3430_ST_WDT3_MASK (1 << 12) 605 #define OMAP3430_ST_MCBSP4_SHIFT 2 606 #define OMAP3430_ST_MCBSP4_MASK (1 << 2) 607 #define OMAP3430_ST_MCBSP3_SHIFT 1 608 #define OMAP3430_ST_MCBSP3_MASK (1 << 1) 609 #define OMAP3430_ST_MCBSP2_SHIFT 0 610 #define OMAP3430_ST_MCBSP2_MASK (1 << 0) 611 612 /* CM_AUTOIDLE_PER */ 613 #define OMAP3430_AUTO_GPIO6 (1 << 17) 614 #define OMAP3430_AUTO_GPIO6_SHIFT 17 615 #define OMAP3430_AUTO_GPIO5 (1 << 16) 616 #define OMAP3430_AUTO_GPIO5_SHIFT 16 617 #define OMAP3430_AUTO_GPIO4 (1 << 15) 618 #define OMAP3430_AUTO_GPIO4_SHIFT 15 619 #define OMAP3430_AUTO_GPIO3 (1 << 14) 620 #define OMAP3430_AUTO_GPIO3_SHIFT 14 621 #define OMAP3430_AUTO_GPIO2 (1 << 13) 622 #define OMAP3430_AUTO_GPIO2_SHIFT 13 623 #define OMAP3430_AUTO_WDT3 (1 << 12) 624 #define OMAP3430_AUTO_WDT3_SHIFT 12 625 #define OMAP3430_AUTO_UART3 (1 << 11) 626 #define OMAP3430_AUTO_UART3_SHIFT 11 627 #define OMAP3430_AUTO_GPT9 (1 << 10) 628 #define OMAP3430_AUTO_GPT9_SHIFT 10 629 #define OMAP3430_AUTO_GPT8 (1 << 9) 630 #define OMAP3430_AUTO_GPT8_SHIFT 9 631 #define OMAP3430_AUTO_GPT7 (1 << 8) 632 #define OMAP3430_AUTO_GPT7_SHIFT 8 633 #define OMAP3430_AUTO_GPT6 (1 << 7) 634 #define OMAP3430_AUTO_GPT6_SHIFT 7 635 #define OMAP3430_AUTO_GPT5 (1 << 6) 636 #define OMAP3430_AUTO_GPT5_SHIFT 6 637 #define OMAP3430_AUTO_GPT4 (1 << 5) 638 #define OMAP3430_AUTO_GPT4_SHIFT 5 639 #define OMAP3430_AUTO_GPT3 (1 << 4) 640 #define OMAP3430_AUTO_GPT3_SHIFT 4 641 #define OMAP3430_AUTO_GPT2 (1 << 3) 642 #define OMAP3430_AUTO_GPT2_SHIFT 3 643 #define OMAP3430_AUTO_MCBSP4 (1 << 2) 644 #define OMAP3430_AUTO_MCBSP4_SHIFT 2 645 #define OMAP3430_AUTO_MCBSP3 (1 << 1) 646 #define OMAP3430_AUTO_MCBSP3_SHIFT 1 647 #define OMAP3430_AUTO_MCBSP2 (1 << 0) 648 #define OMAP3430_AUTO_MCBSP2_SHIFT 0 649 650 /* CM_CLKSEL_PER */ 651 #define OMAP3430_CLKSEL_GPT9_MASK (1 << 7) 652 #define OMAP3430_CLKSEL_GPT9_SHIFT 7 653 #define OMAP3430_CLKSEL_GPT8_MASK (1 << 6) 654 #define OMAP3430_CLKSEL_GPT8_SHIFT 6 655 #define OMAP3430_CLKSEL_GPT7_MASK (1 << 5) 656 #define OMAP3430_CLKSEL_GPT7_SHIFT 5 657 #define OMAP3430_CLKSEL_GPT6_MASK (1 << 4) 658 #define OMAP3430_CLKSEL_GPT6_SHIFT 4 659 #define OMAP3430_CLKSEL_GPT5_MASK (1 << 3) 660 #define OMAP3430_CLKSEL_GPT5_SHIFT 3 661 #define OMAP3430_CLKSEL_GPT4_MASK (1 << 2) 662 #define OMAP3430_CLKSEL_GPT4_SHIFT 2 663 #define OMAP3430_CLKSEL_GPT3_MASK (1 << 1) 664 #define OMAP3430_CLKSEL_GPT3_SHIFT 1 665 #define OMAP3430_CLKSEL_GPT2_MASK (1 << 0) 666 #define OMAP3430_CLKSEL_GPT2_SHIFT 0 667 668 /* CM_SLEEPDEP_PER specific bits */ 669 #define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2 (1 << 2) 670 671 /* CM_CLKSTCTRL_PER */ 672 #define OMAP3430_CLKTRCTRL_PER_SHIFT 0 673 #define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0) 674 675 /* CM_CLKSTST_PER */ 676 #define OMAP3430_CLKACTIVITY_PER_SHIFT 0 677 #define OMAP3430_CLKACTIVITY_PER_MASK (1 << 0) 678 679 /* CM_CLKSEL1_EMU */ 680 #define OMAP3430_DIV_DPLL4_SHIFT 24 681 #define OMAP3430_DIV_DPLL4_MASK (0x1f << 24) 682 #define OMAP3430_DIV_DPLL3_SHIFT 16 683 #define OMAP3430_DIV_DPLL3_MASK (0x1f << 16) 684 #define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 685 #define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11) 686 #define OMAP3430_CLKSEL_PCLK_SHIFT 8 687 #define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8) 688 #define OMAP3430_CLKSEL_PCLKX2_SHIFT 6 689 #define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6) 690 #define OMAP3430_CLKSEL_ATCLK_SHIFT 4 691 #define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4) 692 #define OMAP3430_TRACE_MUX_CTRL_SHIFT 2 693 #define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2) 694 #define OMAP3430_MUX_CTRL_SHIFT 0 695 #define OMAP3430_MUX_CTRL_MASK (0x3 << 0) 696 697 /* CM_CLKSTCTRL_EMU */ 698 #define OMAP3430_CLKTRCTRL_EMU_SHIFT 0 699 #define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0) 700 701 /* CM_CLKSTST_EMU */ 702 #define OMAP3430_CLKACTIVITY_EMU_SHIFT 0 703 #define OMAP3430_CLKACTIVITY_EMU_MASK (1 << 0) 704 705 /* CM_CLKSEL2_EMU specific bits */ 706 #define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8 707 #define OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8) 708 #define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0 709 #define OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0) 710 711 /* CM_CLKSEL3_EMU specific bits */ 712 #define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8 713 #define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8) 714 #define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0 715 #define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0) 716 717 /* CM_POLCTRL */ 718 #define OMAP3430_CLKOUT2_POL (1 << 0) 719 720 /* CM_IDLEST_NEON */ 721 #define OMAP3430_ST_NEON (1 << 0) 722 723 /* CM_CLKSTCTRL_NEON */ 724 #define OMAP3430_CLKTRCTRL_NEON_SHIFT 0 725 #define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0) 726 727 /* CM_FCLKEN_USBHOST */ 728 #define OMAP3430ES2_EN_USBHOST2_SHIFT 1 729 #define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1) 730 #define OMAP3430ES2_EN_USBHOST1_SHIFT 0 731 #define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0) 732 733 /* CM_ICLKEN_USBHOST */ 734 #define OMAP3430ES2_EN_USBHOST_SHIFT 0 735 #define OMAP3430ES2_EN_USBHOST_MASK (1 << 0) 736 737 /* CM_IDLEST_USBHOST */ 738 #define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1 739 #define OMAP3430ES2_ST_USBHOST_IDLE_MASK (1 << 1) 740 #define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0 741 #define OMAP3430ES2_ST_USBHOST_STDBY_MASK (1 << 0) 742 743 /* CM_AUTOIDLE_USBHOST */ 744 #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 745 #define OMAP3430ES2_AUTO_USBHOST_MASK (1 << 0) 746 747 /* CM_SLEEPDEP_USBHOST */ 748 #define OMAP3430ES2_EN_MPU_SHIFT 1 749 #define OMAP3430ES2_EN_MPU_MASK (1 << 1) 750 #define OMAP3430ES2_EN_IVA2_SHIFT 2 751 #define OMAP3430ES2_EN_IVA2_MASK (1 << 2) 752 753 /* CM_CLKSTCTRL_USBHOST */ 754 #define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0 755 #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0) 756 757 /* CM_CLKSTST_USBHOST */ 758 #define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0 759 #define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0) 760 761 #endif 762