1 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H 2 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H 3 4 /* 5 * OMAP3430 Clock Management register bits 6 * 7 * Copyright (C) 2007-2008 Texas Instruments, Inc. 8 * Copyright (C) 2007-2008 Nokia Corporation 9 * 10 * Written by Paul Walmsley 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License version 2 as 14 * published by the Free Software Foundation. 15 */ 16 17 #include "cm.h" 18 19 /* Bits shared between registers */ 20 21 /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ 22 #define OMAP3430ES2_EN_MMC3_MASK (1 << 30) 23 #define OMAP3430ES2_EN_MMC3_SHIFT 30 24 #define OMAP3430_EN_MSPRO (1 << 23) 25 #define OMAP3430_EN_MSPRO_SHIFT 23 26 #define OMAP3430_EN_HDQ (1 << 22) 27 #define OMAP3430_EN_HDQ_SHIFT 22 28 #define OMAP3430ES1_EN_FSHOSTUSB (1 << 5) 29 #define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5 30 #define OMAP3430ES1_EN_D2D (1 << 3) 31 #define OMAP3430ES1_EN_D2D_SHIFT 3 32 #define OMAP3430_EN_SSI (1 << 0) 33 #define OMAP3430_EN_SSI_SHIFT 0 34 35 /* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */ 36 #define OMAP3430ES2_EN_USBTLL_SHIFT 2 37 #define OMAP3430ES2_EN_USBTLL_MASK (1 << 2) 38 39 /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ 40 #define OMAP3430_EN_WDT2 (1 << 5) 41 #define OMAP3430_EN_WDT2_SHIFT 5 42 43 /* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */ 44 #define OMAP3430_EN_CAM (1 << 0) 45 #define OMAP3430_EN_CAM_SHIFT 0 46 47 /* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */ 48 #define OMAP3430_EN_WDT3 (1 << 12) 49 #define OMAP3430_EN_WDT3_SHIFT 12 50 51 /* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */ 52 #define OMAP3430_OVERRIDE_ENABLE (1 << 19) 53 54 55 /* Bits specific to each register */ 56 57 /* CM_FCLKEN_IVA2 */ 58 #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2 (1 << 0) 59 #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0 60 61 /* CM_CLKEN_PLL_IVA2 */ 62 #define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8 63 #define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8) 64 #define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4 65 #define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4) 66 #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3 67 #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3) 68 #define OMAP3430_EN_IVA2_DPLL_SHIFT 0 69 #define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0) 70 71 /* CM_IDLEST_IVA2 */ 72 #define OMAP3430_ST_IVA2 (1 << 0) 73 74 /* CM_IDLEST_PLL_IVA2 */ 75 #define OMAP3430_ST_IVA2_CLK_SHIFT 0 76 #define OMAP3430_ST_IVA2_CLK_MASK (1 << 0) 77 78 /* CM_AUTOIDLE_PLL_IVA2 */ 79 #define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0 80 #define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0) 81 82 /* CM_CLKSEL1_PLL_IVA2 */ 83 #define OMAP3430_IVA2_CLK_SRC_SHIFT 19 84 #define OMAP3430_IVA2_CLK_SRC_MASK (0x3 << 19) 85 #define OMAP3430_IVA2_DPLL_MULT_SHIFT 8 86 #define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) 87 #define OMAP3430_IVA2_DPLL_DIV_SHIFT 0 88 #define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0) 89 90 /* CM_CLKSEL2_PLL_IVA2 */ 91 #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0 92 #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0) 93 94 /* CM_CLKSTCTRL_IVA2 */ 95 #define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0 96 #define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0) 97 98 /* CM_CLKSTST_IVA2 */ 99 #define OMAP3430_CLKACTIVITY_IVA2_SHIFT 0 100 #define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0) 101 102 /* CM_REVISION specific bits */ 103 104 /* CM_SYSCONFIG specific bits */ 105 106 /* CM_CLKEN_PLL_MPU */ 107 #define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8 108 #define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8) 109 #define OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4 110 #define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4) 111 #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3 112 #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3) 113 #define OMAP3430_EN_MPU_DPLL_SHIFT 0 114 #define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0) 115 116 /* CM_IDLEST_MPU */ 117 #define OMAP3430_ST_MPU (1 << 0) 118 119 /* CM_IDLEST_PLL_MPU */ 120 #define OMAP3430_ST_MPU_CLK_SHIFT 0 121 #define OMAP3430_ST_MPU_CLK_MASK (1 << 0) 122 123 /* CM_AUTOIDLE_PLL_MPU */ 124 #define OMAP3430_AUTO_MPU_DPLL_SHIFT 0 125 #define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0) 126 127 /* CM_CLKSEL1_PLL_MPU */ 128 #define OMAP3430_MPU_CLK_SRC_SHIFT 19 129 #define OMAP3430_MPU_CLK_SRC_MASK (0x3 << 19) 130 #define OMAP3430_MPU_DPLL_MULT_SHIFT 8 131 #define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) 132 #define OMAP3430_MPU_DPLL_DIV_SHIFT 0 133 #define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0) 134 135 /* CM_CLKSEL2_PLL_MPU */ 136 #define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0 137 #define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0) 138 139 /* CM_CLKSTCTRL_MPU */ 140 #define OMAP3430_CLKTRCTRL_MPU_SHIFT 0 141 #define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0) 142 143 /* CM_CLKSTST_MPU */ 144 #define OMAP3430_CLKACTIVITY_MPU_SHIFT 0 145 #define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0) 146 147 /* CM_FCLKEN1_CORE specific bits */ 148 #define OMAP3430_EN_MODEM (1 << 31) 149 #define OMAP3430_EN_MODEM_SHIFT 31 150 151 /* CM_ICLKEN1_CORE specific bits */ 152 #define OMAP3430_EN_ICR (1 << 29) 153 #define OMAP3430_EN_ICR_SHIFT 29 154 #define OMAP3430_EN_AES2 (1 << 28) 155 #define OMAP3430_EN_AES2_SHIFT 28 156 #define OMAP3430_EN_SHA12 (1 << 27) 157 #define OMAP3430_EN_SHA12_SHIFT 27 158 #define OMAP3430_EN_DES2 (1 << 26) 159 #define OMAP3430_EN_DES2_SHIFT 26 160 #define OMAP3430ES1_EN_FAC (1 << 8) 161 #define OMAP3430ES1_EN_FAC_SHIFT 8 162 #define OMAP3430_EN_MAILBOXES (1 << 7) 163 #define OMAP3430_EN_MAILBOXES_SHIFT 7 164 #define OMAP3430_EN_OMAPCTRL (1 << 6) 165 #define OMAP3430_EN_OMAPCTRL_SHIFT 6 166 #define OMAP3430_EN_SAD2D (1 << 3) 167 #define OMAP3430_EN_SAD2D_SHIFT 3 168 #define OMAP3430_EN_SDRC (1 << 1) 169 #define OMAP3430_EN_SDRC_SHIFT 1 170 171 /* CM_ICLKEN2_CORE */ 172 #define OMAP3430_EN_PKA (1 << 4) 173 #define OMAP3430_EN_PKA_SHIFT 4 174 #define OMAP3430_EN_AES1 (1 << 3) 175 #define OMAP3430_EN_AES1_SHIFT 3 176 #define OMAP3430_EN_RNG (1 << 2) 177 #define OMAP3430_EN_RNG_SHIFT 2 178 #define OMAP3430_EN_SHA11 (1 << 1) 179 #define OMAP3430_EN_SHA11_SHIFT 1 180 #define OMAP3430_EN_DES1 (1 << 0) 181 #define OMAP3430_EN_DES1_SHIFT 0 182 183 /* CM_ICLKEN3_CORE */ 184 #define OMAP3430_EN_MAD2D_SHIFT 3 185 #define OMAP3430_EN_MAD2D (1 << 3) 186 187 /* CM_FCLKEN3_CORE specific bits */ 188 #define OMAP3430ES2_EN_TS_SHIFT 1 189 #define OMAP3430ES2_EN_TS_MASK (1 << 1) 190 #define OMAP3430ES2_EN_CPEFUSE_SHIFT 0 191 #define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0) 192 193 /* CM_IDLEST1_CORE specific bits */ 194 #define OMAP3430ES2_ST_MMC3_SHIFT 30 195 #define OMAP3430ES2_ST_MMC3_MASK (1 << 30) 196 #define OMAP3430_ST_ICR_SHIFT 29 197 #define OMAP3430_ST_ICR_MASK (1 << 29) 198 #define OMAP3430_ST_AES2_SHIFT 28 199 #define OMAP3430_ST_AES2_MASK (1 << 28) 200 #define OMAP3430_ST_SHA12_SHIFT 27 201 #define OMAP3430_ST_SHA12_MASK (1 << 27) 202 #define OMAP3430_ST_DES2_SHIFT 26 203 #define OMAP3430_ST_DES2_MASK (1 << 26) 204 #define OMAP3430_ST_MSPRO_SHIFT 23 205 #define OMAP3430_ST_MSPRO_MASK (1 << 23) 206 #define OMAP3430_ST_HDQ_SHIFT 22 207 #define OMAP3430_ST_HDQ_MASK (1 << 22) 208 #define OMAP3430ES1_ST_FAC_SHIFT 8 209 #define OMAP3430ES1_ST_FAC_MASK (1 << 8) 210 #define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8 211 #define OMAP3430ES2_ST_SSI_IDLE_MASK (1 << 8) 212 #define OMAP3430_ST_MAILBOXES_SHIFT 7 213 #define OMAP3430_ST_MAILBOXES_MASK (1 << 7) 214 #define OMAP3430_ST_OMAPCTRL_SHIFT 6 215 #define OMAP3430_ST_OMAPCTRL_MASK (1 << 6) 216 #define OMAP3430_ST_SDMA_SHIFT 2 217 #define OMAP3430_ST_SDMA_MASK (1 << 2) 218 #define OMAP3430_ST_SDRC_SHIFT 1 219 #define OMAP3430_ST_SDRC_MASK (1 << 1) 220 #define OMAP3430_ST_SSI_STDBY_SHIFT 0 221 #define OMAP3430_ST_SSI_STDBY_MASK (1 << 0) 222 223 /* CM_IDLEST2_CORE */ 224 #define OMAP3430_ST_PKA_SHIFT 4 225 #define OMAP3430_ST_PKA_MASK (1 << 4) 226 #define OMAP3430_ST_AES1_SHIFT 3 227 #define OMAP3430_ST_AES1_MASK (1 << 3) 228 #define OMAP3430_ST_RNG_SHIFT 2 229 #define OMAP3430_ST_RNG_MASK (1 << 2) 230 #define OMAP3430_ST_SHA11_SHIFT 1 231 #define OMAP3430_ST_SHA11_MASK (1 << 1) 232 #define OMAP3430_ST_DES1_SHIFT 0 233 #define OMAP3430_ST_DES1_MASK (1 << 0) 234 235 /* CM_IDLEST3_CORE */ 236 #define OMAP3430ES2_ST_USBTLL_SHIFT 2 237 #define OMAP3430ES2_ST_USBTLL_MASK (1 << 2) 238 #define OMAP3430ES2_ST_CPEFUSE_SHIFT 0 239 #define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0) 240 241 /* CM_AUTOIDLE1_CORE */ 242 #define OMAP3430_AUTO_MODEM (1 << 31) 243 #define OMAP3430_AUTO_MODEM_SHIFT 31 244 #define OMAP3430ES2_AUTO_MMC3 (1 << 30) 245 #define OMAP3430ES2_AUTO_MMC3_SHIFT 30 246 #define OMAP3430ES2_AUTO_ICR (1 << 29) 247 #define OMAP3430ES2_AUTO_ICR_SHIFT 29 248 #define OMAP3430_AUTO_AES2 (1 << 28) 249 #define OMAP3430_AUTO_AES2_SHIFT 28 250 #define OMAP3430_AUTO_SHA12 (1 << 27) 251 #define OMAP3430_AUTO_SHA12_SHIFT 27 252 #define OMAP3430_AUTO_DES2 (1 << 26) 253 #define OMAP3430_AUTO_DES2_SHIFT 26 254 #define OMAP3430_AUTO_MMC2 (1 << 25) 255 #define OMAP3430_AUTO_MMC2_SHIFT 25 256 #define OMAP3430_AUTO_MMC1 (1 << 24) 257 #define OMAP3430_AUTO_MMC1_SHIFT 24 258 #define OMAP3430_AUTO_MSPRO (1 << 23) 259 #define OMAP3430_AUTO_MSPRO_SHIFT 23 260 #define OMAP3430_AUTO_HDQ (1 << 22) 261 #define OMAP3430_AUTO_HDQ_SHIFT 22 262 #define OMAP3430_AUTO_MCSPI4 (1 << 21) 263 #define OMAP3430_AUTO_MCSPI4_SHIFT 21 264 #define OMAP3430_AUTO_MCSPI3 (1 << 20) 265 #define OMAP3430_AUTO_MCSPI3_SHIFT 20 266 #define OMAP3430_AUTO_MCSPI2 (1 << 19) 267 #define OMAP3430_AUTO_MCSPI2_SHIFT 19 268 #define OMAP3430_AUTO_MCSPI1 (1 << 18) 269 #define OMAP3430_AUTO_MCSPI1_SHIFT 18 270 #define OMAP3430_AUTO_I2C3 (1 << 17) 271 #define OMAP3430_AUTO_I2C3_SHIFT 17 272 #define OMAP3430_AUTO_I2C2 (1 << 16) 273 #define OMAP3430_AUTO_I2C2_SHIFT 16 274 #define OMAP3430_AUTO_I2C1 (1 << 15) 275 #define OMAP3430_AUTO_I2C1_SHIFT 15 276 #define OMAP3430_AUTO_UART2 (1 << 14) 277 #define OMAP3430_AUTO_UART2_SHIFT 14 278 #define OMAP3430_AUTO_UART1 (1 << 13) 279 #define OMAP3430_AUTO_UART1_SHIFT 13 280 #define OMAP3430_AUTO_GPT11 (1 << 12) 281 #define OMAP3430_AUTO_GPT11_SHIFT 12 282 #define OMAP3430_AUTO_GPT10 (1 << 11) 283 #define OMAP3430_AUTO_GPT10_SHIFT 11 284 #define OMAP3430_AUTO_MCBSP5 (1 << 10) 285 #define OMAP3430_AUTO_MCBSP5_SHIFT 10 286 #define OMAP3430_AUTO_MCBSP1 (1 << 9) 287 #define OMAP3430_AUTO_MCBSP1_SHIFT 9 288 #define OMAP3430ES1_AUTO_FAC (1 << 8) 289 #define OMAP3430ES1_AUTO_FAC_SHIFT 8 290 #define OMAP3430_AUTO_MAILBOXES (1 << 7) 291 #define OMAP3430_AUTO_MAILBOXES_SHIFT 7 292 #define OMAP3430_AUTO_OMAPCTRL (1 << 6) 293 #define OMAP3430_AUTO_OMAPCTRL_SHIFT 6 294 #define OMAP3430ES1_AUTO_FSHOSTUSB (1 << 5) 295 #define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5 296 #define OMAP3430_AUTO_HSOTGUSB (1 << 4) 297 #define OMAP3430_AUTO_HSOTGUSB_SHIFT 4 298 #define OMAP3430ES1_AUTO_D2D (1 << 3) 299 #define OMAP3430ES1_AUTO_D2D_SHIFT 3 300 #define OMAP3430_AUTO_SAD2D (1 << 3) 301 #define OMAP3430_AUTO_SAD2D_SHIFT 3 302 #define OMAP3430_AUTO_SSI (1 << 0) 303 #define OMAP3430_AUTO_SSI_SHIFT 0 304 305 /* CM_AUTOIDLE2_CORE */ 306 #define OMAP3430_AUTO_PKA (1 << 4) 307 #define OMAP3430_AUTO_PKA_SHIFT 4 308 #define OMAP3430_AUTO_AES1 (1 << 3) 309 #define OMAP3430_AUTO_AES1_SHIFT 3 310 #define OMAP3430_AUTO_RNG (1 << 2) 311 #define OMAP3430_AUTO_RNG_SHIFT 2 312 #define OMAP3430_AUTO_SHA11 (1 << 1) 313 #define OMAP3430_AUTO_SHA11_SHIFT 1 314 #define OMAP3430_AUTO_DES1 (1 << 0) 315 #define OMAP3430_AUTO_DES1_SHIFT 0 316 317 /* CM_AUTOIDLE3_CORE */ 318 #define OMAP3430ES2_AUTO_USBHOST (1 << 0) 319 #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 320 #define OMAP3430ES2_AUTO_USBTLL (1 << 2) 321 #define OMAP3430ES2_AUTO_USBTLL_SHIFT 2 322 #define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2) 323 #define OMAP3430_AUTO_MAD2D_SHIFT 3 324 #define OMAP3430_AUTO_MAD2D (1 << 3) 325 326 /* CM_CLKSEL_CORE */ 327 #define OMAP3430_CLKSEL_SSI_SHIFT 8 328 #define OMAP3430_CLKSEL_SSI_MASK (0xf << 8) 329 #define OMAP3430_CLKSEL_GPT11_MASK (1 << 7) 330 #define OMAP3430_CLKSEL_GPT11_SHIFT 7 331 #define OMAP3430_CLKSEL_GPT10_MASK (1 << 6) 332 #define OMAP3430_CLKSEL_GPT10_SHIFT 6 333 #define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4 334 #define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4) 335 #define OMAP3430_CLKSEL_L4_SHIFT 2 336 #define OMAP3430_CLKSEL_L4_MASK (0x3 << 2) 337 #define OMAP3430_CLKSEL_L3_SHIFT 0 338 #define OMAP3430_CLKSEL_L3_MASK (0x3 << 0) 339 340 /* CM_CLKSTCTRL_CORE */ 341 #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4 342 #define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4) 343 #define OMAP3430_CLKTRCTRL_L4_SHIFT 2 344 #define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2) 345 #define OMAP3430_CLKTRCTRL_L3_SHIFT 0 346 #define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0) 347 348 /* CM_CLKSTST_CORE */ 349 #define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT 2 350 #define OMAP3430ES1_CLKACTIVITY_D2D_MASK (1 << 2) 351 #define OMAP3430_CLKACTIVITY_L4_SHIFT 1 352 #define OMAP3430_CLKACTIVITY_L4_MASK (1 << 1) 353 #define OMAP3430_CLKACTIVITY_L3_SHIFT 0 354 #define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0) 355 356 /* CM_FCLKEN_GFX */ 357 #define OMAP3430ES1_EN_3D (1 << 2) 358 #define OMAP3430ES1_EN_3D_SHIFT 2 359 #define OMAP3430ES1_EN_2D (1 << 1) 360 #define OMAP3430ES1_EN_2D_SHIFT 1 361 362 /* CM_ICLKEN_GFX specific bits */ 363 364 /* CM_IDLEST_GFX specific bits */ 365 366 /* CM_CLKSEL_GFX specific bits */ 367 368 /* CM_SLEEPDEP_GFX specific bits */ 369 370 /* CM_CLKSTCTRL_GFX */ 371 #define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0 372 #define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0) 373 374 /* CM_CLKSTST_GFX */ 375 #define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT 0 376 #define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0) 377 378 /* CM_FCLKEN_SGX */ 379 #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1 380 #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1) 381 382 /* CM_ICLKEN_SGX */ 383 #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0 384 #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0) 385 386 /* CM_CLKSEL_SGX */ 387 #define OMAP3430ES2_CLKSEL_SGX_SHIFT 0 388 #define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0) 389 390 /* CM_CLKSTCTRL_SGX */ 391 #define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT 0 392 #define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0) 393 394 /* CM_CLKSTST_SGX */ 395 #define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT 0 396 #define OMAP3430ES2_CLKACTIVITY_SGX_MASK (1 << 0) 397 398 /* CM_FCLKEN_WKUP specific bits */ 399 #define OMAP3430ES2_EN_USIMOCP_SHIFT 9 400 #define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9) 401 402 /* CM_ICLKEN_WKUP specific bits */ 403 #define OMAP3430_EN_WDT1 (1 << 4) 404 #define OMAP3430_EN_WDT1_SHIFT 4 405 #define OMAP3430_EN_32KSYNC (1 << 2) 406 #define OMAP3430_EN_32KSYNC_SHIFT 2 407 408 /* CM_IDLEST_WKUP specific bits */ 409 #define OMAP3430ES2_ST_USIMOCP_SHIFT 9 410 #define OMAP3430ES2_ST_USIMOCP_MASK (1 << 9) 411 #define OMAP3430_ST_WDT2_SHIFT 5 412 #define OMAP3430_ST_WDT2_MASK (1 << 5) 413 #define OMAP3430_ST_WDT1_SHIFT 4 414 #define OMAP3430_ST_WDT1_MASK (1 << 4) 415 #define OMAP3430_ST_32KSYNC_SHIFT 2 416 #define OMAP3430_ST_32KSYNC_MASK (1 << 2) 417 418 /* CM_AUTOIDLE_WKUP */ 419 #define OMAP3430ES2_AUTO_USIMOCP (1 << 9) 420 #define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9 421 #define OMAP3430_AUTO_WDT2 (1 << 5) 422 #define OMAP3430_AUTO_WDT2_SHIFT 5 423 #define OMAP3430_AUTO_WDT1 (1 << 4) 424 #define OMAP3430_AUTO_WDT1_SHIFT 4 425 #define OMAP3430_AUTO_GPIO1 (1 << 3) 426 #define OMAP3430_AUTO_GPIO1_SHIFT 3 427 #define OMAP3430_AUTO_32KSYNC (1 << 2) 428 #define OMAP3430_AUTO_32KSYNC_SHIFT 2 429 #define OMAP3430_AUTO_GPT12 (1 << 1) 430 #define OMAP3430_AUTO_GPT12_SHIFT 1 431 #define OMAP3430_AUTO_GPT1 (1 << 0) 432 #define OMAP3430_AUTO_GPT1_SHIFT 0 433 434 /* CM_CLKSEL_WKUP */ 435 #define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3) 436 #define OMAP3430_CLKSEL_RM_SHIFT 1 437 #define OMAP3430_CLKSEL_RM_MASK (0x3 << 1) 438 #define OMAP3430_CLKSEL_GPT1_SHIFT 0 439 #define OMAP3430_CLKSEL_GPT1_MASK (1 << 0) 440 441 /* CM_CLKEN_PLL */ 442 #define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31 443 #define OMAP3430_PWRDN_CAM_SHIFT 30 444 #define OMAP3430_PWRDN_DSS1_SHIFT 29 445 #define OMAP3430_PWRDN_TV_SHIFT 28 446 #define OMAP3430_PWRDN_96M_SHIFT 27 447 #define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24 448 #define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24) 449 #define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20 450 #define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20) 451 #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19 452 #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19) 453 #define OMAP3430_EN_PERIPH_DPLL_SHIFT 16 454 #define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16) 455 #define OMAP3430_PWRDN_EMU_CORE_SHIFT 12 456 #define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8 457 #define OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8) 458 #define OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4 459 #define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4) 460 #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3 461 #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3) 462 #define OMAP3430_EN_CORE_DPLL_SHIFT 0 463 #define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0) 464 465 /* CM_CLKEN2_PLL */ 466 #define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10 467 #define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8) 468 #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4 469 #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4) 470 #define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3 471 #define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0 472 #define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0) 473 474 /* CM_IDLEST_CKGEN */ 475 #define OMAP3430_ST_54M_CLK (1 << 5) 476 #define OMAP3430_ST_12M_CLK (1 << 4) 477 #define OMAP3430_ST_48M_CLK (1 << 3) 478 #define OMAP3430_ST_96M_CLK (1 << 2) 479 #define OMAP3430_ST_PERIPH_CLK_SHIFT 1 480 #define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1) 481 #define OMAP3430_ST_CORE_CLK_SHIFT 0 482 #define OMAP3430_ST_CORE_CLK_MASK (1 << 0) 483 484 /* CM_IDLEST2_CKGEN */ 485 #define OMAP3430ES2_ST_USIM_CLK_SHIFT 2 486 #define OMAP3430ES2_ST_USIM_CLK_MASK (1 << 2) 487 #define OMAP3430ES2_ST_120M_CLK_SHIFT 1 488 #define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1) 489 #define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0 490 #define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0) 491 492 /* CM_AUTOIDLE_PLL */ 493 #define OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3 494 #define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3) 495 #define OMAP3430_AUTO_CORE_DPLL_SHIFT 0 496 #define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0) 497 498 /* CM_AUTOIDLE2_PLL */ 499 #define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT 0 500 #define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0) 501 502 /* CM_CLKSEL1_PLL */ 503 /* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */ 504 #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27 505 #define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27) 506 #define OMAP3430_CORE_DPLL_MULT_SHIFT 16 507 #define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) 508 #define OMAP3430_CORE_DPLL_DIV_SHIFT 8 509 #define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8) 510 #define OMAP3430_SOURCE_96M_SHIFT 6 511 #define OMAP3430_SOURCE_96M_MASK (1 << 6) 512 #define OMAP3430_SOURCE_54M_SHIFT 5 513 #define OMAP3430_SOURCE_54M_MASK (1 << 5) 514 #define OMAP3430_SOURCE_48M_SHIFT 3 515 #define OMAP3430_SOURCE_48M_MASK (1 << 3) 516 517 /* CM_CLKSEL2_PLL */ 518 #define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8 519 #define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8) 520 #define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0 521 #define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0) 522 523 /* CM_CLKSEL3_PLL */ 524 #define OMAP3430_DIV_96M_SHIFT 0 525 #define OMAP3430_DIV_96M_MASK (0x1f << 0) 526 527 /* CM_CLKSEL4_PLL */ 528 #define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8 529 #define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8) 530 #define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0 531 #define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0) 532 533 /* CM_CLKSEL5_PLL */ 534 #define OMAP3430ES2_DIV_120M_SHIFT 0 535 #define OMAP3430ES2_DIV_120M_MASK (0x1f << 0) 536 537 /* CM_CLKOUT_CTRL */ 538 #define OMAP3430_CLKOUT2_EN_SHIFT 7 539 #define OMAP3430_CLKOUT2_EN (1 << 7) 540 #define OMAP3430_CLKOUT2_DIV_SHIFT 3 541 #define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3) 542 #define OMAP3430_CLKOUT2SOURCE_SHIFT 0 543 #define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0) 544 545 /* CM_FCLKEN_DSS */ 546 #define OMAP3430_EN_TV (1 << 2) 547 #define OMAP3430_EN_TV_SHIFT 2 548 #define OMAP3430_EN_DSS2 (1 << 1) 549 #define OMAP3430_EN_DSS2_SHIFT 1 550 #define OMAP3430_EN_DSS1 (1 << 0) 551 #define OMAP3430_EN_DSS1_SHIFT 0 552 553 /* CM_ICLKEN_DSS */ 554 #define OMAP3430_CM_ICLKEN_DSS_EN_DSS (1 << 0) 555 #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 556 557 /* CM_IDLEST_DSS */ 558 #define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1 559 #define OMAP3430ES2_ST_DSS_IDLE_MASK (1 << 1) 560 #define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0 561 #define OMAP3430ES2_ST_DSS_STDBY_MASK (1 << 0) 562 #define OMAP3430ES1_ST_DSS_SHIFT 0 563 #define OMAP3430ES1_ST_DSS_MASK (1 << 0) 564 565 /* CM_AUTOIDLE_DSS */ 566 #define OMAP3430_AUTO_DSS (1 << 0) 567 #define OMAP3430_AUTO_DSS_SHIFT 0 568 569 /* CM_CLKSEL_DSS */ 570 #define OMAP3430_CLKSEL_TV_SHIFT 8 571 #define OMAP3430_CLKSEL_TV_MASK (0x1f << 8) 572 #define OMAP3430_CLKSEL_DSS1_SHIFT 0 573 #define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0) 574 575 /* CM_SLEEPDEP_DSS specific bits */ 576 577 /* CM_CLKSTCTRL_DSS */ 578 #define OMAP3430_CLKTRCTRL_DSS_SHIFT 0 579 #define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0) 580 581 /* CM_CLKSTST_DSS */ 582 #define OMAP3430_CLKACTIVITY_DSS_SHIFT 0 583 #define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0) 584 585 /* CM_FCLKEN_CAM specific bits */ 586 #define OMAP3430_EN_CSI2 (1 << 1) 587 #define OMAP3430_EN_CSI2_SHIFT 1 588 589 /* CM_ICLKEN_CAM specific bits */ 590 591 /* CM_IDLEST_CAM */ 592 #define OMAP3430_ST_CAM (1 << 0) 593 594 /* CM_AUTOIDLE_CAM */ 595 #define OMAP3430_AUTO_CAM (1 << 0) 596 #define OMAP3430_AUTO_CAM_SHIFT 0 597 598 /* CM_CLKSEL_CAM */ 599 #define OMAP3430_CLKSEL_CAM_SHIFT 0 600 #define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0) 601 602 /* CM_SLEEPDEP_CAM specific bits */ 603 604 /* CM_CLKSTCTRL_CAM */ 605 #define OMAP3430_CLKTRCTRL_CAM_SHIFT 0 606 #define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0) 607 608 /* CM_CLKSTST_CAM */ 609 #define OMAP3430_CLKACTIVITY_CAM_SHIFT 0 610 #define OMAP3430_CLKACTIVITY_CAM_MASK (1 << 0) 611 612 /* CM_FCLKEN_PER specific bits */ 613 614 /* CM_ICLKEN_PER specific bits */ 615 616 /* CM_IDLEST_PER */ 617 #define OMAP3430_ST_WDT3_SHIFT 12 618 #define OMAP3430_ST_WDT3_MASK (1 << 12) 619 #define OMAP3430_ST_MCBSP4_SHIFT 2 620 #define OMAP3430_ST_MCBSP4_MASK (1 << 2) 621 #define OMAP3430_ST_MCBSP3_SHIFT 1 622 #define OMAP3430_ST_MCBSP3_MASK (1 << 1) 623 #define OMAP3430_ST_MCBSP2_SHIFT 0 624 #define OMAP3430_ST_MCBSP2_MASK (1 << 0) 625 626 /* CM_AUTOIDLE_PER */ 627 #define OMAP3430_AUTO_GPIO6 (1 << 17) 628 #define OMAP3430_AUTO_GPIO6_SHIFT 17 629 #define OMAP3430_AUTO_GPIO5 (1 << 16) 630 #define OMAP3430_AUTO_GPIO5_SHIFT 16 631 #define OMAP3430_AUTO_GPIO4 (1 << 15) 632 #define OMAP3430_AUTO_GPIO4_SHIFT 15 633 #define OMAP3430_AUTO_GPIO3 (1 << 14) 634 #define OMAP3430_AUTO_GPIO3_SHIFT 14 635 #define OMAP3430_AUTO_GPIO2 (1 << 13) 636 #define OMAP3430_AUTO_GPIO2_SHIFT 13 637 #define OMAP3430_AUTO_WDT3 (1 << 12) 638 #define OMAP3430_AUTO_WDT3_SHIFT 12 639 #define OMAP3430_AUTO_UART3 (1 << 11) 640 #define OMAP3430_AUTO_UART3_SHIFT 11 641 #define OMAP3430_AUTO_GPT9 (1 << 10) 642 #define OMAP3430_AUTO_GPT9_SHIFT 10 643 #define OMAP3430_AUTO_GPT8 (1 << 9) 644 #define OMAP3430_AUTO_GPT8_SHIFT 9 645 #define OMAP3430_AUTO_GPT7 (1 << 8) 646 #define OMAP3430_AUTO_GPT7_SHIFT 8 647 #define OMAP3430_AUTO_GPT6 (1 << 7) 648 #define OMAP3430_AUTO_GPT6_SHIFT 7 649 #define OMAP3430_AUTO_GPT5 (1 << 6) 650 #define OMAP3430_AUTO_GPT5_SHIFT 6 651 #define OMAP3430_AUTO_GPT4 (1 << 5) 652 #define OMAP3430_AUTO_GPT4_SHIFT 5 653 #define OMAP3430_AUTO_GPT3 (1 << 4) 654 #define OMAP3430_AUTO_GPT3_SHIFT 4 655 #define OMAP3430_AUTO_GPT2 (1 << 3) 656 #define OMAP3430_AUTO_GPT2_SHIFT 3 657 #define OMAP3430_AUTO_MCBSP4 (1 << 2) 658 #define OMAP3430_AUTO_MCBSP4_SHIFT 2 659 #define OMAP3430_AUTO_MCBSP3 (1 << 1) 660 #define OMAP3430_AUTO_MCBSP3_SHIFT 1 661 #define OMAP3430_AUTO_MCBSP2 (1 << 0) 662 #define OMAP3430_AUTO_MCBSP2_SHIFT 0 663 664 /* CM_CLKSEL_PER */ 665 #define OMAP3430_CLKSEL_GPT9_MASK (1 << 7) 666 #define OMAP3430_CLKSEL_GPT9_SHIFT 7 667 #define OMAP3430_CLKSEL_GPT8_MASK (1 << 6) 668 #define OMAP3430_CLKSEL_GPT8_SHIFT 6 669 #define OMAP3430_CLKSEL_GPT7_MASK (1 << 5) 670 #define OMAP3430_CLKSEL_GPT7_SHIFT 5 671 #define OMAP3430_CLKSEL_GPT6_MASK (1 << 4) 672 #define OMAP3430_CLKSEL_GPT6_SHIFT 4 673 #define OMAP3430_CLKSEL_GPT5_MASK (1 << 3) 674 #define OMAP3430_CLKSEL_GPT5_SHIFT 3 675 #define OMAP3430_CLKSEL_GPT4_MASK (1 << 2) 676 #define OMAP3430_CLKSEL_GPT4_SHIFT 2 677 #define OMAP3430_CLKSEL_GPT3_MASK (1 << 1) 678 #define OMAP3430_CLKSEL_GPT3_SHIFT 1 679 #define OMAP3430_CLKSEL_GPT2_MASK (1 << 0) 680 #define OMAP3430_CLKSEL_GPT2_SHIFT 0 681 682 /* CM_SLEEPDEP_PER specific bits */ 683 #define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2 (1 << 2) 684 685 /* CM_CLKSTCTRL_PER */ 686 #define OMAP3430_CLKTRCTRL_PER_SHIFT 0 687 #define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0) 688 689 /* CM_CLKSTST_PER */ 690 #define OMAP3430_CLKACTIVITY_PER_SHIFT 0 691 #define OMAP3430_CLKACTIVITY_PER_MASK (1 << 0) 692 693 /* CM_CLKSEL1_EMU */ 694 #define OMAP3430_DIV_DPLL4_SHIFT 24 695 #define OMAP3430_DIV_DPLL4_MASK (0x1f << 24) 696 #define OMAP3430_DIV_DPLL3_SHIFT 16 697 #define OMAP3430_DIV_DPLL3_MASK (0x1f << 16) 698 #define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 699 #define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11) 700 #define OMAP3430_CLKSEL_PCLK_SHIFT 8 701 #define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8) 702 #define OMAP3430_CLKSEL_PCLKX2_SHIFT 6 703 #define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6) 704 #define OMAP3430_CLKSEL_ATCLK_SHIFT 4 705 #define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4) 706 #define OMAP3430_TRACE_MUX_CTRL_SHIFT 2 707 #define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2) 708 #define OMAP3430_MUX_CTRL_SHIFT 0 709 #define OMAP3430_MUX_CTRL_MASK (0x3 << 0) 710 711 /* CM_CLKSTCTRL_EMU */ 712 #define OMAP3430_CLKTRCTRL_EMU_SHIFT 0 713 #define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0) 714 715 /* CM_CLKSTST_EMU */ 716 #define OMAP3430_CLKACTIVITY_EMU_SHIFT 0 717 #define OMAP3430_CLKACTIVITY_EMU_MASK (1 << 0) 718 719 /* CM_CLKSEL2_EMU specific bits */ 720 #define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8 721 #define OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8) 722 #define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0 723 #define OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0) 724 725 /* CM_CLKSEL3_EMU specific bits */ 726 #define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8 727 #define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8) 728 #define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0 729 #define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0) 730 731 /* CM_POLCTRL */ 732 #define OMAP3430_CLKOUT2_POL (1 << 0) 733 734 /* CM_IDLEST_NEON */ 735 #define OMAP3430_ST_NEON (1 << 0) 736 737 /* CM_CLKSTCTRL_NEON */ 738 #define OMAP3430_CLKTRCTRL_NEON_SHIFT 0 739 #define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0) 740 741 /* CM_FCLKEN_USBHOST */ 742 #define OMAP3430ES2_EN_USBHOST2_SHIFT 1 743 #define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1) 744 #define OMAP3430ES2_EN_USBHOST1_SHIFT 0 745 #define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0) 746 747 /* CM_ICLKEN_USBHOST */ 748 #define OMAP3430ES2_EN_USBHOST_SHIFT 0 749 #define OMAP3430ES2_EN_USBHOST_MASK (1 << 0) 750 751 /* CM_IDLEST_USBHOST */ 752 #define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1 753 #define OMAP3430ES2_ST_USBHOST_IDLE_MASK (1 << 1) 754 #define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0 755 #define OMAP3430ES2_ST_USBHOST_STDBY_MASK (1 << 0) 756 757 /* CM_AUTOIDLE_USBHOST */ 758 #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 759 #define OMAP3430ES2_AUTO_USBHOST_MASK (1 << 0) 760 761 /* CM_SLEEPDEP_USBHOST */ 762 #define OMAP3430ES2_EN_MPU_SHIFT 1 763 #define OMAP3430ES2_EN_MPU_MASK (1 << 1) 764 #define OMAP3430ES2_EN_IVA2_SHIFT 2 765 #define OMAP3430ES2_EN_IVA2_MASK (1 << 2) 766 767 /* CM_CLKSTCTRL_USBHOST */ 768 #define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0 769 #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0) 770 771 /* CM_CLKSTST_USBHOST */ 772 #define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0 773 #define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0) 774 775 #endif 776