1 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H 2 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H 3 4 /* 5 * OMAP3430 Clock Management register bits 6 * 7 * Copyright (C) 2007-2008 Texas Instruments, Inc. 8 * Copyright (C) 2007-2008 Nokia Corporation 9 * 10 * Written by Paul Walmsley 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License version 2 as 14 * published by the Free Software Foundation. 15 */ 16 17 #include "cm.h" 18 19 /* Bits shared between registers */ 20 21 /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ 22 #define OMAP3430ES2_EN_MMC3_MASK (1 << 30) 23 #define OMAP3430ES2_EN_MMC3_SHIFT 30 24 #define OMAP3430_EN_MSPRO (1 << 23) 25 #define OMAP3430_EN_MSPRO_SHIFT 23 26 #define OMAP3430_EN_HDQ (1 << 22) 27 #define OMAP3430_EN_HDQ_SHIFT 22 28 #define OMAP3430ES1_EN_FSHOSTUSB (1 << 5) 29 #define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5 30 #define OMAP3430ES1_EN_D2D (1 << 3) 31 #define OMAP3430ES1_EN_D2D_SHIFT 3 32 #define OMAP3430_EN_SSI (1 << 0) 33 #define OMAP3430_EN_SSI_SHIFT 0 34 35 /* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */ 36 #define OMAP3430ES2_EN_USBTLL_SHIFT 2 37 #define OMAP3430ES2_EN_USBTLL_MASK (1 << 2) 38 39 /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ 40 #define OMAP3430_EN_WDT2 (1 << 5) 41 #define OMAP3430_EN_WDT2_SHIFT 5 42 43 /* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */ 44 #define OMAP3430_EN_CAM (1 << 0) 45 #define OMAP3430_EN_CAM_SHIFT 0 46 47 /* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */ 48 #define OMAP3430_EN_WDT3 (1 << 12) 49 #define OMAP3430_EN_WDT3_SHIFT 12 50 51 /* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */ 52 #define OMAP3430_OVERRIDE_ENABLE (1 << 19) 53 54 55 /* Bits specific to each register */ 56 57 /* CM_FCLKEN_IVA2 */ 58 #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2 (1 << 0) 59 #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0 60 61 /* CM_CLKEN_PLL_IVA2 */ 62 #define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8 63 #define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8) 64 #define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4 65 #define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4) 66 #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3 67 #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3) 68 #define OMAP3430_EN_IVA2_DPLL_SHIFT 0 69 #define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0) 70 71 /* CM_IDLEST_IVA2 */ 72 #define OMAP3430_ST_IVA2 (1 << 0) 73 74 /* CM_IDLEST_PLL_IVA2 */ 75 #define OMAP3430_ST_IVA2_CLK (1 << 0) 76 77 /* CM_AUTOIDLE_PLL_IVA2 */ 78 #define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0 79 #define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0) 80 81 /* CM_CLKSEL1_PLL_IVA2 */ 82 #define OMAP3430_IVA2_CLK_SRC_SHIFT 19 83 #define OMAP3430_IVA2_CLK_SRC_MASK (0x3 << 19) 84 #define OMAP3430_IVA2_DPLL_MULT_SHIFT 8 85 #define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) 86 #define OMAP3430_IVA2_DPLL_DIV_SHIFT 0 87 #define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0) 88 89 /* CM_CLKSEL2_PLL_IVA2 */ 90 #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0 91 #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0) 92 93 /* CM_CLKSTCTRL_IVA2 */ 94 #define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0 95 #define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0) 96 97 /* CM_CLKSTST_IVA2 */ 98 #define OMAP3430_CLKACTIVITY_IVA2 (1 << 0) 99 100 /* CM_REVISION specific bits */ 101 102 /* CM_SYSCONFIG specific bits */ 103 104 /* CM_CLKEN_PLL_MPU */ 105 #define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8 106 #define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8) 107 #define OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4 108 #define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4) 109 #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3 110 #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3) 111 #define OMAP3430_EN_MPU_DPLL_SHIFT 0 112 #define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0) 113 114 /* CM_IDLEST_MPU */ 115 #define OMAP3430_ST_MPU (1 << 0) 116 117 /* CM_IDLEST_PLL_MPU */ 118 #define OMAP3430_ST_MPU_CLK (1 << 0) 119 #define OMAP3430_ST_IVA2_CLK_MASK (1 << 0) 120 121 /* CM_IDLEST_PLL_MPU */ 122 #define OMAP3430_ST_MPU_CLK_MASK (1 << 0) 123 124 /* CM_AUTOIDLE_PLL_MPU */ 125 #define OMAP3430_AUTO_MPU_DPLL_SHIFT 0 126 #define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0) 127 128 /* CM_CLKSEL1_PLL_MPU */ 129 #define OMAP3430_MPU_CLK_SRC_SHIFT 19 130 #define OMAP3430_MPU_CLK_SRC_MASK (0x3 << 19) 131 #define OMAP3430_MPU_DPLL_MULT_SHIFT 8 132 #define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) 133 #define OMAP3430_MPU_DPLL_DIV_SHIFT 0 134 #define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0) 135 136 /* CM_CLKSEL2_PLL_MPU */ 137 #define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0 138 #define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0) 139 140 /* CM_CLKSTCTRL_MPU */ 141 #define OMAP3430_CLKTRCTRL_MPU_SHIFT 0 142 #define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0) 143 144 /* CM_CLKSTST_MPU */ 145 #define OMAP3430_CLKACTIVITY_MPU (1 << 0) 146 147 /* CM_FCLKEN1_CORE specific bits */ 148 149 /* CM_ICLKEN1_CORE specific bits */ 150 #define OMAP3430_EN_ICR (1 << 29) 151 #define OMAP3430_EN_ICR_SHIFT 29 152 #define OMAP3430_EN_AES2 (1 << 28) 153 #define OMAP3430_EN_AES2_SHIFT 28 154 #define OMAP3430_EN_SHA12 (1 << 27) 155 #define OMAP3430_EN_SHA12_SHIFT 27 156 #define OMAP3430_EN_DES2 (1 << 26) 157 #define OMAP3430_EN_DES2_SHIFT 26 158 #define OMAP3430ES1_EN_FAC (1 << 8) 159 #define OMAP3430ES1_EN_FAC_SHIFT 8 160 #define OMAP3430_EN_MAILBOXES (1 << 7) 161 #define OMAP3430_EN_MAILBOXES_SHIFT 7 162 #define OMAP3430_EN_OMAPCTRL (1 << 6) 163 #define OMAP3430_EN_OMAPCTRL_SHIFT 6 164 #define OMAP3430_EN_SDRC (1 << 1) 165 #define OMAP3430_EN_SDRC_SHIFT 1 166 167 /* CM_ICLKEN2_CORE */ 168 #define OMAP3430_EN_PKA (1 << 4) 169 #define OMAP3430_EN_PKA_SHIFT 4 170 #define OMAP3430_EN_AES1 (1 << 3) 171 #define OMAP3430_EN_AES1_SHIFT 3 172 #define OMAP3430_EN_RNG (1 << 2) 173 #define OMAP3430_EN_RNG_SHIFT 2 174 #define OMAP3430_EN_SHA11 (1 << 1) 175 #define OMAP3430_EN_SHA11_SHIFT 1 176 #define OMAP3430_EN_DES1 (1 << 0) 177 #define OMAP3430_EN_DES1_SHIFT 0 178 179 /* CM_FCLKEN3_CORE specific bits */ 180 #define OMAP3430ES2_EN_TS_SHIFT 1 181 #define OMAP3430ES2_EN_TS_MASK (1 << 1) 182 #define OMAP3430ES2_EN_CPEFUSE_SHIFT 0 183 #define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0) 184 185 /* CM_IDLEST1_CORE specific bits */ 186 #define OMAP3430_ST_ICR (1 << 29) 187 #define OMAP3430_ST_AES2 (1 << 28) 188 #define OMAP3430_ST_SHA12 (1 << 27) 189 #define OMAP3430_ST_DES2 (1 << 26) 190 #define OMAP3430_ST_MSPRO (1 << 23) 191 #define OMAP3430_ST_HDQ (1 << 22) 192 #define OMAP3430ES1_ST_FAC (1 << 8) 193 #define OMAP3430ES1_ST_MAILBOXES (1 << 7) 194 #define OMAP3430_ST_OMAPCTRL (1 << 6) 195 #define OMAP3430_ST_SDMA (1 << 2) 196 #define OMAP3430_ST_SDRC (1 << 1) 197 #define OMAP3430_ST_SSI (1 << 0) 198 199 /* CM_IDLEST2_CORE */ 200 #define OMAP3430_ST_PKA (1 << 4) 201 #define OMAP3430_ST_AES1 (1 << 3) 202 #define OMAP3430_ST_RNG (1 << 2) 203 #define OMAP3430_ST_SHA11 (1 << 1) 204 #define OMAP3430_ST_DES1 (1 << 0) 205 206 /* CM_IDLEST3_CORE */ 207 #define OMAP3430ES2_ST_USBTLL_SHIFT 2 208 #define OMAP3430ES2_ST_USBTLL_MASK (1 << 2) 209 210 /* CM_AUTOIDLE1_CORE */ 211 #define OMAP3430_AUTO_AES2 (1 << 28) 212 #define OMAP3430_AUTO_AES2_SHIFT 28 213 #define OMAP3430_AUTO_SHA12 (1 << 27) 214 #define OMAP3430_AUTO_SHA12_SHIFT 27 215 #define OMAP3430_AUTO_DES2 (1 << 26) 216 #define OMAP3430_AUTO_DES2_SHIFT 26 217 #define OMAP3430_AUTO_MMC2 (1 << 25) 218 #define OMAP3430_AUTO_MMC2_SHIFT 25 219 #define OMAP3430_AUTO_MMC1 (1 << 24) 220 #define OMAP3430_AUTO_MMC1_SHIFT 24 221 #define OMAP3430_AUTO_MSPRO (1 << 23) 222 #define OMAP3430_AUTO_MSPRO_SHIFT 23 223 #define OMAP3430_AUTO_HDQ (1 << 22) 224 #define OMAP3430_AUTO_HDQ_SHIFT 22 225 #define OMAP3430_AUTO_MCSPI4 (1 << 21) 226 #define OMAP3430_AUTO_MCSPI4_SHIFT 21 227 #define OMAP3430_AUTO_MCSPI3 (1 << 20) 228 #define OMAP3430_AUTO_MCSPI3_SHIFT 20 229 #define OMAP3430_AUTO_MCSPI2 (1 << 19) 230 #define OMAP3430_AUTO_MCSPI2_SHIFT 19 231 #define OMAP3430_AUTO_MCSPI1 (1 << 18) 232 #define OMAP3430_AUTO_MCSPI1_SHIFT 18 233 #define OMAP3430_AUTO_I2C3 (1 << 17) 234 #define OMAP3430_AUTO_I2C3_SHIFT 17 235 #define OMAP3430_AUTO_I2C2 (1 << 16) 236 #define OMAP3430_AUTO_I2C2_SHIFT 16 237 #define OMAP3430_AUTO_I2C1 (1 << 15) 238 #define OMAP3430_AUTO_I2C1_SHIFT 15 239 #define OMAP3430_AUTO_UART2 (1 << 14) 240 #define OMAP3430_AUTO_UART2_SHIFT 14 241 #define OMAP3430_AUTO_UART1 (1 << 13) 242 #define OMAP3430_AUTO_UART1_SHIFT 13 243 #define OMAP3430_AUTO_GPT11 (1 << 12) 244 #define OMAP3430_AUTO_GPT11_SHIFT 12 245 #define OMAP3430_AUTO_GPT10 (1 << 11) 246 #define OMAP3430_AUTO_GPT10_SHIFT 11 247 #define OMAP3430_AUTO_MCBSP5 (1 << 10) 248 #define OMAP3430_AUTO_MCBSP5_SHIFT 10 249 #define OMAP3430_AUTO_MCBSP1 (1 << 9) 250 #define OMAP3430_AUTO_MCBSP1_SHIFT 9 251 #define OMAP3430ES1_AUTO_FAC (1 << 8) 252 #define OMAP3430ES1_AUTO_FAC_SHIFT 8 253 #define OMAP3430_AUTO_MAILBOXES (1 << 7) 254 #define OMAP3430_AUTO_MAILBOXES_SHIFT 7 255 #define OMAP3430_AUTO_OMAPCTRL (1 << 6) 256 #define OMAP3430_AUTO_OMAPCTRL_SHIFT 6 257 #define OMAP3430ES1_AUTO_FSHOSTUSB (1 << 5) 258 #define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5 259 #define OMAP3430_AUTO_HSOTGUSB (1 << 4) 260 #define OMAP3430_AUTO_HSOTGUSB_SHIFT 4 261 #define OMAP3430ES1_AUTO_D2D (1 << 3) 262 #define OMAP3430ES1_AUTO_D2D_SHIFT 3 263 #define OMAP3430_AUTO_SSI (1 << 0) 264 #define OMAP3430_AUTO_SSI_SHIFT 0 265 266 /* CM_AUTOIDLE2_CORE */ 267 #define OMAP3430_AUTO_PKA (1 << 4) 268 #define OMAP3430_AUTO_PKA_SHIFT 4 269 #define OMAP3430_AUTO_AES1 (1 << 3) 270 #define OMAP3430_AUTO_AES1_SHIFT 3 271 #define OMAP3430_AUTO_RNG (1 << 2) 272 #define OMAP3430_AUTO_RNG_SHIFT 2 273 #define OMAP3430_AUTO_SHA11 (1 << 1) 274 #define OMAP3430_AUTO_SHA11_SHIFT 1 275 #define OMAP3430_AUTO_DES1 (1 << 0) 276 #define OMAP3430_AUTO_DES1_SHIFT 0 277 278 /* CM_AUTOIDLE3_CORE */ 279 #define OMAP3430ES2_AUTO_USBTLL_SHIFT 2 280 #define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2) 281 282 /* CM_CLKSEL_CORE */ 283 #define OMAP3430_CLKSEL_SSI_SHIFT 8 284 #define OMAP3430_CLKSEL_SSI_MASK (0xf << 8) 285 #define OMAP3430_CLKSEL_GPT11_MASK (1 << 7) 286 #define OMAP3430_CLKSEL_GPT11_SHIFT 7 287 #define OMAP3430_CLKSEL_GPT10_MASK (1 << 6) 288 #define OMAP3430_CLKSEL_GPT10_SHIFT 6 289 #define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4 290 #define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4) 291 #define OMAP3430_CLKSEL_L4_SHIFT 2 292 #define OMAP3430_CLKSEL_L4_MASK (0x3 << 2) 293 #define OMAP3430_CLKSEL_L3_SHIFT 0 294 #define OMAP3430_CLKSEL_L3_MASK (0x3 << 0) 295 296 /* CM_CLKSTCTRL_CORE */ 297 #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4 298 #define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4) 299 #define OMAP3430_CLKTRCTRL_L4_SHIFT 2 300 #define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2) 301 #define OMAP3430_CLKTRCTRL_L3_SHIFT 0 302 #define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0) 303 304 /* CM_CLKSTST_CORE */ 305 #define OMAP3430ES1_CLKACTIVITY_D2D (1 << 2) 306 #define OMAP3430_CLKACTIVITY_L4 (1 << 1) 307 #define OMAP3430_CLKACTIVITY_L3 (1 << 0) 308 309 /* CM_FCLKEN_GFX */ 310 #define OMAP3430ES1_EN_3D (1 << 2) 311 #define OMAP3430ES1_EN_3D_SHIFT 2 312 #define OMAP3430ES1_EN_2D (1 << 1) 313 #define OMAP3430ES1_EN_2D_SHIFT 1 314 315 /* CM_ICLKEN_GFX specific bits */ 316 317 /* CM_IDLEST_GFX specific bits */ 318 319 /* CM_CLKSEL_GFX specific bits */ 320 321 /* CM_SLEEPDEP_GFX specific bits */ 322 323 /* CM_CLKSTCTRL_GFX */ 324 #define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0 325 #define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0) 326 327 /* CM_CLKSTST_GFX */ 328 #define OMAP3430ES1_CLKACTIVITY_GFX (1 << 0) 329 330 /* CM_FCLKEN_SGX */ 331 #define OMAP3430ES2_EN_SGX_SHIFT 1 332 #define OMAP3430ES2_EN_SGX_MASK (1 << 1) 333 334 /* CM_CLKSEL_SGX */ 335 #define OMAP3430ES2_CLKSEL_SGX_SHIFT 0 336 #define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0) 337 338 /* CM_FCLKEN_WKUP specific bits */ 339 #define OMAP3430ES2_EN_USIMOCP_SHIFT 9 340 341 /* CM_ICLKEN_WKUP specific bits */ 342 #define OMAP3430_EN_WDT1 (1 << 4) 343 #define OMAP3430_EN_WDT1_SHIFT 4 344 #define OMAP3430_EN_32KSYNC (1 << 2) 345 #define OMAP3430_EN_32KSYNC_SHIFT 2 346 347 /* CM_IDLEST_WKUP specific bits */ 348 #define OMAP3430_ST_WDT2 (1 << 5) 349 #define OMAP3430_ST_WDT1 (1 << 4) 350 #define OMAP3430_ST_32KSYNC (1 << 2) 351 352 /* CM_AUTOIDLE_WKUP */ 353 #define OMAP3430_AUTO_WDT2 (1 << 5) 354 #define OMAP3430_AUTO_WDT2_SHIFT 5 355 #define OMAP3430_AUTO_WDT1 (1 << 4) 356 #define OMAP3430_AUTO_WDT1_SHIFT 4 357 #define OMAP3430_AUTO_GPIO1 (1 << 3) 358 #define OMAP3430_AUTO_GPIO1_SHIFT 3 359 #define OMAP3430_AUTO_32KSYNC (1 << 2) 360 #define OMAP3430_AUTO_32KSYNC_SHIFT 2 361 #define OMAP3430_AUTO_GPT12 (1 << 1) 362 #define OMAP3430_AUTO_GPT12_SHIFT 1 363 #define OMAP3430_AUTO_GPT1 (1 << 0) 364 #define OMAP3430_AUTO_GPT1_SHIFT 0 365 366 /* CM_CLKSEL_WKUP */ 367 #define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3) 368 #define OMAP3430_CLKSEL_RM_SHIFT 1 369 #define OMAP3430_CLKSEL_RM_MASK (0x3 << 1) 370 #define OMAP3430_CLKSEL_GPT1_SHIFT 0 371 #define OMAP3430_CLKSEL_GPT1_MASK (1 << 0) 372 373 /* CM_CLKEN_PLL */ 374 #define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31 375 #define OMAP3430_PWRDN_CAM_SHIFT 30 376 #define OMAP3430_PWRDN_DSS1_SHIFT 29 377 #define OMAP3430_PWRDN_TV_SHIFT 28 378 #define OMAP3430_PWRDN_96M_SHIFT 27 379 #define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24 380 #define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24) 381 #define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20 382 #define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20) 383 #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19 384 #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19) 385 #define OMAP3430_EN_PERIPH_DPLL_SHIFT 16 386 #define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16) 387 #define OMAP3430_PWRDN_EMU_CORE_SHIFT 12 388 #define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8 389 #define OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8) 390 #define OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4 391 #define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4) 392 #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3 393 #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3) 394 #define OMAP3430_EN_CORE_DPLL_SHIFT 0 395 #define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0) 396 397 /* CM_CLKEN2_PLL */ 398 #define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10 399 #define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8) 400 #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4 401 #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4) 402 #define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3 403 #define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0 404 #define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0) 405 406 /* CM_IDLEST_CKGEN */ 407 #define OMAP3430_ST_54M_CLK (1 << 5) 408 #define OMAP3430_ST_12M_CLK (1 << 4) 409 #define OMAP3430_ST_48M_CLK (1 << 3) 410 #define OMAP3430_ST_96M_CLK (1 << 2) 411 #define OMAP3430_ST_PERIPH_CLK (1 << 1) 412 #define OMAP3430_ST_CORE_CLK (1 << 0) 413 414 /* CM_IDLEST2_CKGEN */ 415 #define OMAP3430ES2_ST_120M_CLK_SHIFT 1 416 #define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1) 417 #define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0 418 #define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0) 419 420 /* CM_AUTOIDLE_PLL */ 421 #define OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3 422 #define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3) 423 #define OMAP3430_AUTO_CORE_DPLL_SHIFT 0 424 #define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0) 425 426 /* CM_CLKSEL1_PLL */ 427 /* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */ 428 #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27 429 #define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27) 430 #define OMAP3430_CORE_DPLL_MULT_SHIFT 16 431 #define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) 432 #define OMAP3430_CORE_DPLL_DIV_SHIFT 8 433 #define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8) 434 #define OMAP3430_SOURCE_54M (1 << 5) 435 #define OMAP3430_SOURCE_48M (1 << 3) 436 437 /* CM_CLKSEL2_PLL */ 438 #define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8 439 #define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8) 440 #define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0 441 #define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0) 442 443 /* CM_CLKSEL3_PLL */ 444 #define OMAP3430_DIV_96M_SHIFT 0 445 #define OMAP3430_DIV_96M_MASK (0x1f << 0) 446 447 /* CM_CLKSEL4_PLL */ 448 #define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8 449 #define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8) 450 #define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0 451 #define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0) 452 453 /* CM_CLKSEL5_PLL */ 454 #define OMAP3430ES2_DIV_120M_SHIFT 0 455 #define OMAP3430ES2_DIV_120M_MASK (0x1f << 0) 456 457 /* CM_CLKOUT_CTRL */ 458 #define OMAP3430_CLKOUT2_EN_SHIFT 7 459 #define OMAP3430_CLKOUT2_EN (1 << 7) 460 #define OMAP3430_CLKOUT2_DIV_SHIFT 3 461 #define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3) 462 #define OMAP3430_CLKOUT2SOURCE_SHIFT 0 463 #define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0) 464 465 /* CM_FCLKEN_DSS */ 466 #define OMAP3430_EN_TV (1 << 2) 467 #define OMAP3430_EN_TV_SHIFT 2 468 #define OMAP3430_EN_DSS2 (1 << 1) 469 #define OMAP3430_EN_DSS2_SHIFT 1 470 #define OMAP3430_EN_DSS1 (1 << 0) 471 #define OMAP3430_EN_DSS1_SHIFT 0 472 473 /* CM_ICLKEN_DSS */ 474 #define OMAP3430_CM_ICLKEN_DSS_EN_DSS (1 << 0) 475 #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 476 477 /* CM_IDLEST_DSS */ 478 #define OMAP3430_ST_DSS (1 << 0) 479 480 /* CM_AUTOIDLE_DSS */ 481 #define OMAP3430_AUTO_DSS (1 << 0) 482 #define OMAP3430_AUTO_DSS_SHIFT 0 483 484 /* CM_CLKSEL_DSS */ 485 #define OMAP3430_CLKSEL_TV_SHIFT 8 486 #define OMAP3430_CLKSEL_TV_MASK (0x1f << 8) 487 #define OMAP3430_CLKSEL_DSS1_SHIFT 0 488 #define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0) 489 490 /* CM_SLEEPDEP_DSS specific bits */ 491 492 /* CM_CLKSTCTRL_DSS */ 493 #define OMAP3430_CLKTRCTRL_DSS_SHIFT 0 494 #define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0) 495 496 /* CM_CLKSTST_DSS */ 497 #define OMAP3430_CLKACTIVITY_DSS (1 << 0) 498 499 /* CM_FCLKEN_CAM specific bits */ 500 501 /* CM_ICLKEN_CAM specific bits */ 502 503 /* CM_IDLEST_CAM */ 504 #define OMAP3430_ST_CAM (1 << 0) 505 506 /* CM_AUTOIDLE_CAM */ 507 #define OMAP3430_AUTO_CAM (1 << 0) 508 #define OMAP3430_AUTO_CAM_SHIFT 0 509 510 /* CM_CLKSEL_CAM */ 511 #define OMAP3430_CLKSEL_CAM_SHIFT 0 512 #define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0) 513 514 /* CM_SLEEPDEP_CAM specific bits */ 515 516 /* CM_CLKSTCTRL_CAM */ 517 #define OMAP3430_CLKTRCTRL_CAM_SHIFT 0 518 #define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0) 519 520 /* CM_CLKSTST_CAM */ 521 #define OMAP3430_CLKACTIVITY_CAM (1 << 0) 522 523 /* CM_FCLKEN_PER specific bits */ 524 525 /* CM_ICLKEN_PER specific bits */ 526 527 /* CM_IDLEST_PER */ 528 #define OMAP3430_ST_WDT3 (1 << 12) 529 #define OMAP3430_ST_MCBSP4 (1 << 2) 530 #define OMAP3430_ST_MCBSP3 (1 << 1) 531 #define OMAP3430_ST_MCBSP2 (1 << 0) 532 533 /* CM_AUTOIDLE_PER */ 534 #define OMAP3430_AUTO_GPIO6 (1 << 17) 535 #define OMAP3430_AUTO_GPIO6_SHIFT 17 536 #define OMAP3430_AUTO_GPIO5 (1 << 16) 537 #define OMAP3430_AUTO_GPIO5_SHIFT 16 538 #define OMAP3430_AUTO_GPIO4 (1 << 15) 539 #define OMAP3430_AUTO_GPIO4_SHIFT 15 540 #define OMAP3430_AUTO_GPIO3 (1 << 14) 541 #define OMAP3430_AUTO_GPIO3_SHIFT 14 542 #define OMAP3430_AUTO_GPIO2 (1 << 13) 543 #define OMAP3430_AUTO_GPIO2_SHIFT 13 544 #define OMAP3430_AUTO_WDT3 (1 << 12) 545 #define OMAP3430_AUTO_WDT3_SHIFT 12 546 #define OMAP3430_AUTO_UART3 (1 << 11) 547 #define OMAP3430_AUTO_UART3_SHIFT 11 548 #define OMAP3430_AUTO_GPT9 (1 << 10) 549 #define OMAP3430_AUTO_GPT9_SHIFT 10 550 #define OMAP3430_AUTO_GPT8 (1 << 9) 551 #define OMAP3430_AUTO_GPT8_SHIFT 9 552 #define OMAP3430_AUTO_GPT7 (1 << 8) 553 #define OMAP3430_AUTO_GPT7_SHIFT 8 554 #define OMAP3430_AUTO_GPT6 (1 << 7) 555 #define OMAP3430_AUTO_GPT6_SHIFT 7 556 #define OMAP3430_AUTO_GPT5 (1 << 6) 557 #define OMAP3430_AUTO_GPT5_SHIFT 6 558 #define OMAP3430_AUTO_GPT4 (1 << 5) 559 #define OMAP3430_AUTO_GPT4_SHIFT 5 560 #define OMAP3430_AUTO_GPT3 (1 << 4) 561 #define OMAP3430_AUTO_GPT3_SHIFT 4 562 #define OMAP3430_AUTO_GPT2 (1 << 3) 563 #define OMAP3430_AUTO_GPT2_SHIFT 3 564 #define OMAP3430_AUTO_MCBSP4 (1 << 2) 565 #define OMAP3430_AUTO_MCBSP4_SHIFT 2 566 #define OMAP3430_AUTO_MCBSP3 (1 << 1) 567 #define OMAP3430_AUTO_MCBSP3_SHIFT 1 568 #define OMAP3430_AUTO_MCBSP2 (1 << 0) 569 #define OMAP3430_AUTO_MCBSP2_SHIFT 0 570 571 /* CM_CLKSEL_PER */ 572 #define OMAP3430_CLKSEL_GPT9_MASK (1 << 7) 573 #define OMAP3430_CLKSEL_GPT9_SHIFT 7 574 #define OMAP3430_CLKSEL_GPT8_MASK (1 << 6) 575 #define OMAP3430_CLKSEL_GPT8_SHIFT 6 576 #define OMAP3430_CLKSEL_GPT7_MASK (1 << 5) 577 #define OMAP3430_CLKSEL_GPT7_SHIFT 5 578 #define OMAP3430_CLKSEL_GPT6_MASK (1 << 4) 579 #define OMAP3430_CLKSEL_GPT6_SHIFT 4 580 #define OMAP3430_CLKSEL_GPT5_MASK (1 << 3) 581 #define OMAP3430_CLKSEL_GPT5_SHIFT 3 582 #define OMAP3430_CLKSEL_GPT4_MASK (1 << 2) 583 #define OMAP3430_CLKSEL_GPT4_SHIFT 2 584 #define OMAP3430_CLKSEL_GPT3_MASK (1 << 1) 585 #define OMAP3430_CLKSEL_GPT3_SHIFT 1 586 #define OMAP3430_CLKSEL_GPT2_MASK (1 << 0) 587 #define OMAP3430_CLKSEL_GPT2_SHIFT 0 588 589 /* CM_SLEEPDEP_PER specific bits */ 590 #define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2 (1 << 2) 591 592 /* CM_CLKSTCTRL_PER */ 593 #define OMAP3430_CLKTRCTRL_PER_SHIFT 0 594 #define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0) 595 596 /* CM_CLKSTST_PER */ 597 #define OMAP3430_CLKACTIVITY_PER (1 << 0) 598 599 /* CM_CLKSEL1_EMU */ 600 #define OMAP3430_DIV_DPLL4_SHIFT 24 601 #define OMAP3430_DIV_DPLL4_MASK (0x1f << 24) 602 #define OMAP3430_DIV_DPLL3_SHIFT 16 603 #define OMAP3430_DIV_DPLL3_MASK (0x1f << 16) 604 #define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 605 #define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11) 606 #define OMAP3430_CLKSEL_PCLK_SHIFT 8 607 #define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8) 608 #define OMAP3430_CLKSEL_PCLKX2_SHIFT 6 609 #define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6) 610 #define OMAP3430_CLKSEL_ATCLK_SHIFT 4 611 #define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4) 612 #define OMAP3430_TRACE_MUX_CTRL_SHIFT 2 613 #define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2) 614 #define OMAP3430_MUX_CTRL_SHIFT 0 615 #define OMAP3430_MUX_CTRL_MASK (0x3 << 0) 616 617 /* CM_CLKSTCTRL_EMU */ 618 #define OMAP3430_CLKTRCTRL_EMU_SHIFT 0 619 #define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0) 620 621 /* CM_CLKSTST_EMU */ 622 #define OMAP3430_CLKACTIVITY_EMU (1 << 0) 623 624 /* CM_CLKSEL2_EMU specific bits */ 625 #define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8 626 #define OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8) 627 #define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0 628 #define OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0) 629 630 /* CM_CLKSEL3_EMU specific bits */ 631 #define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8 632 #define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8) 633 #define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0 634 #define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0) 635 636 /* CM_POLCTRL */ 637 #define OMAP3430_CLKOUT2_POL (1 << 0) 638 639 /* CM_IDLEST_NEON */ 640 #define OMAP3430_ST_NEON (1 << 0) 641 642 /* CM_CLKSTCTRL_NEON */ 643 #define OMAP3430_CLKTRCTRL_NEON_SHIFT 0 644 #define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0) 645 646 /* CM_FCLKEN_USBHOST */ 647 #define OMAP3430ES2_EN_USBHOST2_SHIFT 1 648 #define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1) 649 #define OMAP3430ES2_EN_USBHOST1_SHIFT 0 650 #define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0) 651 652 /* CM_ICLKEN_USBHOST */ 653 #define OMAP3430ES2_EN_USBHOST_SHIFT 0 654 #define OMAP3430ES2_EN_USBHOST_MASK (1 << 0) 655 656 /* CM_IDLEST_USBHOST */ 657 658 /* CM_AUTOIDLE_USBHOST */ 659 #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 660 #define OMAP3430ES2_AUTO_USBHOST_MASK (1 << 0) 661 662 /* CM_SLEEPDEP_USBHOST */ 663 #define OMAP3430ES2_EN_MPU_SHIFT 1 664 #define OMAP3430ES2_EN_MPU_MASK (1 << 1) 665 #define OMAP3430ES2_EN_IVA2_SHIFT 2 666 #define OMAP3430ES2_EN_IVA2_MASK (1 << 2) 667 668 /* CM_CLKSTCTRL_USBHOST */ 669 #define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0 670 #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0) 671 672 673 674 #endif 675