1 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H 2 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H 3 4 /* 5 * OMAP3430 Clock Management register bits 6 * 7 * Copyright (C) 2007-2008 Texas Instruments, Inc. 8 * Copyright (C) 2007-2008 Nokia Corporation 9 * 10 * Written by Paul Walmsley 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License version 2 as 14 * published by the Free Software Foundation. 15 */ 16 17 #include "cm.h" 18 19 /* Bits shared between registers */ 20 21 /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ 22 #define OMAP3430ES2_EN_MMC3_MASK (1 << 30) 23 #define OMAP3430ES2_EN_MMC3_SHIFT 30 24 #define OMAP3430_EN_MSPRO (1 << 23) 25 #define OMAP3430_EN_MSPRO_SHIFT 23 26 #define OMAP3430_EN_HDQ (1 << 22) 27 #define OMAP3430_EN_HDQ_SHIFT 22 28 #define OMAP3430ES1_EN_FSHOSTUSB (1 << 5) 29 #define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5 30 #define OMAP3430ES1_EN_D2D (1 << 3) 31 #define OMAP3430ES1_EN_D2D_SHIFT 3 32 #define OMAP3430_EN_SSI (1 << 0) 33 #define OMAP3430_EN_SSI_SHIFT 0 34 35 /* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */ 36 #define OMAP3430ES2_EN_USBTLL_SHIFT 2 37 #define OMAP3430ES2_EN_USBTLL_MASK (1 << 2) 38 39 /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ 40 #define OMAP3430_EN_WDT2 (1 << 5) 41 #define OMAP3430_EN_WDT2_SHIFT 5 42 43 /* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */ 44 #define OMAP3430_EN_CAM (1 << 0) 45 #define OMAP3430_EN_CAM_SHIFT 0 46 47 /* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */ 48 #define OMAP3430_EN_WDT3 (1 << 12) 49 #define OMAP3430_EN_WDT3_SHIFT 12 50 51 /* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */ 52 #define OMAP3430_OVERRIDE_ENABLE (1 << 19) 53 54 55 /* Bits specific to each register */ 56 57 /* CM_FCLKEN_IVA2 */ 58 #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2 (1 << 0) 59 60 /* CM_CLKEN_PLL_IVA2 */ 61 #define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8 62 #define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8) 63 #define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4 64 #define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4) 65 #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3 66 #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3) 67 #define OMAP3430_EN_IVA2_DPLL_SHIFT 0 68 #define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0) 69 70 /* CM_IDLEST_IVA2 */ 71 #define OMAP3430_ST_IVA2 (1 << 0) 72 73 /* CM_IDLEST_PLL_IVA2 */ 74 #define OMAP3430_ST_IVA2_CLK (1 << 0) 75 76 /* CM_AUTOIDLE_PLL_IVA2 */ 77 #define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0 78 #define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0) 79 80 /* CM_CLKSEL1_PLL_IVA2 */ 81 #define OMAP3430_IVA2_CLK_SRC_SHIFT 19 82 #define OMAP3430_IVA2_CLK_SRC_MASK (0x3 << 19) 83 #define OMAP3430_IVA2_DPLL_MULT_SHIFT 8 84 #define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) 85 #define OMAP3430_IVA2_DPLL_DIV_SHIFT 0 86 #define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0) 87 88 /* CM_CLKSEL2_PLL_IVA2 */ 89 #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0 90 #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0) 91 92 /* CM_CLKSTCTRL_IVA2 */ 93 #define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0 94 #define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0) 95 96 /* CM_CLKSTST_IVA2 */ 97 #define OMAP3430_CLKACTIVITY_IVA2 (1 << 0) 98 99 /* CM_REVISION specific bits */ 100 101 /* CM_SYSCONFIG specific bits */ 102 103 /* CM_CLKEN_PLL_MPU */ 104 #define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8 105 #define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8) 106 #define OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4 107 #define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4) 108 #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3 109 #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3) 110 #define OMAP3430_EN_MPU_DPLL_SHIFT 0 111 #define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0) 112 113 /* CM_IDLEST_MPU */ 114 #define OMAP3430_ST_MPU (1 << 0) 115 116 /* CM_IDLEST_PLL_MPU */ 117 #define OMAP3430_ST_MPU_CLK (1 << 0) 118 #define OMAP3430_ST_IVA2_CLK_MASK (1 << 0) 119 120 /* CM_IDLEST_PLL_MPU */ 121 #define OMAP3430_ST_MPU_CLK_MASK (1 << 0) 122 123 /* CM_AUTOIDLE_PLL_MPU */ 124 #define OMAP3430_AUTO_MPU_DPLL_SHIFT 0 125 #define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0) 126 127 /* CM_CLKSEL1_PLL_MPU */ 128 #define OMAP3430_MPU_CLK_SRC_SHIFT 19 129 #define OMAP3430_MPU_CLK_SRC_MASK (0x3 << 19) 130 #define OMAP3430_MPU_DPLL_MULT_SHIFT 8 131 #define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) 132 #define OMAP3430_MPU_DPLL_DIV_SHIFT 0 133 #define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0) 134 135 /* CM_CLKSEL2_PLL_MPU */ 136 #define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0 137 #define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0) 138 139 /* CM_CLKSTCTRL_MPU */ 140 #define OMAP3430_CLKTRCTRL_MPU_SHIFT 0 141 #define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0) 142 143 /* CM_CLKSTST_MPU */ 144 #define OMAP3430_CLKACTIVITY_MPU (1 << 0) 145 146 /* CM_FCLKEN1_CORE specific bits */ 147 148 /* CM_ICLKEN1_CORE specific bits */ 149 #define OMAP3430_EN_ICR (1 << 29) 150 #define OMAP3430_EN_ICR_SHIFT 29 151 #define OMAP3430_EN_AES2 (1 << 28) 152 #define OMAP3430_EN_AES2_SHIFT 28 153 #define OMAP3430_EN_SHA12 (1 << 27) 154 #define OMAP3430_EN_SHA12_SHIFT 27 155 #define OMAP3430_EN_DES2 (1 << 26) 156 #define OMAP3430_EN_DES2_SHIFT 26 157 #define OMAP3430ES1_EN_FAC (1 << 8) 158 #define OMAP3430ES1_EN_FAC_SHIFT 8 159 #define OMAP3430_EN_MAILBOXES (1 << 7) 160 #define OMAP3430_EN_MAILBOXES_SHIFT 7 161 #define OMAP3430_EN_OMAPCTRL (1 << 6) 162 #define OMAP3430_EN_OMAPCTRL_SHIFT 6 163 #define OMAP3430_EN_SDRC (1 << 1) 164 #define OMAP3430_EN_SDRC_SHIFT 1 165 166 /* CM_ICLKEN2_CORE */ 167 #define OMAP3430_EN_PKA (1 << 4) 168 #define OMAP3430_EN_PKA_SHIFT 4 169 #define OMAP3430_EN_AES1 (1 << 3) 170 #define OMAP3430_EN_AES1_SHIFT 3 171 #define OMAP3430_EN_RNG (1 << 2) 172 #define OMAP3430_EN_RNG_SHIFT 2 173 #define OMAP3430_EN_SHA11 (1 << 1) 174 #define OMAP3430_EN_SHA11_SHIFT 1 175 #define OMAP3430_EN_DES1 (1 << 0) 176 #define OMAP3430_EN_DES1_SHIFT 0 177 178 /* CM_FCLKEN3_CORE specific bits */ 179 #define OMAP3430ES2_EN_TS_SHIFT 1 180 #define OMAP3430ES2_EN_TS_MASK (1 << 1) 181 #define OMAP3430ES2_EN_CPEFUSE_SHIFT 0 182 #define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0) 183 184 /* CM_IDLEST1_CORE specific bits */ 185 #define OMAP3430_ST_ICR (1 << 29) 186 #define OMAP3430_ST_AES2 (1 << 28) 187 #define OMAP3430_ST_SHA12 (1 << 27) 188 #define OMAP3430_ST_DES2 (1 << 26) 189 #define OMAP3430_ST_MSPRO (1 << 23) 190 #define OMAP3430_ST_HDQ (1 << 22) 191 #define OMAP3430ES1_ST_FAC (1 << 8) 192 #define OMAP3430ES1_ST_MAILBOXES (1 << 7) 193 #define OMAP3430_ST_OMAPCTRL (1 << 6) 194 #define OMAP3430_ST_SDMA (1 << 2) 195 #define OMAP3430_ST_SDRC (1 << 1) 196 #define OMAP3430_ST_SSI (1 << 0) 197 198 /* CM_IDLEST2_CORE */ 199 #define OMAP3430_ST_PKA (1 << 4) 200 #define OMAP3430_ST_AES1 (1 << 3) 201 #define OMAP3430_ST_RNG (1 << 2) 202 #define OMAP3430_ST_SHA11 (1 << 1) 203 #define OMAP3430_ST_DES1 (1 << 0) 204 205 /* CM_IDLEST3_CORE */ 206 #define OMAP3430ES2_ST_USBTLL_SHIFT 2 207 #define OMAP3430ES2_ST_USBTLL_MASK (1 << 2) 208 209 /* CM_AUTOIDLE1_CORE */ 210 #define OMAP3430_AUTO_AES2 (1 << 28) 211 #define OMAP3430_AUTO_AES2_SHIFT 28 212 #define OMAP3430_AUTO_SHA12 (1 << 27) 213 #define OMAP3430_AUTO_SHA12_SHIFT 27 214 #define OMAP3430_AUTO_DES2 (1 << 26) 215 #define OMAP3430_AUTO_DES2_SHIFT 26 216 #define OMAP3430_AUTO_MMC2 (1 << 25) 217 #define OMAP3430_AUTO_MMC2_SHIFT 25 218 #define OMAP3430_AUTO_MMC1 (1 << 24) 219 #define OMAP3430_AUTO_MMC1_SHIFT 24 220 #define OMAP3430_AUTO_MSPRO (1 << 23) 221 #define OMAP3430_AUTO_MSPRO_SHIFT 23 222 #define OMAP3430_AUTO_HDQ (1 << 22) 223 #define OMAP3430_AUTO_HDQ_SHIFT 22 224 #define OMAP3430_AUTO_MCSPI4 (1 << 21) 225 #define OMAP3430_AUTO_MCSPI4_SHIFT 21 226 #define OMAP3430_AUTO_MCSPI3 (1 << 20) 227 #define OMAP3430_AUTO_MCSPI3_SHIFT 20 228 #define OMAP3430_AUTO_MCSPI2 (1 << 19) 229 #define OMAP3430_AUTO_MCSPI2_SHIFT 19 230 #define OMAP3430_AUTO_MCSPI1 (1 << 18) 231 #define OMAP3430_AUTO_MCSPI1_SHIFT 18 232 #define OMAP3430_AUTO_I2C3 (1 << 17) 233 #define OMAP3430_AUTO_I2C3_SHIFT 17 234 #define OMAP3430_AUTO_I2C2 (1 << 16) 235 #define OMAP3430_AUTO_I2C2_SHIFT 16 236 #define OMAP3430_AUTO_I2C1 (1 << 15) 237 #define OMAP3430_AUTO_I2C1_SHIFT 15 238 #define OMAP3430_AUTO_UART2 (1 << 14) 239 #define OMAP3430_AUTO_UART2_SHIFT 14 240 #define OMAP3430_AUTO_UART1 (1 << 13) 241 #define OMAP3430_AUTO_UART1_SHIFT 13 242 #define OMAP3430_AUTO_GPT11 (1 << 12) 243 #define OMAP3430_AUTO_GPT11_SHIFT 12 244 #define OMAP3430_AUTO_GPT10 (1 << 11) 245 #define OMAP3430_AUTO_GPT10_SHIFT 11 246 #define OMAP3430_AUTO_MCBSP5 (1 << 10) 247 #define OMAP3430_AUTO_MCBSP5_SHIFT 10 248 #define OMAP3430_AUTO_MCBSP1 (1 << 9) 249 #define OMAP3430_AUTO_MCBSP1_SHIFT 9 250 #define OMAP3430ES1_AUTO_FAC (1 << 8) 251 #define OMAP3430ES1_AUTO_FAC_SHIFT 8 252 #define OMAP3430_AUTO_MAILBOXES (1 << 7) 253 #define OMAP3430_AUTO_MAILBOXES_SHIFT 7 254 #define OMAP3430_AUTO_OMAPCTRL (1 << 6) 255 #define OMAP3430_AUTO_OMAPCTRL_SHIFT 6 256 #define OMAP3430ES1_AUTO_FSHOSTUSB (1 << 5) 257 #define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5 258 #define OMAP3430_AUTO_HSOTGUSB (1 << 4) 259 #define OMAP3430_AUTO_HSOTGUSB_SHIFT 4 260 #define OMAP3430ES1_AUTO_D2D (1 << 3) 261 #define OMAP3430ES1_AUTO_D2D_SHIFT 3 262 #define OMAP3430_AUTO_SSI (1 << 0) 263 #define OMAP3430_AUTO_SSI_SHIFT 0 264 265 /* CM_AUTOIDLE2_CORE */ 266 #define OMAP3430_AUTO_PKA (1 << 4) 267 #define OMAP3430_AUTO_PKA_SHIFT 4 268 #define OMAP3430_AUTO_AES1 (1 << 3) 269 #define OMAP3430_AUTO_AES1_SHIFT 3 270 #define OMAP3430_AUTO_RNG (1 << 2) 271 #define OMAP3430_AUTO_RNG_SHIFT 2 272 #define OMAP3430_AUTO_SHA11 (1 << 1) 273 #define OMAP3430_AUTO_SHA11_SHIFT 1 274 #define OMAP3430_AUTO_DES1 (1 << 0) 275 #define OMAP3430_AUTO_DES1_SHIFT 0 276 277 /* CM_AUTOIDLE3_CORE */ 278 #define OMAP3430ES2_AUTO_USBTLL_SHIFT 2 279 #define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2) 280 281 /* CM_CLKSEL_CORE */ 282 #define OMAP3430_CLKSEL_SSI_SHIFT 8 283 #define OMAP3430_CLKSEL_SSI_MASK (0xf << 8) 284 #define OMAP3430_CLKSEL_GPT11_MASK (1 << 7) 285 #define OMAP3430_CLKSEL_GPT11_SHIFT 7 286 #define OMAP3430_CLKSEL_GPT10_MASK (1 << 6) 287 #define OMAP3430_CLKSEL_GPT10_SHIFT 6 288 #define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4 289 #define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4) 290 #define OMAP3430_CLKSEL_L4_SHIFT 2 291 #define OMAP3430_CLKSEL_L4_MASK (0x3 << 2) 292 #define OMAP3430_CLKSEL_L3_SHIFT 0 293 #define OMAP3430_CLKSEL_L3_MASK (0x3 << 0) 294 295 /* CM_CLKSTCTRL_CORE */ 296 #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4 297 #define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4) 298 #define OMAP3430_CLKTRCTRL_L4_SHIFT 2 299 #define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2) 300 #define OMAP3430_CLKTRCTRL_L3_SHIFT 0 301 #define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0) 302 303 /* CM_CLKSTST_CORE */ 304 #define OMAP3430ES1_CLKACTIVITY_D2D (1 << 2) 305 #define OMAP3430_CLKACTIVITY_L4 (1 << 1) 306 #define OMAP3430_CLKACTIVITY_L3 (1 << 0) 307 308 /* CM_FCLKEN_GFX */ 309 #define OMAP3430ES1_EN_3D (1 << 2) 310 #define OMAP3430ES1_EN_3D_SHIFT 2 311 #define OMAP3430ES1_EN_2D (1 << 1) 312 #define OMAP3430ES1_EN_2D_SHIFT 1 313 314 /* CM_ICLKEN_GFX specific bits */ 315 316 /* CM_IDLEST_GFX specific bits */ 317 318 /* CM_CLKSEL_GFX specific bits */ 319 320 /* CM_SLEEPDEP_GFX specific bits */ 321 322 /* CM_CLKSTCTRL_GFX */ 323 #define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0 324 #define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0) 325 326 /* CM_CLKSTST_GFX */ 327 #define OMAP3430ES1_CLKACTIVITY_GFX (1 << 0) 328 329 /* CM_FCLKEN_SGX */ 330 #define OMAP3430ES2_EN_SGX_SHIFT 1 331 #define OMAP3430ES2_EN_SGX_MASK (1 << 1) 332 333 /* CM_CLKSEL_SGX */ 334 #define OMAP3430ES2_CLKSEL_SGX_SHIFT 0 335 #define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0) 336 337 /* CM_FCLKEN_WKUP specific bits */ 338 #define OMAP3430ES2_EN_USIMOCP_SHIFT 9 339 340 /* CM_ICLKEN_WKUP specific bits */ 341 #define OMAP3430_EN_WDT1 (1 << 4) 342 #define OMAP3430_EN_WDT1_SHIFT 4 343 #define OMAP3430_EN_32KSYNC (1 << 2) 344 #define OMAP3430_EN_32KSYNC_SHIFT 2 345 346 /* CM_IDLEST_WKUP specific bits */ 347 #define OMAP3430_ST_WDT2 (1 << 5) 348 #define OMAP3430_ST_WDT1 (1 << 4) 349 #define OMAP3430_ST_32KSYNC (1 << 2) 350 351 /* CM_AUTOIDLE_WKUP */ 352 #define OMAP3430_AUTO_WDT2 (1 << 5) 353 #define OMAP3430_AUTO_WDT2_SHIFT 5 354 #define OMAP3430_AUTO_WDT1 (1 << 4) 355 #define OMAP3430_AUTO_WDT1_SHIFT 4 356 #define OMAP3430_AUTO_GPIO1 (1 << 3) 357 #define OMAP3430_AUTO_GPIO1_SHIFT 3 358 #define OMAP3430_AUTO_32KSYNC (1 << 2) 359 #define OMAP3430_AUTO_32KSYNC_SHIFT 2 360 #define OMAP3430_AUTO_GPT12 (1 << 1) 361 #define OMAP3430_AUTO_GPT12_SHIFT 1 362 #define OMAP3430_AUTO_GPT1 (1 << 0) 363 #define OMAP3430_AUTO_GPT1_SHIFT 0 364 365 /* CM_CLKSEL_WKUP */ 366 #define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3) 367 #define OMAP3430_CLKSEL_RM_SHIFT 1 368 #define OMAP3430_CLKSEL_RM_MASK (0x3 << 1) 369 #define OMAP3430_CLKSEL_GPT1_SHIFT 0 370 #define OMAP3430_CLKSEL_GPT1_MASK (1 << 0) 371 372 /* CM_CLKEN_PLL */ 373 #define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31 374 #define OMAP3430_PWRDN_CAM_SHIFT 30 375 #define OMAP3430_PWRDN_DSS1_SHIFT 29 376 #define OMAP3430_PWRDN_TV_SHIFT 28 377 #define OMAP3430_PWRDN_96M_SHIFT 27 378 #define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24 379 #define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24) 380 #define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20 381 #define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20) 382 #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19 383 #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19) 384 #define OMAP3430_EN_PERIPH_DPLL_SHIFT 16 385 #define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16) 386 #define OMAP3430_PWRDN_EMU_CORE_SHIFT 12 387 #define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8 388 #define OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8) 389 #define OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4 390 #define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4) 391 #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3 392 #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3) 393 #define OMAP3430_EN_CORE_DPLL_SHIFT 0 394 #define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0) 395 396 /* CM_CLKEN2_PLL */ 397 #define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10 398 #define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8) 399 #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4 400 #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4) 401 #define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3 402 #define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0 403 #define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0) 404 405 /* CM_IDLEST_CKGEN */ 406 #define OMAP3430_ST_54M_CLK (1 << 5) 407 #define OMAP3430_ST_12M_CLK (1 << 4) 408 #define OMAP3430_ST_48M_CLK (1 << 3) 409 #define OMAP3430_ST_96M_CLK (1 << 2) 410 #define OMAP3430_ST_PERIPH_CLK (1 << 1) 411 #define OMAP3430_ST_CORE_CLK (1 << 0) 412 413 /* CM_IDLEST2_CKGEN */ 414 #define OMAP3430ES2_ST_120M_CLK_SHIFT 1 415 #define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1) 416 #define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0 417 #define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0) 418 419 /* CM_AUTOIDLE_PLL */ 420 #define OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3 421 #define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3) 422 #define OMAP3430_AUTO_CORE_DPLL_SHIFT 0 423 #define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0) 424 425 /* CM_CLKSEL1_PLL */ 426 /* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */ 427 #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27 428 #define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27) 429 #define OMAP3430_CORE_DPLL_MULT_SHIFT 16 430 #define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) 431 #define OMAP3430_CORE_DPLL_DIV_SHIFT 8 432 #define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8) 433 #define OMAP3430_SOURCE_54M (1 << 5) 434 #define OMAP3430_SOURCE_48M (1 << 3) 435 436 /* CM_CLKSEL2_PLL */ 437 #define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8 438 #define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8) 439 #define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0 440 #define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0) 441 442 /* CM_CLKSEL3_PLL */ 443 #define OMAP3430_DIV_96M_SHIFT 0 444 #define OMAP3430_DIV_96M_MASK (0x1f << 0) 445 446 /* CM_CLKSEL4_PLL */ 447 #define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8 448 #define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8) 449 #define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0 450 #define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0) 451 452 /* CM_CLKSEL5_PLL */ 453 #define OMAP3430ES2_DIV_120M_SHIFT 0 454 #define OMAP3430ES2_DIV_120M_MASK (0x1f << 0) 455 456 /* CM_CLKOUT_CTRL */ 457 #define OMAP3430_CLKOUT2_EN_SHIFT 7 458 #define OMAP3430_CLKOUT2_EN (1 << 7) 459 #define OMAP3430_CLKOUT2_DIV_SHIFT 3 460 #define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3) 461 #define OMAP3430_CLKOUT2SOURCE_SHIFT 0 462 #define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0) 463 464 /* CM_FCLKEN_DSS */ 465 #define OMAP3430_EN_TV (1 << 2) 466 #define OMAP3430_EN_TV_SHIFT 2 467 #define OMAP3430_EN_DSS2 (1 << 1) 468 #define OMAP3430_EN_DSS2_SHIFT 1 469 #define OMAP3430_EN_DSS1 (1 << 0) 470 #define OMAP3430_EN_DSS1_SHIFT 0 471 472 /* CM_ICLKEN_DSS */ 473 #define OMAP3430_CM_ICLKEN_DSS_EN_DSS (1 << 0) 474 #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 475 476 /* CM_IDLEST_DSS */ 477 #define OMAP3430_ST_DSS (1 << 0) 478 479 /* CM_AUTOIDLE_DSS */ 480 #define OMAP3430_AUTO_DSS (1 << 0) 481 #define OMAP3430_AUTO_DSS_SHIFT 0 482 483 /* CM_CLKSEL_DSS */ 484 #define OMAP3430_CLKSEL_TV_SHIFT 8 485 #define OMAP3430_CLKSEL_TV_MASK (0x1f << 8) 486 #define OMAP3430_CLKSEL_DSS1_SHIFT 0 487 #define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0) 488 489 /* CM_SLEEPDEP_DSS specific bits */ 490 491 /* CM_CLKSTCTRL_DSS */ 492 #define OMAP3430_CLKTRCTRL_DSS_SHIFT 0 493 #define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0) 494 495 /* CM_CLKSTST_DSS */ 496 #define OMAP3430_CLKACTIVITY_DSS (1 << 0) 497 498 /* CM_FCLKEN_CAM specific bits */ 499 500 /* CM_ICLKEN_CAM specific bits */ 501 502 /* CM_IDLEST_CAM */ 503 #define OMAP3430_ST_CAM (1 << 0) 504 505 /* CM_AUTOIDLE_CAM */ 506 #define OMAP3430_AUTO_CAM (1 << 0) 507 #define OMAP3430_AUTO_CAM_SHIFT 0 508 509 /* CM_CLKSEL_CAM */ 510 #define OMAP3430_CLKSEL_CAM_SHIFT 0 511 #define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0) 512 513 /* CM_SLEEPDEP_CAM specific bits */ 514 515 /* CM_CLKSTCTRL_CAM */ 516 #define OMAP3430_CLKTRCTRL_CAM_SHIFT 0 517 #define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0) 518 519 /* CM_CLKSTST_CAM */ 520 #define OMAP3430_CLKACTIVITY_CAM (1 << 0) 521 522 /* CM_FCLKEN_PER specific bits */ 523 524 /* CM_ICLKEN_PER specific bits */ 525 526 /* CM_IDLEST_PER */ 527 #define OMAP3430_ST_WDT3 (1 << 12) 528 #define OMAP3430_ST_MCBSP4 (1 << 2) 529 #define OMAP3430_ST_MCBSP3 (1 << 1) 530 #define OMAP3430_ST_MCBSP2 (1 << 0) 531 532 /* CM_AUTOIDLE_PER */ 533 #define OMAP3430_AUTO_GPIO6 (1 << 17) 534 #define OMAP3430_AUTO_GPIO6_SHIFT 17 535 #define OMAP3430_AUTO_GPIO5 (1 << 16) 536 #define OMAP3430_AUTO_GPIO5_SHIFT 16 537 #define OMAP3430_AUTO_GPIO4 (1 << 15) 538 #define OMAP3430_AUTO_GPIO4_SHIFT 15 539 #define OMAP3430_AUTO_GPIO3 (1 << 14) 540 #define OMAP3430_AUTO_GPIO3_SHIFT 14 541 #define OMAP3430_AUTO_GPIO2 (1 << 13) 542 #define OMAP3430_AUTO_GPIO2_SHIFT 13 543 #define OMAP3430_AUTO_WDT3 (1 << 12) 544 #define OMAP3430_AUTO_WDT3_SHIFT 12 545 #define OMAP3430_AUTO_UART3 (1 << 11) 546 #define OMAP3430_AUTO_UART3_SHIFT 11 547 #define OMAP3430_AUTO_GPT9 (1 << 10) 548 #define OMAP3430_AUTO_GPT9_SHIFT 10 549 #define OMAP3430_AUTO_GPT8 (1 << 9) 550 #define OMAP3430_AUTO_GPT8_SHIFT 9 551 #define OMAP3430_AUTO_GPT7 (1 << 8) 552 #define OMAP3430_AUTO_GPT7_SHIFT 8 553 #define OMAP3430_AUTO_GPT6 (1 << 7) 554 #define OMAP3430_AUTO_GPT6_SHIFT 7 555 #define OMAP3430_AUTO_GPT5 (1 << 6) 556 #define OMAP3430_AUTO_GPT5_SHIFT 6 557 #define OMAP3430_AUTO_GPT4 (1 << 5) 558 #define OMAP3430_AUTO_GPT4_SHIFT 5 559 #define OMAP3430_AUTO_GPT3 (1 << 4) 560 #define OMAP3430_AUTO_GPT3_SHIFT 4 561 #define OMAP3430_AUTO_GPT2 (1 << 3) 562 #define OMAP3430_AUTO_GPT2_SHIFT 3 563 #define OMAP3430_AUTO_MCBSP4 (1 << 2) 564 #define OMAP3430_AUTO_MCBSP4_SHIFT 2 565 #define OMAP3430_AUTO_MCBSP3 (1 << 1) 566 #define OMAP3430_AUTO_MCBSP3_SHIFT 1 567 #define OMAP3430_AUTO_MCBSP2 (1 << 0) 568 #define OMAP3430_AUTO_MCBSP2_SHIFT 0 569 570 /* CM_CLKSEL_PER */ 571 #define OMAP3430_CLKSEL_GPT9_MASK (1 << 7) 572 #define OMAP3430_CLKSEL_GPT9_SHIFT 7 573 #define OMAP3430_CLKSEL_GPT8_MASK (1 << 6) 574 #define OMAP3430_CLKSEL_GPT8_SHIFT 6 575 #define OMAP3430_CLKSEL_GPT7_MASK (1 << 5) 576 #define OMAP3430_CLKSEL_GPT7_SHIFT 5 577 #define OMAP3430_CLKSEL_GPT6_MASK (1 << 4) 578 #define OMAP3430_CLKSEL_GPT6_SHIFT 4 579 #define OMAP3430_CLKSEL_GPT5_MASK (1 << 3) 580 #define OMAP3430_CLKSEL_GPT5_SHIFT 3 581 #define OMAP3430_CLKSEL_GPT4_MASK (1 << 2) 582 #define OMAP3430_CLKSEL_GPT4_SHIFT 2 583 #define OMAP3430_CLKSEL_GPT3_MASK (1 << 1) 584 #define OMAP3430_CLKSEL_GPT3_SHIFT 1 585 #define OMAP3430_CLKSEL_GPT2_MASK (1 << 0) 586 #define OMAP3430_CLKSEL_GPT2_SHIFT 0 587 588 /* CM_SLEEPDEP_PER specific bits */ 589 #define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2 (1 << 2) 590 591 /* CM_CLKSTCTRL_PER */ 592 #define OMAP3430_CLKTRCTRL_PER_SHIFT 0 593 #define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0) 594 595 /* CM_CLKSTST_PER */ 596 #define OMAP3430_CLKACTIVITY_PER (1 << 0) 597 598 /* CM_CLKSEL1_EMU */ 599 #define OMAP3430_DIV_DPLL4_SHIFT 24 600 #define OMAP3430_DIV_DPLL4_MASK (0x1f << 24) 601 #define OMAP3430_DIV_DPLL3_SHIFT 16 602 #define OMAP3430_DIV_DPLL3_MASK (0x1f << 16) 603 #define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 604 #define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11) 605 #define OMAP3430_CLKSEL_PCLK_SHIFT 8 606 #define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8) 607 #define OMAP3430_CLKSEL_PCLKX2_SHIFT 6 608 #define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6) 609 #define OMAP3430_CLKSEL_ATCLK_SHIFT 4 610 #define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4) 611 #define OMAP3430_TRACE_MUX_CTRL_SHIFT 2 612 #define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2) 613 #define OMAP3430_MUX_CTRL_SHIFT 0 614 #define OMAP3430_MUX_CTRL_MASK (0x3 << 0) 615 616 /* CM_CLKSTCTRL_EMU */ 617 #define OMAP3430_CLKTRCTRL_EMU_SHIFT 0 618 #define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0) 619 620 /* CM_CLKSTST_EMU */ 621 #define OMAP3430_CLKACTIVITY_EMU (1 << 0) 622 623 /* CM_CLKSEL2_EMU specific bits */ 624 #define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8 625 #define OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8) 626 #define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0 627 #define OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0) 628 629 /* CM_CLKSEL3_EMU specific bits */ 630 #define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8 631 #define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8) 632 #define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0 633 #define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0) 634 635 /* CM_POLCTRL */ 636 #define OMAP3430_CLKOUT2_POL (1 << 0) 637 638 /* CM_IDLEST_NEON */ 639 #define OMAP3430_ST_NEON (1 << 0) 640 641 /* CM_CLKSTCTRL_NEON */ 642 #define OMAP3430_CLKTRCTRL_NEON_SHIFT 0 643 #define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0) 644 645 /* CM_FCLKEN_USBHOST */ 646 #define OMAP3430ES2_EN_USBHOST2_SHIFT 1 647 #define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1) 648 #define OMAP3430ES2_EN_USBHOST1_SHIFT 0 649 #define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0) 650 651 /* CM_ICLKEN_USBHOST */ 652 #define OMAP3430ES2_EN_USBHOST_SHIFT 0 653 #define OMAP3430ES2_EN_USBHOST_MASK (1 << 0) 654 655 /* CM_IDLEST_USBHOST */ 656 657 /* CM_AUTOIDLE_USBHOST */ 658 #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 659 #define OMAP3430ES2_AUTO_USBHOST_MASK (1 << 0) 660 661 /* CM_SLEEPDEP_USBHOST */ 662 #define OMAP3430ES2_EN_MPU_SHIFT 1 663 #define OMAP3430ES2_EN_MPU_MASK (1 << 1) 664 #define OMAP3430ES2_EN_IVA2_SHIFT 2 665 #define OMAP3430ES2_EN_IVA2_MASK (1 << 2) 666 667 /* CM_CLKSTCTRL_USBHOST */ 668 #define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0 669 #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0) 670 671 672 673 #endif 674