1c595713dSTony Lindgren #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H 2c595713dSTony Lindgren #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H 3c595713dSTony Lindgren 4c595713dSTony Lindgren /* 5c595713dSTony Lindgren * OMAP3430 Clock Management register bits 6c595713dSTony Lindgren * 7c595713dSTony Lindgren * Copyright (C) 2007-2008 Texas Instruments, Inc. 8c595713dSTony Lindgren * Copyright (C) 2007-2008 Nokia Corporation 9c595713dSTony Lindgren * 10c595713dSTony Lindgren * Written by Paul Walmsley 11c595713dSTony Lindgren * 12c595713dSTony Lindgren * This program is free software; you can redistribute it and/or modify 13c595713dSTony Lindgren * it under the terms of the GNU General Public License version 2 as 14c595713dSTony Lindgren * published by the Free Software Foundation. 15c595713dSTony Lindgren */ 16c595713dSTony Lindgren 17c595713dSTony Lindgren #include "cm.h" 18c595713dSTony Lindgren 19c595713dSTony Lindgren /* Bits shared between registers */ 20c595713dSTony Lindgren 21c595713dSTony Lindgren /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ 22c595713dSTony Lindgren #define OMAP3430ES2_EN_MMC3_MASK (1 << 30) 23c595713dSTony Lindgren #define OMAP3430ES2_EN_MMC3_SHIFT 30 24c595713dSTony Lindgren #define OMAP3430_EN_MSPRO (1 << 23) 25c595713dSTony Lindgren #define OMAP3430_EN_MSPRO_SHIFT 23 26c595713dSTony Lindgren #define OMAP3430_EN_HDQ (1 << 22) 27c595713dSTony Lindgren #define OMAP3430_EN_HDQ_SHIFT 22 28c595713dSTony Lindgren #define OMAP3430ES1_EN_FSHOSTUSB (1 << 5) 29c595713dSTony Lindgren #define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5 30c595713dSTony Lindgren #define OMAP3430ES1_EN_D2D (1 << 3) 31c595713dSTony Lindgren #define OMAP3430ES1_EN_D2D_SHIFT 3 32c595713dSTony Lindgren #define OMAP3430_EN_SSI (1 << 0) 33c595713dSTony Lindgren #define OMAP3430_EN_SSI_SHIFT 0 34c595713dSTony Lindgren 35c595713dSTony Lindgren /* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */ 36c595713dSTony Lindgren #define OMAP3430ES2_EN_USBTLL_SHIFT 2 37c595713dSTony Lindgren #define OMAP3430ES2_EN_USBTLL_MASK (1 << 2) 38c595713dSTony Lindgren 39c595713dSTony Lindgren /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ 40c595713dSTony Lindgren #define OMAP3430_EN_WDT2 (1 << 5) 41c595713dSTony Lindgren #define OMAP3430_EN_WDT2_SHIFT 5 42c595713dSTony Lindgren 43c595713dSTony Lindgren /* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */ 44c595713dSTony Lindgren #define OMAP3430_EN_CAM (1 << 0) 45c595713dSTony Lindgren #define OMAP3430_EN_CAM_SHIFT 0 46c595713dSTony Lindgren 47c595713dSTony Lindgren /* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */ 48c595713dSTony Lindgren #define OMAP3430_EN_WDT3 (1 << 12) 49c595713dSTony Lindgren #define OMAP3430_EN_WDT3_SHIFT 12 50c595713dSTony Lindgren 51c595713dSTony Lindgren /* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */ 52c595713dSTony Lindgren #define OMAP3430_OVERRIDE_ENABLE (1 << 19) 53c595713dSTony Lindgren 54c595713dSTony Lindgren 55c595713dSTony Lindgren /* Bits specific to each register */ 56c595713dSTony Lindgren 57c595713dSTony Lindgren /* CM_FCLKEN_IVA2 */ 58dfa6d6f8SKevin Hilman #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0) 5931c203d4SHiroshi DOYU #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0 60c595713dSTony Lindgren 61c595713dSTony Lindgren /* CM_CLKEN_PLL_IVA2 */ 62c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8 63c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8) 64c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4 65c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4) 66c595713dSTony Lindgren #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3 67c595713dSTony Lindgren #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3) 68c595713dSTony Lindgren #define OMAP3430_EN_IVA2_DPLL_SHIFT 0 69c595713dSTony Lindgren #define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0) 70c595713dSTony Lindgren 71c595713dSTony Lindgren /* CM_IDLEST_IVA2 */ 72c595713dSTony Lindgren #define OMAP3430_ST_IVA2 (1 << 0) 73c595713dSTony Lindgren 74c595713dSTony Lindgren /* CM_IDLEST_PLL_IVA2 */ 75542313ccSPaul Walmsley #define OMAP3430_ST_IVA2_CLK_SHIFT 0 76542313ccSPaul Walmsley #define OMAP3430_ST_IVA2_CLK_MASK (1 << 0) 77c595713dSTony Lindgren 78c595713dSTony Lindgren /* CM_AUTOIDLE_PLL_IVA2 */ 79c595713dSTony Lindgren #define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0 80c595713dSTony Lindgren #define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0) 81c595713dSTony Lindgren 82c595713dSTony Lindgren /* CM_CLKSEL1_PLL_IVA2 */ 83c595713dSTony Lindgren #define OMAP3430_IVA2_CLK_SRC_SHIFT 19 84c595713dSTony Lindgren #define OMAP3430_IVA2_CLK_SRC_MASK (0x3 << 19) 85c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_MULT_SHIFT 8 86c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) 87c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_DIV_SHIFT 0 88c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0) 89c595713dSTony Lindgren 90c595713dSTony Lindgren /* CM_CLKSEL2_PLL_IVA2 */ 91c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0 92c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0) 93c595713dSTony Lindgren 94c595713dSTony Lindgren /* CM_CLKSTCTRL_IVA2 */ 95c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0 96c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0) 97c595713dSTony Lindgren 98c595713dSTony Lindgren /* CM_CLKSTST_IVA2 */ 99801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_IVA2_SHIFT 0 100801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0) 101c595713dSTony Lindgren 102c595713dSTony Lindgren /* CM_REVISION specific bits */ 103c595713dSTony Lindgren 104c595713dSTony Lindgren /* CM_SYSCONFIG specific bits */ 105c595713dSTony Lindgren 106c595713dSTony Lindgren /* CM_CLKEN_PLL_MPU */ 107c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8 108c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8) 109c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4 110c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4) 111c595713dSTony Lindgren #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3 112c595713dSTony Lindgren #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3) 113c595713dSTony Lindgren #define OMAP3430_EN_MPU_DPLL_SHIFT 0 114c595713dSTony Lindgren #define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0) 115c595713dSTony Lindgren 116c595713dSTony Lindgren /* CM_IDLEST_MPU */ 117c595713dSTony Lindgren #define OMAP3430_ST_MPU (1 << 0) 118c595713dSTony Lindgren 119c595713dSTony Lindgren /* CM_IDLEST_PLL_MPU */ 120542313ccSPaul Walmsley #define OMAP3430_ST_MPU_CLK_SHIFT 0 1213760d31fSRoman Tereshonkov #define OMAP3430_ST_MPU_CLK_MASK (1 << 0) 122c595713dSTony Lindgren 123c595713dSTony Lindgren /* CM_AUTOIDLE_PLL_MPU */ 124c595713dSTony Lindgren #define OMAP3430_AUTO_MPU_DPLL_SHIFT 0 125c595713dSTony Lindgren #define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0) 126c595713dSTony Lindgren 127c595713dSTony Lindgren /* CM_CLKSEL1_PLL_MPU */ 128c595713dSTony Lindgren #define OMAP3430_MPU_CLK_SRC_SHIFT 19 129c595713dSTony Lindgren #define OMAP3430_MPU_CLK_SRC_MASK (0x3 << 19) 130c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_MULT_SHIFT 8 131c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) 132c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_DIV_SHIFT 0 133c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0) 134c595713dSTony Lindgren 135c595713dSTony Lindgren /* CM_CLKSEL2_PLL_MPU */ 136c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0 137c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0) 138c595713dSTony Lindgren 139c595713dSTony Lindgren /* CM_CLKSTCTRL_MPU */ 140c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_MPU_SHIFT 0 141c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0) 142c595713dSTony Lindgren 143c595713dSTony Lindgren /* CM_CLKSTST_MPU */ 144801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_MPU_SHIFT 0 145801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0) 146c595713dSTony Lindgren 147c595713dSTony Lindgren /* CM_FCLKEN1_CORE specific bits */ 1488111b221SKevin Hilman #define OMAP3430_EN_MODEM (1 << 31) 1498111b221SKevin Hilman #define OMAP3430_EN_MODEM_SHIFT 31 150c595713dSTony Lindgren 151c595713dSTony Lindgren /* CM_ICLKEN1_CORE specific bits */ 152c595713dSTony Lindgren #define OMAP3430_EN_ICR (1 << 29) 153c595713dSTony Lindgren #define OMAP3430_EN_ICR_SHIFT 29 154c595713dSTony Lindgren #define OMAP3430_EN_AES2 (1 << 28) 155c595713dSTony Lindgren #define OMAP3430_EN_AES2_SHIFT 28 156c595713dSTony Lindgren #define OMAP3430_EN_SHA12 (1 << 27) 157c595713dSTony Lindgren #define OMAP3430_EN_SHA12_SHIFT 27 158c595713dSTony Lindgren #define OMAP3430_EN_DES2 (1 << 26) 159c595713dSTony Lindgren #define OMAP3430_EN_DES2_SHIFT 26 160c595713dSTony Lindgren #define OMAP3430ES1_EN_FAC (1 << 8) 161c595713dSTony Lindgren #define OMAP3430ES1_EN_FAC_SHIFT 8 162c595713dSTony Lindgren #define OMAP3430_EN_MAILBOXES (1 << 7) 163c595713dSTony Lindgren #define OMAP3430_EN_MAILBOXES_SHIFT 7 164c595713dSTony Lindgren #define OMAP3430_EN_OMAPCTRL (1 << 6) 165c595713dSTony Lindgren #define OMAP3430_EN_OMAPCTRL_SHIFT 6 1668111b221SKevin Hilman #define OMAP3430_EN_SAD2D (1 << 3) 1678111b221SKevin Hilman #define OMAP3430_EN_SAD2D_SHIFT 3 168c595713dSTony Lindgren #define OMAP3430_EN_SDRC (1 << 1) 169c595713dSTony Lindgren #define OMAP3430_EN_SDRC_SHIFT 1 170c595713dSTony Lindgren 171c595713dSTony Lindgren /* CM_ICLKEN2_CORE */ 172c595713dSTony Lindgren #define OMAP3430_EN_PKA (1 << 4) 173c595713dSTony Lindgren #define OMAP3430_EN_PKA_SHIFT 4 174c595713dSTony Lindgren #define OMAP3430_EN_AES1 (1 << 3) 175c595713dSTony Lindgren #define OMAP3430_EN_AES1_SHIFT 3 176c595713dSTony Lindgren #define OMAP3430_EN_RNG (1 << 2) 177c595713dSTony Lindgren #define OMAP3430_EN_RNG_SHIFT 2 178c595713dSTony Lindgren #define OMAP3430_EN_SHA11 (1 << 1) 179c595713dSTony Lindgren #define OMAP3430_EN_SHA11_SHIFT 1 180c595713dSTony Lindgren #define OMAP3430_EN_DES1 (1 << 0) 181c595713dSTony Lindgren #define OMAP3430_EN_DES1_SHIFT 0 182c595713dSTony Lindgren 1838111b221SKevin Hilman /* CM_ICLKEN3_CORE */ 1848111b221SKevin Hilman #define OMAP3430_EN_MAD2D_SHIFT 3 1858111b221SKevin Hilman #define OMAP3430_EN_MAD2D (1 << 3) 1868111b221SKevin Hilman 187c595713dSTony Lindgren /* CM_FCLKEN3_CORE specific bits */ 188c595713dSTony Lindgren #define OMAP3430ES2_EN_TS_SHIFT 1 189c595713dSTony Lindgren #define OMAP3430ES2_EN_TS_MASK (1 << 1) 190c595713dSTony Lindgren #define OMAP3430ES2_EN_CPEFUSE_SHIFT 0 191c595713dSTony Lindgren #define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0) 192c595713dSTony Lindgren 193c595713dSTony Lindgren /* CM_IDLEST1_CORE specific bits */ 194da0747d4SPaul Walmsley #define OMAP3430ES2_ST_MMC3_SHIFT 30 195da0747d4SPaul Walmsley #define OMAP3430ES2_ST_MMC3_MASK (1 << 30) 196da0747d4SPaul Walmsley #define OMAP3430_ST_ICR_SHIFT 29 197da0747d4SPaul Walmsley #define OMAP3430_ST_ICR_MASK (1 << 29) 198da0747d4SPaul Walmsley #define OMAP3430_ST_AES2_SHIFT 28 199da0747d4SPaul Walmsley #define OMAP3430_ST_AES2_MASK (1 << 28) 200da0747d4SPaul Walmsley #define OMAP3430_ST_SHA12_SHIFT 27 201da0747d4SPaul Walmsley #define OMAP3430_ST_SHA12_MASK (1 << 27) 202da0747d4SPaul Walmsley #define OMAP3430_ST_DES2_SHIFT 26 203da0747d4SPaul Walmsley #define OMAP3430_ST_DES2_MASK (1 << 26) 204da0747d4SPaul Walmsley #define OMAP3430_ST_MSPRO_SHIFT 23 205da0747d4SPaul Walmsley #define OMAP3430_ST_MSPRO_MASK (1 << 23) 206da0747d4SPaul Walmsley #define OMAP3430_ST_HDQ_SHIFT 22 207da0747d4SPaul Walmsley #define OMAP3430_ST_HDQ_MASK (1 << 22) 208da0747d4SPaul Walmsley #define OMAP3430ES1_ST_FAC_SHIFT 8 209da0747d4SPaul Walmsley #define OMAP3430ES1_ST_FAC_MASK (1 << 8) 210da0747d4SPaul Walmsley #define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8 211da0747d4SPaul Walmsley #define OMAP3430ES2_ST_SSI_IDLE_MASK (1 << 8) 212da0747d4SPaul Walmsley #define OMAP3430_ST_MAILBOXES_SHIFT 7 213da0747d4SPaul Walmsley #define OMAP3430_ST_MAILBOXES_MASK (1 << 7) 214da0747d4SPaul Walmsley #define OMAP3430_ST_OMAPCTRL_SHIFT 6 215da0747d4SPaul Walmsley #define OMAP3430_ST_OMAPCTRL_MASK (1 << 6) 216da0747d4SPaul Walmsley #define OMAP3430_ST_SDMA_SHIFT 2 217da0747d4SPaul Walmsley #define OMAP3430_ST_SDMA_MASK (1 << 2) 218da0747d4SPaul Walmsley #define OMAP3430_ST_SDRC_SHIFT 1 219da0747d4SPaul Walmsley #define OMAP3430_ST_SDRC_MASK (1 << 1) 220da0747d4SPaul Walmsley #define OMAP3430_ST_SSI_STDBY_SHIFT 0 221da0747d4SPaul Walmsley #define OMAP3430_ST_SSI_STDBY_MASK (1 << 0) 222c595713dSTony Lindgren 223c595713dSTony Lindgren /* CM_IDLEST2_CORE */ 224da0747d4SPaul Walmsley #define OMAP3430_ST_PKA_SHIFT 4 225da0747d4SPaul Walmsley #define OMAP3430_ST_PKA_MASK (1 << 4) 226da0747d4SPaul Walmsley #define OMAP3430_ST_AES1_SHIFT 3 227da0747d4SPaul Walmsley #define OMAP3430_ST_AES1_MASK (1 << 3) 228da0747d4SPaul Walmsley #define OMAP3430_ST_RNG_SHIFT 2 229da0747d4SPaul Walmsley #define OMAP3430_ST_RNG_MASK (1 << 2) 230da0747d4SPaul Walmsley #define OMAP3430_ST_SHA11_SHIFT 1 231da0747d4SPaul Walmsley #define OMAP3430_ST_SHA11_MASK (1 << 1) 232da0747d4SPaul Walmsley #define OMAP3430_ST_DES1_SHIFT 0 233da0747d4SPaul Walmsley #define OMAP3430_ST_DES1_MASK (1 << 0) 234c595713dSTony Lindgren 235c595713dSTony Lindgren /* CM_IDLEST3_CORE */ 236c595713dSTony Lindgren #define OMAP3430ES2_ST_USBTLL_SHIFT 2 237c595713dSTony Lindgren #define OMAP3430ES2_ST_USBTLL_MASK (1 << 2) 238da0747d4SPaul Walmsley #define OMAP3430ES2_ST_CPEFUSE_SHIFT 0 239da0747d4SPaul Walmsley #define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0) 240c595713dSTony Lindgren 241c595713dSTony Lindgren /* CM_AUTOIDLE1_CORE */ 2428111b221SKevin Hilman #define OMAP3430_AUTO_MODEM (1 << 31) 2438111b221SKevin Hilman #define OMAP3430_AUTO_MODEM_SHIFT 31 244027d8dedSJouni Hogander #define OMAP3430ES2_AUTO_MMC3 (1 << 30) 245027d8dedSJouni Hogander #define OMAP3430ES2_AUTO_MMC3_SHIFT 30 246027d8dedSJouni Hogander #define OMAP3430ES2_AUTO_ICR (1 << 29) 247027d8dedSJouni Hogander #define OMAP3430ES2_AUTO_ICR_SHIFT 29 248c595713dSTony Lindgren #define OMAP3430_AUTO_AES2 (1 << 28) 249c595713dSTony Lindgren #define OMAP3430_AUTO_AES2_SHIFT 28 250c595713dSTony Lindgren #define OMAP3430_AUTO_SHA12 (1 << 27) 251c595713dSTony Lindgren #define OMAP3430_AUTO_SHA12_SHIFT 27 252c595713dSTony Lindgren #define OMAP3430_AUTO_DES2 (1 << 26) 253c595713dSTony Lindgren #define OMAP3430_AUTO_DES2_SHIFT 26 254c595713dSTony Lindgren #define OMAP3430_AUTO_MMC2 (1 << 25) 255c595713dSTony Lindgren #define OMAP3430_AUTO_MMC2_SHIFT 25 256c595713dSTony Lindgren #define OMAP3430_AUTO_MMC1 (1 << 24) 257c595713dSTony Lindgren #define OMAP3430_AUTO_MMC1_SHIFT 24 258c595713dSTony Lindgren #define OMAP3430_AUTO_MSPRO (1 << 23) 259c595713dSTony Lindgren #define OMAP3430_AUTO_MSPRO_SHIFT 23 260c595713dSTony Lindgren #define OMAP3430_AUTO_HDQ (1 << 22) 261c595713dSTony Lindgren #define OMAP3430_AUTO_HDQ_SHIFT 22 262c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI4 (1 << 21) 263c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI4_SHIFT 21 264c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI3 (1 << 20) 265c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI3_SHIFT 20 266c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI2 (1 << 19) 267c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI2_SHIFT 19 268c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI1 (1 << 18) 269c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI1_SHIFT 18 270c595713dSTony Lindgren #define OMAP3430_AUTO_I2C3 (1 << 17) 271c595713dSTony Lindgren #define OMAP3430_AUTO_I2C3_SHIFT 17 272c595713dSTony Lindgren #define OMAP3430_AUTO_I2C2 (1 << 16) 273c595713dSTony Lindgren #define OMAP3430_AUTO_I2C2_SHIFT 16 274c595713dSTony Lindgren #define OMAP3430_AUTO_I2C1 (1 << 15) 275c595713dSTony Lindgren #define OMAP3430_AUTO_I2C1_SHIFT 15 276c595713dSTony Lindgren #define OMAP3430_AUTO_UART2 (1 << 14) 277c595713dSTony Lindgren #define OMAP3430_AUTO_UART2_SHIFT 14 278c595713dSTony Lindgren #define OMAP3430_AUTO_UART1 (1 << 13) 279c595713dSTony Lindgren #define OMAP3430_AUTO_UART1_SHIFT 13 280c595713dSTony Lindgren #define OMAP3430_AUTO_GPT11 (1 << 12) 281c595713dSTony Lindgren #define OMAP3430_AUTO_GPT11_SHIFT 12 282c595713dSTony Lindgren #define OMAP3430_AUTO_GPT10 (1 << 11) 283c595713dSTony Lindgren #define OMAP3430_AUTO_GPT10_SHIFT 11 284c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP5 (1 << 10) 285c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP5_SHIFT 10 286c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP1 (1 << 9) 287c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP1_SHIFT 9 288c595713dSTony Lindgren #define OMAP3430ES1_AUTO_FAC (1 << 8) 289c595713dSTony Lindgren #define OMAP3430ES1_AUTO_FAC_SHIFT 8 290c595713dSTony Lindgren #define OMAP3430_AUTO_MAILBOXES (1 << 7) 291c595713dSTony Lindgren #define OMAP3430_AUTO_MAILBOXES_SHIFT 7 292c595713dSTony Lindgren #define OMAP3430_AUTO_OMAPCTRL (1 << 6) 293c595713dSTony Lindgren #define OMAP3430_AUTO_OMAPCTRL_SHIFT 6 294c595713dSTony Lindgren #define OMAP3430ES1_AUTO_FSHOSTUSB (1 << 5) 295c595713dSTony Lindgren #define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5 296c595713dSTony Lindgren #define OMAP3430_AUTO_HSOTGUSB (1 << 4) 297c595713dSTony Lindgren #define OMAP3430_AUTO_HSOTGUSB_SHIFT 4 298c595713dSTony Lindgren #define OMAP3430ES1_AUTO_D2D (1 << 3) 299c595713dSTony Lindgren #define OMAP3430ES1_AUTO_D2D_SHIFT 3 3008111b221SKevin Hilman #define OMAP3430_AUTO_SAD2D (1 << 3) 3018111b221SKevin Hilman #define OMAP3430_AUTO_SAD2D_SHIFT 3 302c595713dSTony Lindgren #define OMAP3430_AUTO_SSI (1 << 0) 303c595713dSTony Lindgren #define OMAP3430_AUTO_SSI_SHIFT 0 304c595713dSTony Lindgren 305c595713dSTony Lindgren /* CM_AUTOIDLE2_CORE */ 306c595713dSTony Lindgren #define OMAP3430_AUTO_PKA (1 << 4) 307c595713dSTony Lindgren #define OMAP3430_AUTO_PKA_SHIFT 4 308c595713dSTony Lindgren #define OMAP3430_AUTO_AES1 (1 << 3) 309c595713dSTony Lindgren #define OMAP3430_AUTO_AES1_SHIFT 3 310c595713dSTony Lindgren #define OMAP3430_AUTO_RNG (1 << 2) 311c595713dSTony Lindgren #define OMAP3430_AUTO_RNG_SHIFT 2 312c595713dSTony Lindgren #define OMAP3430_AUTO_SHA11 (1 << 1) 313c595713dSTony Lindgren #define OMAP3430_AUTO_SHA11_SHIFT 1 314c595713dSTony Lindgren #define OMAP3430_AUTO_DES1 (1 << 0) 315c595713dSTony Lindgren #define OMAP3430_AUTO_DES1_SHIFT 0 316c595713dSTony Lindgren 317c595713dSTony Lindgren /* CM_AUTOIDLE3_CORE */ 318027d8dedSJouni Hogander #define OMAP3430ES2_AUTO_USBHOST (1 << 0) 319027d8dedSJouni Hogander #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 320027d8dedSJouni Hogander #define OMAP3430ES2_AUTO_USBTLL (1 << 2) 321c595713dSTony Lindgren #define OMAP3430ES2_AUTO_USBTLL_SHIFT 2 322c595713dSTony Lindgren #define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2) 3238111b221SKevin Hilman #define OMAP3430_AUTO_MAD2D_SHIFT 3 3248111b221SKevin Hilman #define OMAP3430_AUTO_MAD2D (1 << 3) 325c595713dSTony Lindgren 326c595713dSTony Lindgren /* CM_CLKSEL_CORE */ 327c595713dSTony Lindgren #define OMAP3430_CLKSEL_SSI_SHIFT 8 328c595713dSTony Lindgren #define OMAP3430_CLKSEL_SSI_MASK (0xf << 8) 329c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT11_MASK (1 << 7) 330c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT11_SHIFT 7 331c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT10_MASK (1 << 6) 332c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT10_SHIFT 6 333c595713dSTony Lindgren #define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4 334c595713dSTony Lindgren #define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4) 335c595713dSTony Lindgren #define OMAP3430_CLKSEL_L4_SHIFT 2 336c595713dSTony Lindgren #define OMAP3430_CLKSEL_L4_MASK (0x3 << 2) 337c595713dSTony Lindgren #define OMAP3430_CLKSEL_L3_SHIFT 0 338c595713dSTony Lindgren #define OMAP3430_CLKSEL_L3_MASK (0x3 << 0) 339c595713dSTony Lindgren 340c595713dSTony Lindgren /* CM_CLKSTCTRL_CORE */ 341c595713dSTony Lindgren #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4 342c595713dSTony Lindgren #define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4) 343c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_L4_SHIFT 2 344c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2) 345c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_L3_SHIFT 0 346c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0) 347c595713dSTony Lindgren 348c595713dSTony Lindgren /* CM_CLKSTST_CORE */ 349801954d3SPaul Walmsley #define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT 2 350801954d3SPaul Walmsley #define OMAP3430ES1_CLKACTIVITY_D2D_MASK (1 << 2) 351801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_L4_SHIFT 1 352801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_L4_MASK (1 << 1) 353801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_L3_SHIFT 0 354801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0) 355c595713dSTony Lindgren 356c595713dSTony Lindgren /* CM_FCLKEN_GFX */ 357c595713dSTony Lindgren #define OMAP3430ES1_EN_3D (1 << 2) 358c595713dSTony Lindgren #define OMAP3430ES1_EN_3D_SHIFT 2 359c595713dSTony Lindgren #define OMAP3430ES1_EN_2D (1 << 1) 360c595713dSTony Lindgren #define OMAP3430ES1_EN_2D_SHIFT 1 361c595713dSTony Lindgren 362c595713dSTony Lindgren /* CM_ICLKEN_GFX specific bits */ 363c595713dSTony Lindgren 364c595713dSTony Lindgren /* CM_IDLEST_GFX specific bits */ 365c595713dSTony Lindgren 366c595713dSTony Lindgren /* CM_CLKSEL_GFX specific bits */ 367c595713dSTony Lindgren 368c595713dSTony Lindgren /* CM_SLEEPDEP_GFX specific bits */ 369c595713dSTony Lindgren 370c595713dSTony Lindgren /* CM_CLKSTCTRL_GFX */ 371c595713dSTony Lindgren #define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0 372c595713dSTony Lindgren #define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0) 373c595713dSTony Lindgren 374c595713dSTony Lindgren /* CM_CLKSTST_GFX */ 375801954d3SPaul Walmsley #define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT 0 376801954d3SPaul Walmsley #define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0) 377c595713dSTony Lindgren 378c595713dSTony Lindgren /* CM_FCLKEN_SGX */ 379712d7c86SDaniel Stone #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1 380712d7c86SDaniel Stone #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1) 381712d7c86SDaniel Stone 382712d7c86SDaniel Stone /* CM_ICLKEN_SGX */ 383712d7c86SDaniel Stone #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0 384712d7c86SDaniel Stone #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0) 385c595713dSTony Lindgren 386c595713dSTony Lindgren /* CM_CLKSEL_SGX */ 387c595713dSTony Lindgren #define OMAP3430ES2_CLKSEL_SGX_SHIFT 0 388c595713dSTony Lindgren #define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0) 389c595713dSTony Lindgren 390801954d3SPaul Walmsley /* CM_CLKSTCTRL_SGX */ 391801954d3SPaul Walmsley #define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT 0 392801954d3SPaul Walmsley #define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0) 393801954d3SPaul Walmsley 394801954d3SPaul Walmsley /* CM_CLKSTST_SGX */ 395801954d3SPaul Walmsley #define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT 0 396801954d3SPaul Walmsley #define OMAP3430ES2_CLKACTIVITY_SGX_MASK (1 << 0) 397801954d3SPaul Walmsley 398c595713dSTony Lindgren /* CM_FCLKEN_WKUP specific bits */ 399c595713dSTony Lindgren #define OMAP3430ES2_EN_USIMOCP_SHIFT 9 400da0747d4SPaul Walmsley #define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9) 401c595713dSTony Lindgren 402c595713dSTony Lindgren /* CM_ICLKEN_WKUP specific bits */ 403c595713dSTony Lindgren #define OMAP3430_EN_WDT1 (1 << 4) 404c595713dSTony Lindgren #define OMAP3430_EN_WDT1_SHIFT 4 405c595713dSTony Lindgren #define OMAP3430_EN_32KSYNC (1 << 2) 406c595713dSTony Lindgren #define OMAP3430_EN_32KSYNC_SHIFT 2 407c595713dSTony Lindgren 408c595713dSTony Lindgren /* CM_IDLEST_WKUP specific bits */ 409da0747d4SPaul Walmsley #define OMAP3430ES2_ST_USIMOCP_SHIFT 9 410da0747d4SPaul Walmsley #define OMAP3430ES2_ST_USIMOCP_MASK (1 << 9) 411da0747d4SPaul Walmsley #define OMAP3430_ST_WDT2_SHIFT 5 412da0747d4SPaul Walmsley #define OMAP3430_ST_WDT2_MASK (1 << 5) 413da0747d4SPaul Walmsley #define OMAP3430_ST_WDT1_SHIFT 4 414da0747d4SPaul Walmsley #define OMAP3430_ST_WDT1_MASK (1 << 4) 415da0747d4SPaul Walmsley #define OMAP3430_ST_32KSYNC_SHIFT 2 416da0747d4SPaul Walmsley #define OMAP3430_ST_32KSYNC_MASK (1 << 2) 417c595713dSTony Lindgren 418c595713dSTony Lindgren /* CM_AUTOIDLE_WKUP */ 419da0747d4SPaul Walmsley #define OMAP3430ES2_AUTO_USIMOCP (1 << 9) 420da0747d4SPaul Walmsley #define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9 421c595713dSTony Lindgren #define OMAP3430_AUTO_WDT2 (1 << 5) 422c595713dSTony Lindgren #define OMAP3430_AUTO_WDT2_SHIFT 5 423c595713dSTony Lindgren #define OMAP3430_AUTO_WDT1 (1 << 4) 424c595713dSTony Lindgren #define OMAP3430_AUTO_WDT1_SHIFT 4 425c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO1 (1 << 3) 426c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO1_SHIFT 3 427c595713dSTony Lindgren #define OMAP3430_AUTO_32KSYNC (1 << 2) 428c595713dSTony Lindgren #define OMAP3430_AUTO_32KSYNC_SHIFT 2 429c595713dSTony Lindgren #define OMAP3430_AUTO_GPT12 (1 << 1) 430c595713dSTony Lindgren #define OMAP3430_AUTO_GPT12_SHIFT 1 431c595713dSTony Lindgren #define OMAP3430_AUTO_GPT1 (1 << 0) 432c595713dSTony Lindgren #define OMAP3430_AUTO_GPT1_SHIFT 0 433c595713dSTony Lindgren 434c595713dSTony Lindgren /* CM_CLKSEL_WKUP */ 435c595713dSTony Lindgren #define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3) 436c595713dSTony Lindgren #define OMAP3430_CLKSEL_RM_SHIFT 1 437c595713dSTony Lindgren #define OMAP3430_CLKSEL_RM_MASK (0x3 << 1) 438c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT1_SHIFT 0 439c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT1_MASK (1 << 0) 440c595713dSTony Lindgren 441c595713dSTony Lindgren /* CM_CLKEN_PLL */ 442c595713dSTony Lindgren #define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31 443c595713dSTony Lindgren #define OMAP3430_PWRDN_CAM_SHIFT 30 444c595713dSTony Lindgren #define OMAP3430_PWRDN_DSS1_SHIFT 29 445c595713dSTony Lindgren #define OMAP3430_PWRDN_TV_SHIFT 28 446c595713dSTony Lindgren #define OMAP3430_PWRDN_96M_SHIFT 27 447c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24 448c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24) 449c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20 450c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20) 451c595713dSTony Lindgren #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19 452c595713dSTony Lindgren #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19) 453c595713dSTony Lindgren #define OMAP3430_EN_PERIPH_DPLL_SHIFT 16 454c595713dSTony Lindgren #define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16) 455c595713dSTony Lindgren #define OMAP3430_PWRDN_EMU_CORE_SHIFT 12 456c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8 457c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8) 458c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4 459c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4) 460c595713dSTony Lindgren #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3 461c595713dSTony Lindgren #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3) 462c595713dSTony Lindgren #define OMAP3430_EN_CORE_DPLL_SHIFT 0 463c595713dSTony Lindgren #define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0) 464c595713dSTony Lindgren 465c595713dSTony Lindgren /* CM_CLKEN2_PLL */ 466c595713dSTony Lindgren #define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10 467c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8) 468c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4 469c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4) 470c595713dSTony Lindgren #define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3 471c595713dSTony Lindgren #define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0 472c595713dSTony Lindgren #define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0) 473c595713dSTony Lindgren 474c595713dSTony Lindgren /* CM_IDLEST_CKGEN */ 475c595713dSTony Lindgren #define OMAP3430_ST_54M_CLK (1 << 5) 476c595713dSTony Lindgren #define OMAP3430_ST_12M_CLK (1 << 4) 477c595713dSTony Lindgren #define OMAP3430_ST_48M_CLK (1 << 3) 478c595713dSTony Lindgren #define OMAP3430_ST_96M_CLK (1 << 2) 479542313ccSPaul Walmsley #define OMAP3430_ST_PERIPH_CLK_SHIFT 1 480542313ccSPaul Walmsley #define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1) 481542313ccSPaul Walmsley #define OMAP3430_ST_CORE_CLK_SHIFT 0 482542313ccSPaul Walmsley #define OMAP3430_ST_CORE_CLK_MASK (1 << 0) 483c595713dSTony Lindgren 484c595713dSTony Lindgren /* CM_IDLEST2_CKGEN */ 485da0747d4SPaul Walmsley #define OMAP3430ES2_ST_USIM_CLK_SHIFT 2 486da0747d4SPaul Walmsley #define OMAP3430ES2_ST_USIM_CLK_MASK (1 << 2) 487c595713dSTony Lindgren #define OMAP3430ES2_ST_120M_CLK_SHIFT 1 488c595713dSTony Lindgren #define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1) 489c595713dSTony Lindgren #define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0 490c595713dSTony Lindgren #define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0) 491c595713dSTony Lindgren 492c595713dSTony Lindgren /* CM_AUTOIDLE_PLL */ 493c595713dSTony Lindgren #define OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3 494c595713dSTony Lindgren #define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3) 495c595713dSTony Lindgren #define OMAP3430_AUTO_CORE_DPLL_SHIFT 0 496c595713dSTony Lindgren #define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0) 497c595713dSTony Lindgren 498542313ccSPaul Walmsley /* CM_AUTOIDLE2_PLL */ 499542313ccSPaul Walmsley #define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT 0 500542313ccSPaul Walmsley #define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0) 501542313ccSPaul Walmsley 502c595713dSTony Lindgren /* CM_CLKSEL1_PLL */ 503c595713dSTony Lindgren /* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */ 504c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27 505c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27) 506c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_MULT_SHIFT 16 507c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) 508c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_DIV_SHIFT 8 509c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8) 5109cfd985eSPaul Walmsley #define OMAP3430_SOURCE_96M_SHIFT 6 5119cfd985eSPaul Walmsley #define OMAP3430_SOURCE_96M_MASK (1 << 6) 5129cfd985eSPaul Walmsley #define OMAP3430_SOURCE_54M_SHIFT 5 5139cfd985eSPaul Walmsley #define OMAP3430_SOURCE_54M_MASK (1 << 5) 5149cfd985eSPaul Walmsley #define OMAP3430_SOURCE_48M_SHIFT 3 5159cfd985eSPaul Walmsley #define OMAP3430_SOURCE_48M_MASK (1 << 3) 516c595713dSTony Lindgren 517c595713dSTony Lindgren /* CM_CLKSEL2_PLL */ 518c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8 519c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8) 520c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0 521c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0) 522c595713dSTony Lindgren 523c595713dSTony Lindgren /* CM_CLKSEL3_PLL */ 524c595713dSTony Lindgren #define OMAP3430_DIV_96M_SHIFT 0 525c595713dSTony Lindgren #define OMAP3430_DIV_96M_MASK (0x1f << 0) 526c595713dSTony Lindgren 527c595713dSTony Lindgren /* CM_CLKSEL4_PLL */ 528c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8 529c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8) 530c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0 531c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0) 532c595713dSTony Lindgren 533c595713dSTony Lindgren /* CM_CLKSEL5_PLL */ 534c595713dSTony Lindgren #define OMAP3430ES2_DIV_120M_SHIFT 0 535c595713dSTony Lindgren #define OMAP3430ES2_DIV_120M_MASK (0x1f << 0) 536c595713dSTony Lindgren 537c595713dSTony Lindgren /* CM_CLKOUT_CTRL */ 538c595713dSTony Lindgren #define OMAP3430_CLKOUT2_EN_SHIFT 7 539c595713dSTony Lindgren #define OMAP3430_CLKOUT2_EN (1 << 7) 540c595713dSTony Lindgren #define OMAP3430_CLKOUT2_DIV_SHIFT 3 541c595713dSTony Lindgren #define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3) 542c595713dSTony Lindgren #define OMAP3430_CLKOUT2SOURCE_SHIFT 0 543c595713dSTony Lindgren #define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0) 544c595713dSTony Lindgren 545c595713dSTony Lindgren /* CM_FCLKEN_DSS */ 546c595713dSTony Lindgren #define OMAP3430_EN_TV (1 << 2) 547c595713dSTony Lindgren #define OMAP3430_EN_TV_SHIFT 2 548c595713dSTony Lindgren #define OMAP3430_EN_DSS2 (1 << 1) 549c595713dSTony Lindgren #define OMAP3430_EN_DSS2_SHIFT 1 550c595713dSTony Lindgren #define OMAP3430_EN_DSS1 (1 << 0) 551c595713dSTony Lindgren #define OMAP3430_EN_DSS1_SHIFT 0 552c595713dSTony Lindgren 553c595713dSTony Lindgren /* CM_ICLKEN_DSS */ 554c595713dSTony Lindgren #define OMAP3430_CM_ICLKEN_DSS_EN_DSS (1 << 0) 555c595713dSTony Lindgren #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 556c595713dSTony Lindgren 557c595713dSTony Lindgren /* CM_IDLEST_DSS */ 558da0747d4SPaul Walmsley #define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1 559da0747d4SPaul Walmsley #define OMAP3430ES2_ST_DSS_IDLE_MASK (1 << 1) 560da0747d4SPaul Walmsley #define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0 561da0747d4SPaul Walmsley #define OMAP3430ES2_ST_DSS_STDBY_MASK (1 << 0) 562da0747d4SPaul Walmsley #define OMAP3430ES1_ST_DSS_SHIFT 0 563da0747d4SPaul Walmsley #define OMAP3430ES1_ST_DSS_MASK (1 << 0) 564c595713dSTony Lindgren 565c595713dSTony Lindgren /* CM_AUTOIDLE_DSS */ 566c595713dSTony Lindgren #define OMAP3430_AUTO_DSS (1 << 0) 567c595713dSTony Lindgren #define OMAP3430_AUTO_DSS_SHIFT 0 568c595713dSTony Lindgren 569c595713dSTony Lindgren /* CM_CLKSEL_DSS */ 570c595713dSTony Lindgren #define OMAP3430_CLKSEL_TV_SHIFT 8 571c595713dSTony Lindgren #define OMAP3430_CLKSEL_TV_MASK (0x1f << 8) 572c595713dSTony Lindgren #define OMAP3430_CLKSEL_DSS1_SHIFT 0 573c595713dSTony Lindgren #define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0) 574c595713dSTony Lindgren 575c595713dSTony Lindgren /* CM_SLEEPDEP_DSS specific bits */ 576c595713dSTony Lindgren 577c595713dSTony Lindgren /* CM_CLKSTCTRL_DSS */ 578c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_DSS_SHIFT 0 579c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0) 580c595713dSTony Lindgren 581c595713dSTony Lindgren /* CM_CLKSTST_DSS */ 582801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_DSS_SHIFT 0 583801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0) 584c595713dSTony Lindgren 585c595713dSTony Lindgren /* CM_FCLKEN_CAM specific bits */ 5866c8fe0b9SSergio Aguirre #define OMAP3430_EN_CSI2 (1 << 1) 5876c8fe0b9SSergio Aguirre #define OMAP3430_EN_CSI2_SHIFT 1 588c595713dSTony Lindgren 589c595713dSTony Lindgren /* CM_ICLKEN_CAM specific bits */ 590c595713dSTony Lindgren 591c595713dSTony Lindgren /* CM_IDLEST_CAM */ 592c595713dSTony Lindgren #define OMAP3430_ST_CAM (1 << 0) 593c595713dSTony Lindgren 594c595713dSTony Lindgren /* CM_AUTOIDLE_CAM */ 595c595713dSTony Lindgren #define OMAP3430_AUTO_CAM (1 << 0) 596c595713dSTony Lindgren #define OMAP3430_AUTO_CAM_SHIFT 0 597c595713dSTony Lindgren 598c595713dSTony Lindgren /* CM_CLKSEL_CAM */ 599c595713dSTony Lindgren #define OMAP3430_CLKSEL_CAM_SHIFT 0 600c595713dSTony Lindgren #define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0) 601c595713dSTony Lindgren 602c595713dSTony Lindgren /* CM_SLEEPDEP_CAM specific bits */ 603c595713dSTony Lindgren 604c595713dSTony Lindgren /* CM_CLKSTCTRL_CAM */ 605c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_CAM_SHIFT 0 606c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0) 607c595713dSTony Lindgren 608c595713dSTony Lindgren /* CM_CLKSTST_CAM */ 609801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_CAM_SHIFT 0 610801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_CAM_MASK (1 << 0) 611c595713dSTony Lindgren 612c595713dSTony Lindgren /* CM_FCLKEN_PER specific bits */ 613c595713dSTony Lindgren 614c595713dSTony Lindgren /* CM_ICLKEN_PER specific bits */ 615c595713dSTony Lindgren 616c595713dSTony Lindgren /* CM_IDLEST_PER */ 617da0747d4SPaul Walmsley #define OMAP3430_ST_WDT3_SHIFT 12 618da0747d4SPaul Walmsley #define OMAP3430_ST_WDT3_MASK (1 << 12) 619da0747d4SPaul Walmsley #define OMAP3430_ST_MCBSP4_SHIFT 2 620da0747d4SPaul Walmsley #define OMAP3430_ST_MCBSP4_MASK (1 << 2) 621da0747d4SPaul Walmsley #define OMAP3430_ST_MCBSP3_SHIFT 1 622da0747d4SPaul Walmsley #define OMAP3430_ST_MCBSP3_MASK (1 << 1) 623da0747d4SPaul Walmsley #define OMAP3430_ST_MCBSP2_SHIFT 0 624da0747d4SPaul Walmsley #define OMAP3430_ST_MCBSP2_MASK (1 << 0) 625c595713dSTony Lindgren 626c595713dSTony Lindgren /* CM_AUTOIDLE_PER */ 627c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO6 (1 << 17) 628c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO6_SHIFT 17 629c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO5 (1 << 16) 630c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO5_SHIFT 16 631c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO4 (1 << 15) 632c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO4_SHIFT 15 633c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO3 (1 << 14) 634c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO3_SHIFT 14 635c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO2 (1 << 13) 636c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO2_SHIFT 13 637c595713dSTony Lindgren #define OMAP3430_AUTO_WDT3 (1 << 12) 638c595713dSTony Lindgren #define OMAP3430_AUTO_WDT3_SHIFT 12 639c595713dSTony Lindgren #define OMAP3430_AUTO_UART3 (1 << 11) 640c595713dSTony Lindgren #define OMAP3430_AUTO_UART3_SHIFT 11 641c595713dSTony Lindgren #define OMAP3430_AUTO_GPT9 (1 << 10) 642c595713dSTony Lindgren #define OMAP3430_AUTO_GPT9_SHIFT 10 643c595713dSTony Lindgren #define OMAP3430_AUTO_GPT8 (1 << 9) 644c595713dSTony Lindgren #define OMAP3430_AUTO_GPT8_SHIFT 9 645c595713dSTony Lindgren #define OMAP3430_AUTO_GPT7 (1 << 8) 646c595713dSTony Lindgren #define OMAP3430_AUTO_GPT7_SHIFT 8 647c595713dSTony Lindgren #define OMAP3430_AUTO_GPT6 (1 << 7) 648c595713dSTony Lindgren #define OMAP3430_AUTO_GPT6_SHIFT 7 649c595713dSTony Lindgren #define OMAP3430_AUTO_GPT5 (1 << 6) 650c595713dSTony Lindgren #define OMAP3430_AUTO_GPT5_SHIFT 6 651c595713dSTony Lindgren #define OMAP3430_AUTO_GPT4 (1 << 5) 652c595713dSTony Lindgren #define OMAP3430_AUTO_GPT4_SHIFT 5 653c595713dSTony Lindgren #define OMAP3430_AUTO_GPT3 (1 << 4) 654c595713dSTony Lindgren #define OMAP3430_AUTO_GPT3_SHIFT 4 655c595713dSTony Lindgren #define OMAP3430_AUTO_GPT2 (1 << 3) 656c595713dSTony Lindgren #define OMAP3430_AUTO_GPT2_SHIFT 3 657c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP4 (1 << 2) 658c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP4_SHIFT 2 659c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP3 (1 << 1) 660c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP3_SHIFT 1 661c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP2 (1 << 0) 662c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP2_SHIFT 0 663c595713dSTony Lindgren 664c595713dSTony Lindgren /* CM_CLKSEL_PER */ 665c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT9_MASK (1 << 7) 666c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT9_SHIFT 7 667c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT8_MASK (1 << 6) 668c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT8_SHIFT 6 669c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT7_MASK (1 << 5) 670c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT7_SHIFT 5 671c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT6_MASK (1 << 4) 672c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT6_SHIFT 4 673c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT5_MASK (1 << 3) 674c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT5_SHIFT 3 675c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT4_MASK (1 << 2) 676c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT4_SHIFT 2 677c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT3_MASK (1 << 1) 678c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT3_SHIFT 1 679c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT2_MASK (1 << 0) 680c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT2_SHIFT 0 681c595713dSTony Lindgren 682c595713dSTony Lindgren /* CM_SLEEPDEP_PER specific bits */ 683c595713dSTony Lindgren #define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2 (1 << 2) 684c595713dSTony Lindgren 685c595713dSTony Lindgren /* CM_CLKSTCTRL_PER */ 686c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_PER_SHIFT 0 687c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0) 688c595713dSTony Lindgren 689c595713dSTony Lindgren /* CM_CLKSTST_PER */ 690801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_PER_SHIFT 0 691801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_PER_MASK (1 << 0) 692c595713dSTony Lindgren 693c595713dSTony Lindgren /* CM_CLKSEL1_EMU */ 694c595713dSTony Lindgren #define OMAP3430_DIV_DPLL4_SHIFT 24 695c595713dSTony Lindgren #define OMAP3430_DIV_DPLL4_MASK (0x1f << 24) 696c595713dSTony Lindgren #define OMAP3430_DIV_DPLL3_SHIFT 16 697c595713dSTony Lindgren #define OMAP3430_DIV_DPLL3_MASK (0x1f << 16) 698c595713dSTony Lindgren #define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 699c595713dSTony Lindgren #define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11) 700c595713dSTony Lindgren #define OMAP3430_CLKSEL_PCLK_SHIFT 8 701c595713dSTony Lindgren #define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8) 702c595713dSTony Lindgren #define OMAP3430_CLKSEL_PCLKX2_SHIFT 6 703c595713dSTony Lindgren #define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6) 704c595713dSTony Lindgren #define OMAP3430_CLKSEL_ATCLK_SHIFT 4 705c595713dSTony Lindgren #define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4) 706c595713dSTony Lindgren #define OMAP3430_TRACE_MUX_CTRL_SHIFT 2 707c595713dSTony Lindgren #define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2) 708c595713dSTony Lindgren #define OMAP3430_MUX_CTRL_SHIFT 0 709c595713dSTony Lindgren #define OMAP3430_MUX_CTRL_MASK (0x3 << 0) 710c595713dSTony Lindgren 711c595713dSTony Lindgren /* CM_CLKSTCTRL_EMU */ 712c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_EMU_SHIFT 0 713c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0) 714c595713dSTony Lindgren 715c595713dSTony Lindgren /* CM_CLKSTST_EMU */ 716801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_EMU_SHIFT 0 717801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_EMU_MASK (1 << 0) 718c595713dSTony Lindgren 719c595713dSTony Lindgren /* CM_CLKSEL2_EMU specific bits */ 720c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8 721c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8) 722c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0 723c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0) 724c595713dSTony Lindgren 725c595713dSTony Lindgren /* CM_CLKSEL3_EMU specific bits */ 726c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8 727c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8) 728c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0 729c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0) 730c595713dSTony Lindgren 731c595713dSTony Lindgren /* CM_POLCTRL */ 732c595713dSTony Lindgren #define OMAP3430_CLKOUT2_POL (1 << 0) 733c595713dSTony Lindgren 734c595713dSTony Lindgren /* CM_IDLEST_NEON */ 735c595713dSTony Lindgren #define OMAP3430_ST_NEON (1 << 0) 736c595713dSTony Lindgren 737c595713dSTony Lindgren /* CM_CLKSTCTRL_NEON */ 738c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_NEON_SHIFT 0 739c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0) 740c595713dSTony Lindgren 741c595713dSTony Lindgren /* CM_FCLKEN_USBHOST */ 742c595713dSTony Lindgren #define OMAP3430ES2_EN_USBHOST2_SHIFT 1 743c595713dSTony Lindgren #define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1) 744c595713dSTony Lindgren #define OMAP3430ES2_EN_USBHOST1_SHIFT 0 745c595713dSTony Lindgren #define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0) 746c595713dSTony Lindgren 747c595713dSTony Lindgren /* CM_ICLKEN_USBHOST */ 748c595713dSTony Lindgren #define OMAP3430ES2_EN_USBHOST_SHIFT 0 749c595713dSTony Lindgren #define OMAP3430ES2_EN_USBHOST_MASK (1 << 0) 750c595713dSTony Lindgren 751c595713dSTony Lindgren /* CM_IDLEST_USBHOST */ 752da0747d4SPaul Walmsley #define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1 753da0747d4SPaul Walmsley #define OMAP3430ES2_ST_USBHOST_IDLE_MASK (1 << 1) 754da0747d4SPaul Walmsley #define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0 755da0747d4SPaul Walmsley #define OMAP3430ES2_ST_USBHOST_STDBY_MASK (1 << 0) 756c595713dSTony Lindgren 757c595713dSTony Lindgren /* CM_AUTOIDLE_USBHOST */ 758c595713dSTony Lindgren #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 759c595713dSTony Lindgren #define OMAP3430ES2_AUTO_USBHOST_MASK (1 << 0) 760c595713dSTony Lindgren 761c595713dSTony Lindgren /* CM_SLEEPDEP_USBHOST */ 762c595713dSTony Lindgren #define OMAP3430ES2_EN_MPU_SHIFT 1 763c595713dSTony Lindgren #define OMAP3430ES2_EN_MPU_MASK (1 << 1) 764c595713dSTony Lindgren #define OMAP3430ES2_EN_IVA2_SHIFT 2 765c595713dSTony Lindgren #define OMAP3430ES2_EN_IVA2_MASK (1 << 2) 766c595713dSTony Lindgren 767c595713dSTony Lindgren /* CM_CLKSTCTRL_USBHOST */ 768c595713dSTony Lindgren #define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0 769c595713dSTony Lindgren #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0) 770c595713dSTony Lindgren 771801954d3SPaul Walmsley /* CM_CLKSTST_USBHOST */ 772801954d3SPaul Walmsley #define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0 773801954d3SPaul Walmsley #define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0) 774c595713dSTony Lindgren 775c595713dSTony Lindgren #endif 776