1c595713dSTony Lindgren #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H 2c595713dSTony Lindgren #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H 3c595713dSTony Lindgren 4c595713dSTony Lindgren /* 5c595713dSTony Lindgren * OMAP3430 Clock Management register bits 6c595713dSTony Lindgren * 7c595713dSTony Lindgren * Copyright (C) 2007-2008 Texas Instruments, Inc. 8c595713dSTony Lindgren * Copyright (C) 2007-2008 Nokia Corporation 9c595713dSTony Lindgren * 10c595713dSTony Lindgren * Written by Paul Walmsley 11c595713dSTony Lindgren * 12c595713dSTony Lindgren * This program is free software; you can redistribute it and/or modify 13c595713dSTony Lindgren * it under the terms of the GNU General Public License version 2 as 14c595713dSTony Lindgren * published by the Free Software Foundation. 15c595713dSTony Lindgren */ 16c595713dSTony Lindgren 17c595713dSTony Lindgren #include "cm.h" 18c595713dSTony Lindgren 19c595713dSTony Lindgren /* Bits shared between registers */ 20c595713dSTony Lindgren 21c595713dSTony Lindgren /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ 22c595713dSTony Lindgren #define OMAP3430ES2_EN_MMC3_MASK (1 << 30) 23c595713dSTony Lindgren #define OMAP3430ES2_EN_MMC3_SHIFT 30 24c595713dSTony Lindgren #define OMAP3430_EN_MSPRO (1 << 23) 25c595713dSTony Lindgren #define OMAP3430_EN_MSPRO_SHIFT 23 26c595713dSTony Lindgren #define OMAP3430_EN_HDQ (1 << 22) 27c595713dSTony Lindgren #define OMAP3430_EN_HDQ_SHIFT 22 28c595713dSTony Lindgren #define OMAP3430ES1_EN_FSHOSTUSB (1 << 5) 29c595713dSTony Lindgren #define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5 30c595713dSTony Lindgren #define OMAP3430ES1_EN_D2D (1 << 3) 31c595713dSTony Lindgren #define OMAP3430ES1_EN_D2D_SHIFT 3 32c595713dSTony Lindgren #define OMAP3430_EN_SSI (1 << 0) 33c595713dSTony Lindgren #define OMAP3430_EN_SSI_SHIFT 0 34c595713dSTony Lindgren 35c595713dSTony Lindgren /* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */ 36c595713dSTony Lindgren #define OMAP3430ES2_EN_USBTLL_SHIFT 2 37c595713dSTony Lindgren #define OMAP3430ES2_EN_USBTLL_MASK (1 << 2) 38c595713dSTony Lindgren 39c595713dSTony Lindgren /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ 40c595713dSTony Lindgren #define OMAP3430_EN_WDT2 (1 << 5) 41c595713dSTony Lindgren #define OMAP3430_EN_WDT2_SHIFT 5 42c595713dSTony Lindgren 43c595713dSTony Lindgren /* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */ 44c595713dSTony Lindgren #define OMAP3430_EN_CAM (1 << 0) 45c595713dSTony Lindgren #define OMAP3430_EN_CAM_SHIFT 0 46c595713dSTony Lindgren 47c595713dSTony Lindgren /* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */ 48c595713dSTony Lindgren #define OMAP3430_EN_WDT3 (1 << 12) 49c595713dSTony Lindgren #define OMAP3430_EN_WDT3_SHIFT 12 50c595713dSTony Lindgren 51c595713dSTony Lindgren /* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */ 52c595713dSTony Lindgren #define OMAP3430_OVERRIDE_ENABLE (1 << 19) 53c595713dSTony Lindgren 54c595713dSTony Lindgren 55c595713dSTony Lindgren /* Bits specific to each register */ 56c595713dSTony Lindgren 57c595713dSTony Lindgren /* CM_FCLKEN_IVA2 */ 58c595713dSTony Lindgren #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2 (1 << 0) 5931c203d4SHiroshi DOYU #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0 60c595713dSTony Lindgren 61c595713dSTony Lindgren /* CM_CLKEN_PLL_IVA2 */ 62c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8 63c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8) 64c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4 65c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4) 66c595713dSTony Lindgren #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3 67c595713dSTony Lindgren #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3) 68c595713dSTony Lindgren #define OMAP3430_EN_IVA2_DPLL_SHIFT 0 69c595713dSTony Lindgren #define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0) 70c595713dSTony Lindgren 71c595713dSTony Lindgren /* CM_IDLEST_IVA2 */ 72c595713dSTony Lindgren #define OMAP3430_ST_IVA2 (1 << 0) 73c595713dSTony Lindgren 74c595713dSTony Lindgren /* CM_IDLEST_PLL_IVA2 */ 75542313ccSPaul Walmsley #define OMAP3430_ST_IVA2_CLK_SHIFT 0 76542313ccSPaul Walmsley #define OMAP3430_ST_IVA2_CLK_MASK (1 << 0) 77c595713dSTony Lindgren 78c595713dSTony Lindgren /* CM_AUTOIDLE_PLL_IVA2 */ 79c595713dSTony Lindgren #define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0 80c595713dSTony Lindgren #define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0) 81c595713dSTony Lindgren 82c595713dSTony Lindgren /* CM_CLKSEL1_PLL_IVA2 */ 83c595713dSTony Lindgren #define OMAP3430_IVA2_CLK_SRC_SHIFT 19 84c595713dSTony Lindgren #define OMAP3430_IVA2_CLK_SRC_MASK (0x3 << 19) 85c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_MULT_SHIFT 8 86c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) 87c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_DIV_SHIFT 0 88c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0) 89c595713dSTony Lindgren 90c595713dSTony Lindgren /* CM_CLKSEL2_PLL_IVA2 */ 91c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0 92c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0) 93c595713dSTony Lindgren 94c595713dSTony Lindgren /* CM_CLKSTCTRL_IVA2 */ 95c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0 96c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0) 97c595713dSTony Lindgren 98c595713dSTony Lindgren /* CM_CLKSTST_IVA2 */ 99c595713dSTony Lindgren #define OMAP3430_CLKACTIVITY_IVA2 (1 << 0) 100c595713dSTony Lindgren 101c595713dSTony Lindgren /* CM_REVISION specific bits */ 102c595713dSTony Lindgren 103c595713dSTony Lindgren /* CM_SYSCONFIG specific bits */ 104c595713dSTony Lindgren 105c595713dSTony Lindgren /* CM_CLKEN_PLL_MPU */ 106c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8 107c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8) 108c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4 109c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4) 110c595713dSTony Lindgren #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3 111c595713dSTony Lindgren #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3) 112c595713dSTony Lindgren #define OMAP3430_EN_MPU_DPLL_SHIFT 0 113c595713dSTony Lindgren #define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0) 114c595713dSTony Lindgren 115c595713dSTony Lindgren /* CM_IDLEST_MPU */ 116c595713dSTony Lindgren #define OMAP3430_ST_MPU (1 << 0) 117c595713dSTony Lindgren 118c595713dSTony Lindgren /* CM_IDLEST_PLL_MPU */ 119542313ccSPaul Walmsley #define OMAP3430_ST_MPU_CLK_SHIFT 0 1203760d31fSRoman Tereshonkov #define OMAP3430_ST_MPU_CLK_MASK (1 << 0) 121c595713dSTony Lindgren 122c595713dSTony Lindgren /* CM_AUTOIDLE_PLL_MPU */ 123c595713dSTony Lindgren #define OMAP3430_AUTO_MPU_DPLL_SHIFT 0 124c595713dSTony Lindgren #define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0) 125c595713dSTony Lindgren 126c595713dSTony Lindgren /* CM_CLKSEL1_PLL_MPU */ 127c595713dSTony Lindgren #define OMAP3430_MPU_CLK_SRC_SHIFT 19 128c595713dSTony Lindgren #define OMAP3430_MPU_CLK_SRC_MASK (0x3 << 19) 129c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_MULT_SHIFT 8 130c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) 131c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_DIV_SHIFT 0 132c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0) 133c595713dSTony Lindgren 134c595713dSTony Lindgren /* CM_CLKSEL2_PLL_MPU */ 135c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0 136c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0) 137c595713dSTony Lindgren 138c595713dSTony Lindgren /* CM_CLKSTCTRL_MPU */ 139c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_MPU_SHIFT 0 140c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0) 141c595713dSTony Lindgren 142c595713dSTony Lindgren /* CM_CLKSTST_MPU */ 143c595713dSTony Lindgren #define OMAP3430_CLKACTIVITY_MPU (1 << 0) 144c595713dSTony Lindgren 145c595713dSTony Lindgren /* CM_FCLKEN1_CORE specific bits */ 146c595713dSTony Lindgren 147c595713dSTony Lindgren /* CM_ICLKEN1_CORE specific bits */ 148c595713dSTony Lindgren #define OMAP3430_EN_ICR (1 << 29) 149c595713dSTony Lindgren #define OMAP3430_EN_ICR_SHIFT 29 150c595713dSTony Lindgren #define OMAP3430_EN_AES2 (1 << 28) 151c595713dSTony Lindgren #define OMAP3430_EN_AES2_SHIFT 28 152c595713dSTony Lindgren #define OMAP3430_EN_SHA12 (1 << 27) 153c595713dSTony Lindgren #define OMAP3430_EN_SHA12_SHIFT 27 154c595713dSTony Lindgren #define OMAP3430_EN_DES2 (1 << 26) 155c595713dSTony Lindgren #define OMAP3430_EN_DES2_SHIFT 26 156c595713dSTony Lindgren #define OMAP3430ES1_EN_FAC (1 << 8) 157c595713dSTony Lindgren #define OMAP3430ES1_EN_FAC_SHIFT 8 158c595713dSTony Lindgren #define OMAP3430_EN_MAILBOXES (1 << 7) 159c595713dSTony Lindgren #define OMAP3430_EN_MAILBOXES_SHIFT 7 160c595713dSTony Lindgren #define OMAP3430_EN_OMAPCTRL (1 << 6) 161c595713dSTony Lindgren #define OMAP3430_EN_OMAPCTRL_SHIFT 6 162c595713dSTony Lindgren #define OMAP3430_EN_SDRC (1 << 1) 163c595713dSTony Lindgren #define OMAP3430_EN_SDRC_SHIFT 1 164c595713dSTony Lindgren 165c595713dSTony Lindgren /* CM_ICLKEN2_CORE */ 166c595713dSTony Lindgren #define OMAP3430_EN_PKA (1 << 4) 167c595713dSTony Lindgren #define OMAP3430_EN_PKA_SHIFT 4 168c595713dSTony Lindgren #define OMAP3430_EN_AES1 (1 << 3) 169c595713dSTony Lindgren #define OMAP3430_EN_AES1_SHIFT 3 170c595713dSTony Lindgren #define OMAP3430_EN_RNG (1 << 2) 171c595713dSTony Lindgren #define OMAP3430_EN_RNG_SHIFT 2 172c595713dSTony Lindgren #define OMAP3430_EN_SHA11 (1 << 1) 173c595713dSTony Lindgren #define OMAP3430_EN_SHA11_SHIFT 1 174c595713dSTony Lindgren #define OMAP3430_EN_DES1 (1 << 0) 175c595713dSTony Lindgren #define OMAP3430_EN_DES1_SHIFT 0 176c595713dSTony Lindgren 177c595713dSTony Lindgren /* CM_FCLKEN3_CORE specific bits */ 178c595713dSTony Lindgren #define OMAP3430ES2_EN_TS_SHIFT 1 179c595713dSTony Lindgren #define OMAP3430ES2_EN_TS_MASK (1 << 1) 180c595713dSTony Lindgren #define OMAP3430ES2_EN_CPEFUSE_SHIFT 0 181c595713dSTony Lindgren #define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0) 182c595713dSTony Lindgren 183c595713dSTony Lindgren /* CM_IDLEST1_CORE specific bits */ 184c595713dSTony Lindgren #define OMAP3430_ST_ICR (1 << 29) 185c595713dSTony Lindgren #define OMAP3430_ST_AES2 (1 << 28) 186c595713dSTony Lindgren #define OMAP3430_ST_SHA12 (1 << 27) 187c595713dSTony Lindgren #define OMAP3430_ST_DES2 (1 << 26) 188c595713dSTony Lindgren #define OMAP3430_ST_MSPRO (1 << 23) 189c595713dSTony Lindgren #define OMAP3430_ST_HDQ (1 << 22) 190c595713dSTony Lindgren #define OMAP3430ES1_ST_FAC (1 << 8) 191c595713dSTony Lindgren #define OMAP3430ES1_ST_MAILBOXES (1 << 7) 192c595713dSTony Lindgren #define OMAP3430_ST_OMAPCTRL (1 << 6) 193c595713dSTony Lindgren #define OMAP3430_ST_SDMA (1 << 2) 194c595713dSTony Lindgren #define OMAP3430_ST_SDRC (1 << 1) 195c595713dSTony Lindgren #define OMAP3430_ST_SSI (1 << 0) 196c595713dSTony Lindgren 197c595713dSTony Lindgren /* CM_IDLEST2_CORE */ 198c595713dSTony Lindgren #define OMAP3430_ST_PKA (1 << 4) 199c595713dSTony Lindgren #define OMAP3430_ST_AES1 (1 << 3) 200c595713dSTony Lindgren #define OMAP3430_ST_RNG (1 << 2) 201c595713dSTony Lindgren #define OMAP3430_ST_SHA11 (1 << 1) 202c595713dSTony Lindgren #define OMAP3430_ST_DES1 (1 << 0) 203c595713dSTony Lindgren 204c595713dSTony Lindgren /* CM_IDLEST3_CORE */ 205c595713dSTony Lindgren #define OMAP3430ES2_ST_USBTLL_SHIFT 2 206c595713dSTony Lindgren #define OMAP3430ES2_ST_USBTLL_MASK (1 << 2) 207c595713dSTony Lindgren 208c595713dSTony Lindgren /* CM_AUTOIDLE1_CORE */ 209c595713dSTony Lindgren #define OMAP3430_AUTO_AES2 (1 << 28) 210c595713dSTony Lindgren #define OMAP3430_AUTO_AES2_SHIFT 28 211c595713dSTony Lindgren #define OMAP3430_AUTO_SHA12 (1 << 27) 212c595713dSTony Lindgren #define OMAP3430_AUTO_SHA12_SHIFT 27 213c595713dSTony Lindgren #define OMAP3430_AUTO_DES2 (1 << 26) 214c595713dSTony Lindgren #define OMAP3430_AUTO_DES2_SHIFT 26 215c595713dSTony Lindgren #define OMAP3430_AUTO_MMC2 (1 << 25) 216c595713dSTony Lindgren #define OMAP3430_AUTO_MMC2_SHIFT 25 217c595713dSTony Lindgren #define OMAP3430_AUTO_MMC1 (1 << 24) 218c595713dSTony Lindgren #define OMAP3430_AUTO_MMC1_SHIFT 24 219c595713dSTony Lindgren #define OMAP3430_AUTO_MSPRO (1 << 23) 220c595713dSTony Lindgren #define OMAP3430_AUTO_MSPRO_SHIFT 23 221c595713dSTony Lindgren #define OMAP3430_AUTO_HDQ (1 << 22) 222c595713dSTony Lindgren #define OMAP3430_AUTO_HDQ_SHIFT 22 223c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI4 (1 << 21) 224c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI4_SHIFT 21 225c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI3 (1 << 20) 226c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI3_SHIFT 20 227c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI2 (1 << 19) 228c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI2_SHIFT 19 229c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI1 (1 << 18) 230c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI1_SHIFT 18 231c595713dSTony Lindgren #define OMAP3430_AUTO_I2C3 (1 << 17) 232c595713dSTony Lindgren #define OMAP3430_AUTO_I2C3_SHIFT 17 233c595713dSTony Lindgren #define OMAP3430_AUTO_I2C2 (1 << 16) 234c595713dSTony Lindgren #define OMAP3430_AUTO_I2C2_SHIFT 16 235c595713dSTony Lindgren #define OMAP3430_AUTO_I2C1 (1 << 15) 236c595713dSTony Lindgren #define OMAP3430_AUTO_I2C1_SHIFT 15 237c595713dSTony Lindgren #define OMAP3430_AUTO_UART2 (1 << 14) 238c595713dSTony Lindgren #define OMAP3430_AUTO_UART2_SHIFT 14 239c595713dSTony Lindgren #define OMAP3430_AUTO_UART1 (1 << 13) 240c595713dSTony Lindgren #define OMAP3430_AUTO_UART1_SHIFT 13 241c595713dSTony Lindgren #define OMAP3430_AUTO_GPT11 (1 << 12) 242c595713dSTony Lindgren #define OMAP3430_AUTO_GPT11_SHIFT 12 243c595713dSTony Lindgren #define OMAP3430_AUTO_GPT10 (1 << 11) 244c595713dSTony Lindgren #define OMAP3430_AUTO_GPT10_SHIFT 11 245c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP5 (1 << 10) 246c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP5_SHIFT 10 247c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP1 (1 << 9) 248c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP1_SHIFT 9 249c595713dSTony Lindgren #define OMAP3430ES1_AUTO_FAC (1 << 8) 250c595713dSTony Lindgren #define OMAP3430ES1_AUTO_FAC_SHIFT 8 251c595713dSTony Lindgren #define OMAP3430_AUTO_MAILBOXES (1 << 7) 252c595713dSTony Lindgren #define OMAP3430_AUTO_MAILBOXES_SHIFT 7 253c595713dSTony Lindgren #define OMAP3430_AUTO_OMAPCTRL (1 << 6) 254c595713dSTony Lindgren #define OMAP3430_AUTO_OMAPCTRL_SHIFT 6 255c595713dSTony Lindgren #define OMAP3430ES1_AUTO_FSHOSTUSB (1 << 5) 256c595713dSTony Lindgren #define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5 257c595713dSTony Lindgren #define OMAP3430_AUTO_HSOTGUSB (1 << 4) 258c595713dSTony Lindgren #define OMAP3430_AUTO_HSOTGUSB_SHIFT 4 259c595713dSTony Lindgren #define OMAP3430ES1_AUTO_D2D (1 << 3) 260c595713dSTony Lindgren #define OMAP3430ES1_AUTO_D2D_SHIFT 3 261c595713dSTony Lindgren #define OMAP3430_AUTO_SSI (1 << 0) 262c595713dSTony Lindgren #define OMAP3430_AUTO_SSI_SHIFT 0 263c595713dSTony Lindgren 264c595713dSTony Lindgren /* CM_AUTOIDLE2_CORE */ 265c595713dSTony Lindgren #define OMAP3430_AUTO_PKA (1 << 4) 266c595713dSTony Lindgren #define OMAP3430_AUTO_PKA_SHIFT 4 267c595713dSTony Lindgren #define OMAP3430_AUTO_AES1 (1 << 3) 268c595713dSTony Lindgren #define OMAP3430_AUTO_AES1_SHIFT 3 269c595713dSTony Lindgren #define OMAP3430_AUTO_RNG (1 << 2) 270c595713dSTony Lindgren #define OMAP3430_AUTO_RNG_SHIFT 2 271c595713dSTony Lindgren #define OMAP3430_AUTO_SHA11 (1 << 1) 272c595713dSTony Lindgren #define OMAP3430_AUTO_SHA11_SHIFT 1 273c595713dSTony Lindgren #define OMAP3430_AUTO_DES1 (1 << 0) 274c595713dSTony Lindgren #define OMAP3430_AUTO_DES1_SHIFT 0 275c595713dSTony Lindgren 276c595713dSTony Lindgren /* CM_AUTOIDLE3_CORE */ 277c595713dSTony Lindgren #define OMAP3430ES2_AUTO_USBTLL_SHIFT 2 278c595713dSTony Lindgren #define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2) 279c595713dSTony Lindgren 280c595713dSTony Lindgren /* CM_CLKSEL_CORE */ 281c595713dSTony Lindgren #define OMAP3430_CLKSEL_SSI_SHIFT 8 282c595713dSTony Lindgren #define OMAP3430_CLKSEL_SSI_MASK (0xf << 8) 283c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT11_MASK (1 << 7) 284c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT11_SHIFT 7 285c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT10_MASK (1 << 6) 286c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT10_SHIFT 6 287c595713dSTony Lindgren #define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4 288c595713dSTony Lindgren #define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4) 289c595713dSTony Lindgren #define OMAP3430_CLKSEL_L4_SHIFT 2 290c595713dSTony Lindgren #define OMAP3430_CLKSEL_L4_MASK (0x3 << 2) 291c595713dSTony Lindgren #define OMAP3430_CLKSEL_L3_SHIFT 0 292c595713dSTony Lindgren #define OMAP3430_CLKSEL_L3_MASK (0x3 << 0) 293c595713dSTony Lindgren 294c595713dSTony Lindgren /* CM_CLKSTCTRL_CORE */ 295c595713dSTony Lindgren #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4 296c595713dSTony Lindgren #define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4) 297c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_L4_SHIFT 2 298c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2) 299c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_L3_SHIFT 0 300c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0) 301c595713dSTony Lindgren 302c595713dSTony Lindgren /* CM_CLKSTST_CORE */ 303c595713dSTony Lindgren #define OMAP3430ES1_CLKACTIVITY_D2D (1 << 2) 304c595713dSTony Lindgren #define OMAP3430_CLKACTIVITY_L4 (1 << 1) 305c595713dSTony Lindgren #define OMAP3430_CLKACTIVITY_L3 (1 << 0) 306c595713dSTony Lindgren 307c595713dSTony Lindgren /* CM_FCLKEN_GFX */ 308c595713dSTony Lindgren #define OMAP3430ES1_EN_3D (1 << 2) 309c595713dSTony Lindgren #define OMAP3430ES1_EN_3D_SHIFT 2 310c595713dSTony Lindgren #define OMAP3430ES1_EN_2D (1 << 1) 311c595713dSTony Lindgren #define OMAP3430ES1_EN_2D_SHIFT 1 312c595713dSTony Lindgren 313c595713dSTony Lindgren /* CM_ICLKEN_GFX specific bits */ 314c595713dSTony Lindgren 315c595713dSTony Lindgren /* CM_IDLEST_GFX specific bits */ 316c595713dSTony Lindgren 317c595713dSTony Lindgren /* CM_CLKSEL_GFX specific bits */ 318c595713dSTony Lindgren 319c595713dSTony Lindgren /* CM_SLEEPDEP_GFX specific bits */ 320c595713dSTony Lindgren 321c595713dSTony Lindgren /* CM_CLKSTCTRL_GFX */ 322c595713dSTony Lindgren #define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0 323c595713dSTony Lindgren #define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0) 324c595713dSTony Lindgren 325c595713dSTony Lindgren /* CM_CLKSTST_GFX */ 326c595713dSTony Lindgren #define OMAP3430ES1_CLKACTIVITY_GFX (1 << 0) 327c595713dSTony Lindgren 328c595713dSTony Lindgren /* CM_FCLKEN_SGX */ 329c595713dSTony Lindgren #define OMAP3430ES2_EN_SGX_SHIFT 1 330c595713dSTony Lindgren #define OMAP3430ES2_EN_SGX_MASK (1 << 1) 331c595713dSTony Lindgren 332c595713dSTony Lindgren /* CM_CLKSEL_SGX */ 333c595713dSTony Lindgren #define OMAP3430ES2_CLKSEL_SGX_SHIFT 0 334c595713dSTony Lindgren #define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0) 335c595713dSTony Lindgren 336c595713dSTony Lindgren /* CM_FCLKEN_WKUP specific bits */ 337c595713dSTony Lindgren #define OMAP3430ES2_EN_USIMOCP_SHIFT 9 338c595713dSTony Lindgren 339c595713dSTony Lindgren /* CM_ICLKEN_WKUP specific bits */ 340c595713dSTony Lindgren #define OMAP3430_EN_WDT1 (1 << 4) 341c595713dSTony Lindgren #define OMAP3430_EN_WDT1_SHIFT 4 342c595713dSTony Lindgren #define OMAP3430_EN_32KSYNC (1 << 2) 343c595713dSTony Lindgren #define OMAP3430_EN_32KSYNC_SHIFT 2 344c595713dSTony Lindgren 345c595713dSTony Lindgren /* CM_IDLEST_WKUP specific bits */ 346c595713dSTony Lindgren #define OMAP3430_ST_WDT2 (1 << 5) 347c595713dSTony Lindgren #define OMAP3430_ST_WDT1 (1 << 4) 348c595713dSTony Lindgren #define OMAP3430_ST_32KSYNC (1 << 2) 349c595713dSTony Lindgren 350c595713dSTony Lindgren /* CM_AUTOIDLE_WKUP */ 351c595713dSTony Lindgren #define OMAP3430_AUTO_WDT2 (1 << 5) 352c595713dSTony Lindgren #define OMAP3430_AUTO_WDT2_SHIFT 5 353c595713dSTony Lindgren #define OMAP3430_AUTO_WDT1 (1 << 4) 354c595713dSTony Lindgren #define OMAP3430_AUTO_WDT1_SHIFT 4 355c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO1 (1 << 3) 356c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO1_SHIFT 3 357c595713dSTony Lindgren #define OMAP3430_AUTO_32KSYNC (1 << 2) 358c595713dSTony Lindgren #define OMAP3430_AUTO_32KSYNC_SHIFT 2 359c595713dSTony Lindgren #define OMAP3430_AUTO_GPT12 (1 << 1) 360c595713dSTony Lindgren #define OMAP3430_AUTO_GPT12_SHIFT 1 361c595713dSTony Lindgren #define OMAP3430_AUTO_GPT1 (1 << 0) 362c595713dSTony Lindgren #define OMAP3430_AUTO_GPT1_SHIFT 0 363c595713dSTony Lindgren 364c595713dSTony Lindgren /* CM_CLKSEL_WKUP */ 365c595713dSTony Lindgren #define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3) 366c595713dSTony Lindgren #define OMAP3430_CLKSEL_RM_SHIFT 1 367c595713dSTony Lindgren #define OMAP3430_CLKSEL_RM_MASK (0x3 << 1) 368c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT1_SHIFT 0 369c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT1_MASK (1 << 0) 370c595713dSTony Lindgren 371c595713dSTony Lindgren /* CM_CLKEN_PLL */ 372c595713dSTony Lindgren #define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31 373c595713dSTony Lindgren #define OMAP3430_PWRDN_CAM_SHIFT 30 374c595713dSTony Lindgren #define OMAP3430_PWRDN_DSS1_SHIFT 29 375c595713dSTony Lindgren #define OMAP3430_PWRDN_TV_SHIFT 28 376c595713dSTony Lindgren #define OMAP3430_PWRDN_96M_SHIFT 27 377c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24 378c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24) 379c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20 380c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20) 381c595713dSTony Lindgren #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19 382c595713dSTony Lindgren #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19) 383c595713dSTony Lindgren #define OMAP3430_EN_PERIPH_DPLL_SHIFT 16 384c595713dSTony Lindgren #define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16) 385c595713dSTony Lindgren #define OMAP3430_PWRDN_EMU_CORE_SHIFT 12 386c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8 387c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8) 388c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4 389c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4) 390c595713dSTony Lindgren #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3 391c595713dSTony Lindgren #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3) 392c595713dSTony Lindgren #define OMAP3430_EN_CORE_DPLL_SHIFT 0 393c595713dSTony Lindgren #define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0) 394c595713dSTony Lindgren 395c595713dSTony Lindgren /* CM_CLKEN2_PLL */ 396c595713dSTony Lindgren #define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10 397c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8) 398c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4 399c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4) 400c595713dSTony Lindgren #define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3 401c595713dSTony Lindgren #define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0 402c595713dSTony Lindgren #define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0) 403c595713dSTony Lindgren 404c595713dSTony Lindgren /* CM_IDLEST_CKGEN */ 405c595713dSTony Lindgren #define OMAP3430_ST_54M_CLK (1 << 5) 406c595713dSTony Lindgren #define OMAP3430_ST_12M_CLK (1 << 4) 407c595713dSTony Lindgren #define OMAP3430_ST_48M_CLK (1 << 3) 408c595713dSTony Lindgren #define OMAP3430_ST_96M_CLK (1 << 2) 409542313ccSPaul Walmsley #define OMAP3430_ST_PERIPH_CLK_SHIFT 1 410542313ccSPaul Walmsley #define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1) 411542313ccSPaul Walmsley #define OMAP3430_ST_CORE_CLK_SHIFT 0 412542313ccSPaul Walmsley #define OMAP3430_ST_CORE_CLK_MASK (1 << 0) 413c595713dSTony Lindgren 414c595713dSTony Lindgren /* CM_IDLEST2_CKGEN */ 415c595713dSTony Lindgren #define OMAP3430ES2_ST_120M_CLK_SHIFT 1 416c595713dSTony Lindgren #define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1) 417c595713dSTony Lindgren #define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0 418c595713dSTony Lindgren #define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0) 419c595713dSTony Lindgren 420c595713dSTony Lindgren /* CM_AUTOIDLE_PLL */ 421c595713dSTony Lindgren #define OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3 422c595713dSTony Lindgren #define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3) 423c595713dSTony Lindgren #define OMAP3430_AUTO_CORE_DPLL_SHIFT 0 424c595713dSTony Lindgren #define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0) 425c595713dSTony Lindgren 426542313ccSPaul Walmsley /* CM_AUTOIDLE2_PLL */ 427542313ccSPaul Walmsley #define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT 0 428542313ccSPaul Walmsley #define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0) 429542313ccSPaul Walmsley 430c595713dSTony Lindgren /* CM_CLKSEL1_PLL */ 431c595713dSTony Lindgren /* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */ 432c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27 433c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27) 434c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_MULT_SHIFT 16 435c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) 436c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_DIV_SHIFT 8 437c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8) 438c595713dSTony Lindgren #define OMAP3430_SOURCE_54M (1 << 5) 439c595713dSTony Lindgren #define OMAP3430_SOURCE_48M (1 << 3) 440c595713dSTony Lindgren 441c595713dSTony Lindgren /* CM_CLKSEL2_PLL */ 442c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8 443c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8) 444c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0 445c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0) 446c595713dSTony Lindgren 447c595713dSTony Lindgren /* CM_CLKSEL3_PLL */ 448c595713dSTony Lindgren #define OMAP3430_DIV_96M_SHIFT 0 449c595713dSTony Lindgren #define OMAP3430_DIV_96M_MASK (0x1f << 0) 450c595713dSTony Lindgren 451c595713dSTony Lindgren /* CM_CLKSEL4_PLL */ 452c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8 453c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8) 454c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0 455c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0) 456c595713dSTony Lindgren 457c595713dSTony Lindgren /* CM_CLKSEL5_PLL */ 458c595713dSTony Lindgren #define OMAP3430ES2_DIV_120M_SHIFT 0 459c595713dSTony Lindgren #define OMAP3430ES2_DIV_120M_MASK (0x1f << 0) 460c595713dSTony Lindgren 461c595713dSTony Lindgren /* CM_CLKOUT_CTRL */ 462c595713dSTony Lindgren #define OMAP3430_CLKOUT2_EN_SHIFT 7 463c595713dSTony Lindgren #define OMAP3430_CLKOUT2_EN (1 << 7) 464c595713dSTony Lindgren #define OMAP3430_CLKOUT2_DIV_SHIFT 3 465c595713dSTony Lindgren #define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3) 466c595713dSTony Lindgren #define OMAP3430_CLKOUT2SOURCE_SHIFT 0 467c595713dSTony Lindgren #define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0) 468c595713dSTony Lindgren 469c595713dSTony Lindgren /* CM_FCLKEN_DSS */ 470c595713dSTony Lindgren #define OMAP3430_EN_TV (1 << 2) 471c595713dSTony Lindgren #define OMAP3430_EN_TV_SHIFT 2 472c595713dSTony Lindgren #define OMAP3430_EN_DSS2 (1 << 1) 473c595713dSTony Lindgren #define OMAP3430_EN_DSS2_SHIFT 1 474c595713dSTony Lindgren #define OMAP3430_EN_DSS1 (1 << 0) 475c595713dSTony Lindgren #define OMAP3430_EN_DSS1_SHIFT 0 476c595713dSTony Lindgren 477c595713dSTony Lindgren /* CM_ICLKEN_DSS */ 478c595713dSTony Lindgren #define OMAP3430_CM_ICLKEN_DSS_EN_DSS (1 << 0) 479c595713dSTony Lindgren #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 480c595713dSTony Lindgren 481c595713dSTony Lindgren /* CM_IDLEST_DSS */ 482c595713dSTony Lindgren #define OMAP3430_ST_DSS (1 << 0) 483c595713dSTony Lindgren 484c595713dSTony Lindgren /* CM_AUTOIDLE_DSS */ 485c595713dSTony Lindgren #define OMAP3430_AUTO_DSS (1 << 0) 486c595713dSTony Lindgren #define OMAP3430_AUTO_DSS_SHIFT 0 487c595713dSTony Lindgren 488c595713dSTony Lindgren /* CM_CLKSEL_DSS */ 489c595713dSTony Lindgren #define OMAP3430_CLKSEL_TV_SHIFT 8 490c595713dSTony Lindgren #define OMAP3430_CLKSEL_TV_MASK (0x1f << 8) 491c595713dSTony Lindgren #define OMAP3430_CLKSEL_DSS1_SHIFT 0 492c595713dSTony Lindgren #define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0) 493c595713dSTony Lindgren 494c595713dSTony Lindgren /* CM_SLEEPDEP_DSS specific bits */ 495c595713dSTony Lindgren 496c595713dSTony Lindgren /* CM_CLKSTCTRL_DSS */ 497c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_DSS_SHIFT 0 498c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0) 499c595713dSTony Lindgren 500c595713dSTony Lindgren /* CM_CLKSTST_DSS */ 501c595713dSTony Lindgren #define OMAP3430_CLKACTIVITY_DSS (1 << 0) 502c595713dSTony Lindgren 503c595713dSTony Lindgren /* CM_FCLKEN_CAM specific bits */ 504c595713dSTony Lindgren 505c595713dSTony Lindgren /* CM_ICLKEN_CAM specific bits */ 506c595713dSTony Lindgren 507c595713dSTony Lindgren /* CM_IDLEST_CAM */ 508c595713dSTony Lindgren #define OMAP3430_ST_CAM (1 << 0) 509c595713dSTony Lindgren 510c595713dSTony Lindgren /* CM_AUTOIDLE_CAM */ 511c595713dSTony Lindgren #define OMAP3430_AUTO_CAM (1 << 0) 512c595713dSTony Lindgren #define OMAP3430_AUTO_CAM_SHIFT 0 513c595713dSTony Lindgren 514c595713dSTony Lindgren /* CM_CLKSEL_CAM */ 515c595713dSTony Lindgren #define OMAP3430_CLKSEL_CAM_SHIFT 0 516c595713dSTony Lindgren #define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0) 517c595713dSTony Lindgren 518c595713dSTony Lindgren /* CM_SLEEPDEP_CAM specific bits */ 519c595713dSTony Lindgren 520c595713dSTony Lindgren /* CM_CLKSTCTRL_CAM */ 521c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_CAM_SHIFT 0 522c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0) 523c595713dSTony Lindgren 524c595713dSTony Lindgren /* CM_CLKSTST_CAM */ 525c595713dSTony Lindgren #define OMAP3430_CLKACTIVITY_CAM (1 << 0) 526c595713dSTony Lindgren 527c595713dSTony Lindgren /* CM_FCLKEN_PER specific bits */ 528c595713dSTony Lindgren 529c595713dSTony Lindgren /* CM_ICLKEN_PER specific bits */ 530c595713dSTony Lindgren 531c595713dSTony Lindgren /* CM_IDLEST_PER */ 532c595713dSTony Lindgren #define OMAP3430_ST_WDT3 (1 << 12) 533c595713dSTony Lindgren #define OMAP3430_ST_MCBSP4 (1 << 2) 534c595713dSTony Lindgren #define OMAP3430_ST_MCBSP3 (1 << 1) 535c595713dSTony Lindgren #define OMAP3430_ST_MCBSP2 (1 << 0) 536c595713dSTony Lindgren 537c595713dSTony Lindgren /* CM_AUTOIDLE_PER */ 538c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO6 (1 << 17) 539c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO6_SHIFT 17 540c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO5 (1 << 16) 541c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO5_SHIFT 16 542c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO4 (1 << 15) 543c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO4_SHIFT 15 544c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO3 (1 << 14) 545c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO3_SHIFT 14 546c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO2 (1 << 13) 547c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO2_SHIFT 13 548c595713dSTony Lindgren #define OMAP3430_AUTO_WDT3 (1 << 12) 549c595713dSTony Lindgren #define OMAP3430_AUTO_WDT3_SHIFT 12 550c595713dSTony Lindgren #define OMAP3430_AUTO_UART3 (1 << 11) 551c595713dSTony Lindgren #define OMAP3430_AUTO_UART3_SHIFT 11 552c595713dSTony Lindgren #define OMAP3430_AUTO_GPT9 (1 << 10) 553c595713dSTony Lindgren #define OMAP3430_AUTO_GPT9_SHIFT 10 554c595713dSTony Lindgren #define OMAP3430_AUTO_GPT8 (1 << 9) 555c595713dSTony Lindgren #define OMAP3430_AUTO_GPT8_SHIFT 9 556c595713dSTony Lindgren #define OMAP3430_AUTO_GPT7 (1 << 8) 557c595713dSTony Lindgren #define OMAP3430_AUTO_GPT7_SHIFT 8 558c595713dSTony Lindgren #define OMAP3430_AUTO_GPT6 (1 << 7) 559c595713dSTony Lindgren #define OMAP3430_AUTO_GPT6_SHIFT 7 560c595713dSTony Lindgren #define OMAP3430_AUTO_GPT5 (1 << 6) 561c595713dSTony Lindgren #define OMAP3430_AUTO_GPT5_SHIFT 6 562c595713dSTony Lindgren #define OMAP3430_AUTO_GPT4 (1 << 5) 563c595713dSTony Lindgren #define OMAP3430_AUTO_GPT4_SHIFT 5 564c595713dSTony Lindgren #define OMAP3430_AUTO_GPT3 (1 << 4) 565c595713dSTony Lindgren #define OMAP3430_AUTO_GPT3_SHIFT 4 566c595713dSTony Lindgren #define OMAP3430_AUTO_GPT2 (1 << 3) 567c595713dSTony Lindgren #define OMAP3430_AUTO_GPT2_SHIFT 3 568c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP4 (1 << 2) 569c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP4_SHIFT 2 570c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP3 (1 << 1) 571c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP3_SHIFT 1 572c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP2 (1 << 0) 573c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP2_SHIFT 0 574c595713dSTony Lindgren 575c595713dSTony Lindgren /* CM_CLKSEL_PER */ 576c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT9_MASK (1 << 7) 577c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT9_SHIFT 7 578c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT8_MASK (1 << 6) 579c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT8_SHIFT 6 580c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT7_MASK (1 << 5) 581c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT7_SHIFT 5 582c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT6_MASK (1 << 4) 583c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT6_SHIFT 4 584c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT5_MASK (1 << 3) 585c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT5_SHIFT 3 586c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT4_MASK (1 << 2) 587c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT4_SHIFT 2 588c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT3_MASK (1 << 1) 589c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT3_SHIFT 1 590c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT2_MASK (1 << 0) 591c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT2_SHIFT 0 592c595713dSTony Lindgren 593c595713dSTony Lindgren /* CM_SLEEPDEP_PER specific bits */ 594c595713dSTony Lindgren #define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2 (1 << 2) 595c595713dSTony Lindgren 596c595713dSTony Lindgren /* CM_CLKSTCTRL_PER */ 597c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_PER_SHIFT 0 598c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0) 599c595713dSTony Lindgren 600c595713dSTony Lindgren /* CM_CLKSTST_PER */ 601c595713dSTony Lindgren #define OMAP3430_CLKACTIVITY_PER (1 << 0) 602c595713dSTony Lindgren 603c595713dSTony Lindgren /* CM_CLKSEL1_EMU */ 604c595713dSTony Lindgren #define OMAP3430_DIV_DPLL4_SHIFT 24 605c595713dSTony Lindgren #define OMAP3430_DIV_DPLL4_MASK (0x1f << 24) 606c595713dSTony Lindgren #define OMAP3430_DIV_DPLL3_SHIFT 16 607c595713dSTony Lindgren #define OMAP3430_DIV_DPLL3_MASK (0x1f << 16) 608c595713dSTony Lindgren #define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 609c595713dSTony Lindgren #define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11) 610c595713dSTony Lindgren #define OMAP3430_CLKSEL_PCLK_SHIFT 8 611c595713dSTony Lindgren #define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8) 612c595713dSTony Lindgren #define OMAP3430_CLKSEL_PCLKX2_SHIFT 6 613c595713dSTony Lindgren #define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6) 614c595713dSTony Lindgren #define OMAP3430_CLKSEL_ATCLK_SHIFT 4 615c595713dSTony Lindgren #define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4) 616c595713dSTony Lindgren #define OMAP3430_TRACE_MUX_CTRL_SHIFT 2 617c595713dSTony Lindgren #define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2) 618c595713dSTony Lindgren #define OMAP3430_MUX_CTRL_SHIFT 0 619c595713dSTony Lindgren #define OMAP3430_MUX_CTRL_MASK (0x3 << 0) 620c595713dSTony Lindgren 621c595713dSTony Lindgren /* CM_CLKSTCTRL_EMU */ 622c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_EMU_SHIFT 0 623c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0) 624c595713dSTony Lindgren 625c595713dSTony Lindgren /* CM_CLKSTST_EMU */ 626c595713dSTony Lindgren #define OMAP3430_CLKACTIVITY_EMU (1 << 0) 627c595713dSTony Lindgren 628c595713dSTony Lindgren /* CM_CLKSEL2_EMU specific bits */ 629c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8 630c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8) 631c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0 632c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0) 633c595713dSTony Lindgren 634c595713dSTony Lindgren /* CM_CLKSEL3_EMU specific bits */ 635c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8 636c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8) 637c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0 638c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0) 639c595713dSTony Lindgren 640c595713dSTony Lindgren /* CM_POLCTRL */ 641c595713dSTony Lindgren #define OMAP3430_CLKOUT2_POL (1 << 0) 642c595713dSTony Lindgren 643c595713dSTony Lindgren /* CM_IDLEST_NEON */ 644c595713dSTony Lindgren #define OMAP3430_ST_NEON (1 << 0) 645c595713dSTony Lindgren 646c595713dSTony Lindgren /* CM_CLKSTCTRL_NEON */ 647c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_NEON_SHIFT 0 648c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0) 649c595713dSTony Lindgren 650c595713dSTony Lindgren /* CM_FCLKEN_USBHOST */ 651c595713dSTony Lindgren #define OMAP3430ES2_EN_USBHOST2_SHIFT 1 652c595713dSTony Lindgren #define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1) 653c595713dSTony Lindgren #define OMAP3430ES2_EN_USBHOST1_SHIFT 0 654c595713dSTony Lindgren #define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0) 655c595713dSTony Lindgren 656c595713dSTony Lindgren /* CM_ICLKEN_USBHOST */ 657c595713dSTony Lindgren #define OMAP3430ES2_EN_USBHOST_SHIFT 0 658c595713dSTony Lindgren #define OMAP3430ES2_EN_USBHOST_MASK (1 << 0) 659c595713dSTony Lindgren 660c595713dSTony Lindgren /* CM_IDLEST_USBHOST */ 661c595713dSTony Lindgren 662c595713dSTony Lindgren /* CM_AUTOIDLE_USBHOST */ 663c595713dSTony Lindgren #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 664c595713dSTony Lindgren #define OMAP3430ES2_AUTO_USBHOST_MASK (1 << 0) 665c595713dSTony Lindgren 666c595713dSTony Lindgren /* CM_SLEEPDEP_USBHOST */ 667c595713dSTony Lindgren #define OMAP3430ES2_EN_MPU_SHIFT 1 668c595713dSTony Lindgren #define OMAP3430ES2_EN_MPU_MASK (1 << 1) 669c595713dSTony Lindgren #define OMAP3430ES2_EN_IVA2_SHIFT 2 670c595713dSTony Lindgren #define OMAP3430ES2_EN_IVA2_MASK (1 << 2) 671c595713dSTony Lindgren 672c595713dSTony Lindgren /* CM_CLKSTCTRL_USBHOST */ 673c595713dSTony Lindgren #define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0 674c595713dSTony Lindgren #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0) 675c595713dSTony Lindgren 676c595713dSTony Lindgren 677c595713dSTony Lindgren 678c595713dSTony Lindgren #endif 679