1c595713dSTony Lindgren #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H 2c595713dSTony Lindgren #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H 3c595713dSTony Lindgren 4c595713dSTony Lindgren /* 5c595713dSTony Lindgren * OMAP3430 Clock Management register bits 6c595713dSTony Lindgren * 7c595713dSTony Lindgren * Copyright (C) 2007-2008 Texas Instruments, Inc. 8c595713dSTony Lindgren * Copyright (C) 2007-2008 Nokia Corporation 9c595713dSTony Lindgren * 10c595713dSTony Lindgren * Written by Paul Walmsley 11c595713dSTony Lindgren * 12c595713dSTony Lindgren * This program is free software; you can redistribute it and/or modify 13c595713dSTony Lindgren * it under the terms of the GNU General Public License version 2 as 14c595713dSTony Lindgren * published by the Free Software Foundation. 15c595713dSTony Lindgren */ 16c595713dSTony Lindgren 17c595713dSTony Lindgren /* Bits shared between registers */ 18c595713dSTony Lindgren 19c595713dSTony Lindgren /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ 20c595713dSTony Lindgren #define OMAP3430ES2_EN_MMC3_MASK (1 << 30) 21c595713dSTony Lindgren #define OMAP3430ES2_EN_MMC3_SHIFT 30 222bc4ef71SPaul Walmsley #define OMAP3430_EN_MSPRO_MASK (1 << 23) 23c595713dSTony Lindgren #define OMAP3430_EN_MSPRO_SHIFT 23 242bc4ef71SPaul Walmsley #define OMAP3430_EN_HDQ_MASK (1 << 22) 25c595713dSTony Lindgren #define OMAP3430_EN_HDQ_SHIFT 22 262bc4ef71SPaul Walmsley #define OMAP3430ES1_EN_FSHOSTUSB_MASK (1 << 5) 27c595713dSTony Lindgren #define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5 282bc4ef71SPaul Walmsley #define OMAP3430ES1_EN_D2D_MASK (1 << 3) 29c595713dSTony Lindgren #define OMAP3430ES1_EN_D2D_SHIFT 3 302bc4ef71SPaul Walmsley #define OMAP3430_EN_SSI_MASK (1 << 0) 31c595713dSTony Lindgren #define OMAP3430_EN_SSI_SHIFT 0 32c595713dSTony Lindgren 33c595713dSTony Lindgren /* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */ 34c595713dSTony Lindgren #define OMAP3430ES2_EN_USBTLL_SHIFT 2 35c595713dSTony Lindgren #define OMAP3430ES2_EN_USBTLL_MASK (1 << 2) 36c595713dSTony Lindgren 37c595713dSTony Lindgren /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ 382bc4ef71SPaul Walmsley #define OMAP3430_EN_WDT2_MASK (1 << 5) 39c595713dSTony Lindgren #define OMAP3430_EN_WDT2_SHIFT 5 40c595713dSTony Lindgren 41c595713dSTony Lindgren /* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */ 422bc4ef71SPaul Walmsley #define OMAP3430_EN_CAM_MASK (1 << 0) 43c595713dSTony Lindgren #define OMAP3430_EN_CAM_SHIFT 0 44c595713dSTony Lindgren 45c595713dSTony Lindgren /* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */ 462bc4ef71SPaul Walmsley #define OMAP3430_EN_WDT3_MASK (1 << 12) 47c595713dSTony Lindgren #define OMAP3430_EN_WDT3_SHIFT 12 48c595713dSTony Lindgren 49c595713dSTony Lindgren /* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */ 502bc4ef71SPaul Walmsley #define OMAP3430_OVERRIDE_ENABLE_MASK (1 << 19) 51c595713dSTony Lindgren 52c595713dSTony Lindgren 53c595713dSTony Lindgren /* Bits specific to each register */ 54c595713dSTony Lindgren 55c595713dSTony Lindgren /* CM_FCLKEN_IVA2 */ 56dfa6d6f8SKevin Hilman #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0) 5731c203d4SHiroshi DOYU #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0 58c595713dSTony Lindgren 59c595713dSTony Lindgren /* CM_CLKEN_PLL_IVA2 */ 60c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8 61c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8) 62c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4 63c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4) 64c595713dSTony Lindgren #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3 65c595713dSTony Lindgren #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3) 66c595713dSTony Lindgren #define OMAP3430_EN_IVA2_DPLL_SHIFT 0 67c595713dSTony Lindgren #define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0) 68c595713dSTony Lindgren 69c595713dSTony Lindgren /* CM_IDLEST_IVA2 */ 702bc4ef71SPaul Walmsley #define OMAP3430_ST_IVA2_MASK (1 << 0) 71c595713dSTony Lindgren 72c595713dSTony Lindgren /* CM_IDLEST_PLL_IVA2 */ 73542313ccSPaul Walmsley #define OMAP3430_ST_IVA2_CLK_SHIFT 0 74542313ccSPaul Walmsley #define OMAP3430_ST_IVA2_CLK_MASK (1 << 0) 75c595713dSTony Lindgren 76c595713dSTony Lindgren /* CM_AUTOIDLE_PLL_IVA2 */ 77c595713dSTony Lindgren #define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0 78c595713dSTony Lindgren #define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0) 79c595713dSTony Lindgren 80c595713dSTony Lindgren /* CM_CLKSEL1_PLL_IVA2 */ 81c595713dSTony Lindgren #define OMAP3430_IVA2_CLK_SRC_SHIFT 19 824e68f5a7SRajendra Nayak #define OMAP3430_IVA2_CLK_SRC_MASK (0x7 << 19) 83c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_MULT_SHIFT 8 84c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) 85c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_DIV_SHIFT 0 86c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0) 87c595713dSTony Lindgren 88c595713dSTony Lindgren /* CM_CLKSEL2_PLL_IVA2 */ 89c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0 90c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0) 91c595713dSTony Lindgren 92c595713dSTony Lindgren /* CM_CLKSTCTRL_IVA2 */ 93c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0 94c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0) 95c595713dSTony Lindgren 96c595713dSTony Lindgren /* CM_CLKSTST_IVA2 */ 97801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_IVA2_SHIFT 0 98801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0) 99c595713dSTony Lindgren 100c595713dSTony Lindgren /* CM_REVISION specific bits */ 101c595713dSTony Lindgren 102c595713dSTony Lindgren /* CM_SYSCONFIG specific bits */ 103c595713dSTony Lindgren 104c595713dSTony Lindgren /* CM_CLKEN_PLL_MPU */ 105c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8 106c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8) 107c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4 108c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4) 109c595713dSTony Lindgren #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3 110c595713dSTony Lindgren #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3) 111c595713dSTony Lindgren #define OMAP3430_EN_MPU_DPLL_SHIFT 0 112c595713dSTony Lindgren #define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0) 113c595713dSTony Lindgren 114c595713dSTony Lindgren /* CM_IDLEST_MPU */ 1152bc4ef71SPaul Walmsley #define OMAP3430_ST_MPU_MASK (1 << 0) 116c595713dSTony Lindgren 117c595713dSTony Lindgren /* CM_IDLEST_PLL_MPU */ 118542313ccSPaul Walmsley #define OMAP3430_ST_MPU_CLK_SHIFT 0 1193760d31fSRoman Tereshonkov #define OMAP3430_ST_MPU_CLK_MASK (1 << 0) 120c595713dSTony Lindgren 121c595713dSTony Lindgren /* CM_AUTOIDLE_PLL_MPU */ 122c595713dSTony Lindgren #define OMAP3430_AUTO_MPU_DPLL_SHIFT 0 123c595713dSTony Lindgren #define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0) 124c595713dSTony Lindgren 125c595713dSTony Lindgren /* CM_CLKSEL1_PLL_MPU */ 126c595713dSTony Lindgren #define OMAP3430_MPU_CLK_SRC_SHIFT 19 1274e68f5a7SRajendra Nayak #define OMAP3430_MPU_CLK_SRC_MASK (0x7 << 19) 128c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_MULT_SHIFT 8 129c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) 130c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_DIV_SHIFT 0 131c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0) 132c595713dSTony Lindgren 133c595713dSTony Lindgren /* CM_CLKSEL2_PLL_MPU */ 134c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0 135c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0) 136c595713dSTony Lindgren 137c595713dSTony Lindgren /* CM_CLKSTCTRL_MPU */ 138c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_MPU_SHIFT 0 139c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0) 140c595713dSTony Lindgren 141c595713dSTony Lindgren /* CM_CLKSTST_MPU */ 142801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_MPU_SHIFT 0 143801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0) 144c595713dSTony Lindgren 145c595713dSTony Lindgren /* CM_FCLKEN1_CORE specific bits */ 1462bc4ef71SPaul Walmsley #define OMAP3430_EN_MODEM_MASK (1 << 31) 1478111b221SKevin Hilman #define OMAP3430_EN_MODEM_SHIFT 31 148c595713dSTony Lindgren 149c595713dSTony Lindgren /* CM_ICLKEN1_CORE specific bits */ 1502bc4ef71SPaul Walmsley #define OMAP3430_EN_ICR_MASK (1 << 29) 151c595713dSTony Lindgren #define OMAP3430_EN_ICR_SHIFT 29 1522bc4ef71SPaul Walmsley #define OMAP3430_EN_AES2_MASK (1 << 28) 153c595713dSTony Lindgren #define OMAP3430_EN_AES2_SHIFT 28 1542bc4ef71SPaul Walmsley #define OMAP3430_EN_SHA12_MASK (1 << 27) 155c595713dSTony Lindgren #define OMAP3430_EN_SHA12_SHIFT 27 1562bc4ef71SPaul Walmsley #define OMAP3430_EN_DES2_MASK (1 << 26) 157c595713dSTony Lindgren #define OMAP3430_EN_DES2_SHIFT 26 1582bc4ef71SPaul Walmsley #define OMAP3430ES1_EN_FAC_MASK (1 << 8) 159c595713dSTony Lindgren #define OMAP3430ES1_EN_FAC_SHIFT 8 1602bc4ef71SPaul Walmsley #define OMAP3430_EN_MAILBOXES_MASK (1 << 7) 161c595713dSTony Lindgren #define OMAP3430_EN_MAILBOXES_SHIFT 7 1622bc4ef71SPaul Walmsley #define OMAP3430_EN_OMAPCTRL_MASK (1 << 6) 163c595713dSTony Lindgren #define OMAP3430_EN_OMAPCTRL_SHIFT 6 1642bc4ef71SPaul Walmsley #define OMAP3430_EN_SAD2D_MASK (1 << 3) 1658111b221SKevin Hilman #define OMAP3430_EN_SAD2D_SHIFT 3 1662bc4ef71SPaul Walmsley #define OMAP3430_EN_SDRC_MASK (1 << 1) 167c595713dSTony Lindgren #define OMAP3430_EN_SDRC_SHIFT 1 168c595713dSTony Lindgren 1693cc4a2fcSRanjith Lohithakshan /* AM35XX specific CM_ICLKEN1_CORE bits */ 1703cc4a2fcSRanjith Lohithakshan #define AM35XX_EN_IPSS_MASK (1 << 4) 1713cc4a2fcSRanjith Lohithakshan #define AM35XX_EN_IPSS_SHIFT 4 1723cc4a2fcSRanjith Lohithakshan #define AM35XX_EN_UART4_MASK (1 << 23) 1733cc4a2fcSRanjith Lohithakshan #define AM35XX_EN_UART4_SHIFT 23 1743cc4a2fcSRanjith Lohithakshan 175c595713dSTony Lindgren /* CM_ICLKEN2_CORE */ 1762bc4ef71SPaul Walmsley #define OMAP3430_EN_PKA_MASK (1 << 4) 177c595713dSTony Lindgren #define OMAP3430_EN_PKA_SHIFT 4 1782bc4ef71SPaul Walmsley #define OMAP3430_EN_AES1_MASK (1 << 3) 179c595713dSTony Lindgren #define OMAP3430_EN_AES1_SHIFT 3 1802bc4ef71SPaul Walmsley #define OMAP3430_EN_RNG_MASK (1 << 2) 181c595713dSTony Lindgren #define OMAP3430_EN_RNG_SHIFT 2 1822bc4ef71SPaul Walmsley #define OMAP3430_EN_SHA11_MASK (1 << 1) 183c595713dSTony Lindgren #define OMAP3430_EN_SHA11_SHIFT 1 1842bc4ef71SPaul Walmsley #define OMAP3430_EN_DES1_MASK (1 << 0) 185c595713dSTony Lindgren #define OMAP3430_EN_DES1_SHIFT 0 186c595713dSTony Lindgren 1878111b221SKevin Hilman /* CM_ICLKEN3_CORE */ 1888111b221SKevin Hilman #define OMAP3430_EN_MAD2D_SHIFT 3 1892bc4ef71SPaul Walmsley #define OMAP3430_EN_MAD2D_MASK (1 << 3) 1908111b221SKevin Hilman 191c595713dSTony Lindgren /* CM_FCLKEN3_CORE specific bits */ 192c595713dSTony Lindgren #define OMAP3430ES2_EN_TS_SHIFT 1 193c595713dSTony Lindgren #define OMAP3430ES2_EN_TS_MASK (1 << 1) 194c595713dSTony Lindgren #define OMAP3430ES2_EN_CPEFUSE_SHIFT 0 195c595713dSTony Lindgren #define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0) 196c595713dSTony Lindgren 197c595713dSTony Lindgren /* CM_IDLEST1_CORE specific bits */ 198da0747d4SPaul Walmsley #define OMAP3430ES2_ST_MMC3_SHIFT 30 199da0747d4SPaul Walmsley #define OMAP3430ES2_ST_MMC3_MASK (1 << 30) 200da0747d4SPaul Walmsley #define OMAP3430_ST_ICR_SHIFT 29 201da0747d4SPaul Walmsley #define OMAP3430_ST_ICR_MASK (1 << 29) 202da0747d4SPaul Walmsley #define OMAP3430_ST_AES2_SHIFT 28 203da0747d4SPaul Walmsley #define OMAP3430_ST_AES2_MASK (1 << 28) 204da0747d4SPaul Walmsley #define OMAP3430_ST_SHA12_SHIFT 27 205da0747d4SPaul Walmsley #define OMAP3430_ST_SHA12_MASK (1 << 27) 206da0747d4SPaul Walmsley #define OMAP3430_ST_DES2_SHIFT 26 207da0747d4SPaul Walmsley #define OMAP3430_ST_DES2_MASK (1 << 26) 208da0747d4SPaul Walmsley #define OMAP3430_ST_MSPRO_SHIFT 23 209da0747d4SPaul Walmsley #define OMAP3430_ST_MSPRO_MASK (1 << 23) 210da0747d4SPaul Walmsley #define OMAP3430_ST_HDQ_SHIFT 22 211da0747d4SPaul Walmsley #define OMAP3430_ST_HDQ_MASK (1 << 22) 212da0747d4SPaul Walmsley #define OMAP3430ES1_ST_FAC_SHIFT 8 213da0747d4SPaul Walmsley #define OMAP3430ES1_ST_FAC_MASK (1 << 8) 214da0747d4SPaul Walmsley #define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8 215da0747d4SPaul Walmsley #define OMAP3430ES2_ST_SSI_IDLE_MASK (1 << 8) 216da0747d4SPaul Walmsley #define OMAP3430_ST_MAILBOXES_SHIFT 7 217da0747d4SPaul Walmsley #define OMAP3430_ST_MAILBOXES_MASK (1 << 7) 218da0747d4SPaul Walmsley #define OMAP3430_ST_OMAPCTRL_SHIFT 6 219da0747d4SPaul Walmsley #define OMAP3430_ST_OMAPCTRL_MASK (1 << 6) 220da0747d4SPaul Walmsley #define OMAP3430_ST_SDMA_SHIFT 2 221da0747d4SPaul Walmsley #define OMAP3430_ST_SDMA_MASK (1 << 2) 222da0747d4SPaul Walmsley #define OMAP3430_ST_SDRC_SHIFT 1 223da0747d4SPaul Walmsley #define OMAP3430_ST_SDRC_MASK (1 << 1) 224da0747d4SPaul Walmsley #define OMAP3430_ST_SSI_STDBY_SHIFT 0 225da0747d4SPaul Walmsley #define OMAP3430_ST_SSI_STDBY_MASK (1 << 0) 226c595713dSTony Lindgren 2273cc4a2fcSRanjith Lohithakshan /* AM35xx specific CM_IDLEST1_CORE bits */ 2283cc4a2fcSRanjith Lohithakshan #define AM35XX_ST_IPSS_SHIFT 5 2293cc4a2fcSRanjith Lohithakshan #define AM35XX_ST_IPSS_MASK (1 << 5) 2303cc4a2fcSRanjith Lohithakshan 231c595713dSTony Lindgren /* CM_IDLEST2_CORE */ 232da0747d4SPaul Walmsley #define OMAP3430_ST_PKA_SHIFT 4 233da0747d4SPaul Walmsley #define OMAP3430_ST_PKA_MASK (1 << 4) 234da0747d4SPaul Walmsley #define OMAP3430_ST_AES1_SHIFT 3 235da0747d4SPaul Walmsley #define OMAP3430_ST_AES1_MASK (1 << 3) 236da0747d4SPaul Walmsley #define OMAP3430_ST_RNG_SHIFT 2 237da0747d4SPaul Walmsley #define OMAP3430_ST_RNG_MASK (1 << 2) 238da0747d4SPaul Walmsley #define OMAP3430_ST_SHA11_SHIFT 1 239da0747d4SPaul Walmsley #define OMAP3430_ST_SHA11_MASK (1 << 1) 240da0747d4SPaul Walmsley #define OMAP3430_ST_DES1_SHIFT 0 241da0747d4SPaul Walmsley #define OMAP3430_ST_DES1_MASK (1 << 0) 242c595713dSTony Lindgren 243c595713dSTony Lindgren /* CM_IDLEST3_CORE */ 244c595713dSTony Lindgren #define OMAP3430ES2_ST_USBTLL_SHIFT 2 245c595713dSTony Lindgren #define OMAP3430ES2_ST_USBTLL_MASK (1 << 2) 246da0747d4SPaul Walmsley #define OMAP3430ES2_ST_CPEFUSE_SHIFT 0 247da0747d4SPaul Walmsley #define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0) 248c595713dSTony Lindgren 249c595713dSTony Lindgren /* CM_AUTOIDLE1_CORE */ 2502bc4ef71SPaul Walmsley #define OMAP3430_AUTO_MODEM_MASK (1 << 31) 2518111b221SKevin Hilman #define OMAP3430_AUTO_MODEM_SHIFT 31 2522bc4ef71SPaul Walmsley #define OMAP3430ES2_AUTO_MMC3_MASK (1 << 30) 253027d8dedSJouni Hogander #define OMAP3430ES2_AUTO_MMC3_SHIFT 30 2542bc4ef71SPaul Walmsley #define OMAP3430ES2_AUTO_ICR_MASK (1 << 29) 255027d8dedSJouni Hogander #define OMAP3430ES2_AUTO_ICR_SHIFT 29 2562bc4ef71SPaul Walmsley #define OMAP3430_AUTO_AES2_MASK (1 << 28) 257c595713dSTony Lindgren #define OMAP3430_AUTO_AES2_SHIFT 28 2582bc4ef71SPaul Walmsley #define OMAP3430_AUTO_SHA12_MASK (1 << 27) 259c595713dSTony Lindgren #define OMAP3430_AUTO_SHA12_SHIFT 27 2602bc4ef71SPaul Walmsley #define OMAP3430_AUTO_DES2_MASK (1 << 26) 261c595713dSTony Lindgren #define OMAP3430_AUTO_DES2_SHIFT 26 2622bc4ef71SPaul Walmsley #define OMAP3430_AUTO_MMC2_MASK (1 << 25) 263c595713dSTony Lindgren #define OMAP3430_AUTO_MMC2_SHIFT 25 2642bc4ef71SPaul Walmsley #define OMAP3430_AUTO_MMC1_MASK (1 << 24) 265c595713dSTony Lindgren #define OMAP3430_AUTO_MMC1_SHIFT 24 2662bc4ef71SPaul Walmsley #define OMAP3430_AUTO_MSPRO_MASK (1 << 23) 267c595713dSTony Lindgren #define OMAP3430_AUTO_MSPRO_SHIFT 23 2682bc4ef71SPaul Walmsley #define OMAP3430_AUTO_HDQ_MASK (1 << 22) 269c595713dSTony Lindgren #define OMAP3430_AUTO_HDQ_SHIFT 22 2702bc4ef71SPaul Walmsley #define OMAP3430_AUTO_MCSPI4_MASK (1 << 21) 271c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI4_SHIFT 21 2722bc4ef71SPaul Walmsley #define OMAP3430_AUTO_MCSPI3_MASK (1 << 20) 273c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI3_SHIFT 20 2742bc4ef71SPaul Walmsley #define OMAP3430_AUTO_MCSPI2_MASK (1 << 19) 275c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI2_SHIFT 19 2762bc4ef71SPaul Walmsley #define OMAP3430_AUTO_MCSPI1_MASK (1 << 18) 277c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI1_SHIFT 18 2782bc4ef71SPaul Walmsley #define OMAP3430_AUTO_I2C3_MASK (1 << 17) 279c595713dSTony Lindgren #define OMAP3430_AUTO_I2C3_SHIFT 17 2802bc4ef71SPaul Walmsley #define OMAP3430_AUTO_I2C2_MASK (1 << 16) 281c595713dSTony Lindgren #define OMAP3430_AUTO_I2C2_SHIFT 16 2822bc4ef71SPaul Walmsley #define OMAP3430_AUTO_I2C1_MASK (1 << 15) 283c595713dSTony Lindgren #define OMAP3430_AUTO_I2C1_SHIFT 15 2842bc4ef71SPaul Walmsley #define OMAP3430_AUTO_UART2_MASK (1 << 14) 285c595713dSTony Lindgren #define OMAP3430_AUTO_UART2_SHIFT 14 2862bc4ef71SPaul Walmsley #define OMAP3430_AUTO_UART1_MASK (1 << 13) 287c595713dSTony Lindgren #define OMAP3430_AUTO_UART1_SHIFT 13 2882bc4ef71SPaul Walmsley #define OMAP3430_AUTO_GPT11_MASK (1 << 12) 289c595713dSTony Lindgren #define OMAP3430_AUTO_GPT11_SHIFT 12 2902bc4ef71SPaul Walmsley #define OMAP3430_AUTO_GPT10_MASK (1 << 11) 291c595713dSTony Lindgren #define OMAP3430_AUTO_GPT10_SHIFT 11 2922bc4ef71SPaul Walmsley #define OMAP3430_AUTO_MCBSP5_MASK (1 << 10) 293c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP5_SHIFT 10 2942bc4ef71SPaul Walmsley #define OMAP3430_AUTO_MCBSP1_MASK (1 << 9) 295c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP1_SHIFT 9 2962bc4ef71SPaul Walmsley #define OMAP3430ES1_AUTO_FAC_MASK (1 << 8) 297c595713dSTony Lindgren #define OMAP3430ES1_AUTO_FAC_SHIFT 8 2982bc4ef71SPaul Walmsley #define OMAP3430_AUTO_MAILBOXES_MASK (1 << 7) 299c595713dSTony Lindgren #define OMAP3430_AUTO_MAILBOXES_SHIFT 7 3002bc4ef71SPaul Walmsley #define OMAP3430_AUTO_OMAPCTRL_MASK (1 << 6) 301c595713dSTony Lindgren #define OMAP3430_AUTO_OMAPCTRL_SHIFT 6 3022bc4ef71SPaul Walmsley #define OMAP3430ES1_AUTO_FSHOSTUSB_MASK (1 << 5) 303c595713dSTony Lindgren #define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5 3042bc4ef71SPaul Walmsley #define OMAP3430_AUTO_HSOTGUSB_MASK (1 << 4) 305c595713dSTony Lindgren #define OMAP3430_AUTO_HSOTGUSB_SHIFT 4 3062bc4ef71SPaul Walmsley #define OMAP3430ES1_AUTO_D2D_MASK (1 << 3) 307c595713dSTony Lindgren #define OMAP3430ES1_AUTO_D2D_SHIFT 3 3082bc4ef71SPaul Walmsley #define OMAP3430_AUTO_SAD2D_MASK (1 << 3) 3098111b221SKevin Hilman #define OMAP3430_AUTO_SAD2D_SHIFT 3 3102bc4ef71SPaul Walmsley #define OMAP3430_AUTO_SSI_MASK (1 << 0) 311c595713dSTony Lindgren #define OMAP3430_AUTO_SSI_SHIFT 0 312c595713dSTony Lindgren 313c595713dSTony Lindgren /* CM_AUTOIDLE2_CORE */ 3142bc4ef71SPaul Walmsley #define OMAP3430_AUTO_PKA_MASK (1 << 4) 315c595713dSTony Lindgren #define OMAP3430_AUTO_PKA_SHIFT 4 3162bc4ef71SPaul Walmsley #define OMAP3430_AUTO_AES1_MASK (1 << 3) 317c595713dSTony Lindgren #define OMAP3430_AUTO_AES1_SHIFT 3 3182bc4ef71SPaul Walmsley #define OMAP3430_AUTO_RNG_MASK (1 << 2) 319c595713dSTony Lindgren #define OMAP3430_AUTO_RNG_SHIFT 2 3202bc4ef71SPaul Walmsley #define OMAP3430_AUTO_SHA11_MASK (1 << 1) 321c595713dSTony Lindgren #define OMAP3430_AUTO_SHA11_SHIFT 1 3222bc4ef71SPaul Walmsley #define OMAP3430_AUTO_DES1_MASK (1 << 0) 323c595713dSTony Lindgren #define OMAP3430_AUTO_DES1_SHIFT 0 324c595713dSTony Lindgren 325c595713dSTony Lindgren /* CM_AUTOIDLE3_CORE */ 326027d8dedSJouni Hogander #define OMAP3430ES2_AUTO_USBHOST (1 << 0) 327027d8dedSJouni Hogander #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 328027d8dedSJouni Hogander #define OMAP3430ES2_AUTO_USBTLL (1 << 2) 329c595713dSTony Lindgren #define OMAP3430ES2_AUTO_USBTLL_SHIFT 2 330c595713dSTony Lindgren #define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2) 3318111b221SKevin Hilman #define OMAP3430_AUTO_MAD2D_SHIFT 3 3322bc4ef71SPaul Walmsley #define OMAP3430_AUTO_MAD2D_MASK (1 << 3) 333c595713dSTony Lindgren 334c595713dSTony Lindgren /* CM_CLKSEL_CORE */ 335c595713dSTony Lindgren #define OMAP3430_CLKSEL_SSI_SHIFT 8 336c595713dSTony Lindgren #define OMAP3430_CLKSEL_SSI_MASK (0xf << 8) 337c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT11_MASK (1 << 7) 338c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT11_SHIFT 7 339c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT10_MASK (1 << 6) 340c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT10_SHIFT 6 341c595713dSTony Lindgren #define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4 342c595713dSTony Lindgren #define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4) 343c595713dSTony Lindgren #define OMAP3430_CLKSEL_L4_SHIFT 2 344c595713dSTony Lindgren #define OMAP3430_CLKSEL_L4_MASK (0x3 << 2) 345c595713dSTony Lindgren #define OMAP3430_CLKSEL_L3_SHIFT 0 346c595713dSTony Lindgren #define OMAP3430_CLKSEL_L3_MASK (0x3 << 0) 3477356f0b2SVishwanath BS #define OMAP3630_CLKSEL_96M_SHIFT 12 3487356f0b2SVishwanath BS #define OMAP3630_CLKSEL_96M_MASK (0x3 << 12) 349c595713dSTony Lindgren 350c595713dSTony Lindgren /* CM_CLKSTCTRL_CORE */ 351c595713dSTony Lindgren #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4 352c595713dSTony Lindgren #define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4) 353c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_L4_SHIFT 2 354c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2) 355c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_L3_SHIFT 0 356c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0) 357c595713dSTony Lindgren 358c595713dSTony Lindgren /* CM_CLKSTST_CORE */ 359801954d3SPaul Walmsley #define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT 2 360801954d3SPaul Walmsley #define OMAP3430ES1_CLKACTIVITY_D2D_MASK (1 << 2) 361801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_L4_SHIFT 1 362801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_L4_MASK (1 << 1) 363801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_L3_SHIFT 0 364801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0) 365c595713dSTony Lindgren 366c595713dSTony Lindgren /* CM_FCLKEN_GFX */ 3672bc4ef71SPaul Walmsley #define OMAP3430ES1_EN_3D_MASK (1 << 2) 368c595713dSTony Lindgren #define OMAP3430ES1_EN_3D_SHIFT 2 3692bc4ef71SPaul Walmsley #define OMAP3430ES1_EN_2D_MASK (1 << 1) 370c595713dSTony Lindgren #define OMAP3430ES1_EN_2D_SHIFT 1 371c595713dSTony Lindgren 372c595713dSTony Lindgren /* CM_ICLKEN_GFX specific bits */ 373c595713dSTony Lindgren 374c595713dSTony Lindgren /* CM_IDLEST_GFX specific bits */ 375c595713dSTony Lindgren 376c595713dSTony Lindgren /* CM_CLKSEL_GFX specific bits */ 377c595713dSTony Lindgren 378c595713dSTony Lindgren /* CM_SLEEPDEP_GFX specific bits */ 379c595713dSTony Lindgren 380c595713dSTony Lindgren /* CM_CLKSTCTRL_GFX */ 381c595713dSTony Lindgren #define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0 382c595713dSTony Lindgren #define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0) 383c595713dSTony Lindgren 384c595713dSTony Lindgren /* CM_CLKSTST_GFX */ 385801954d3SPaul Walmsley #define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT 0 386801954d3SPaul Walmsley #define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0) 387c595713dSTony Lindgren 388c595713dSTony Lindgren /* CM_FCLKEN_SGX */ 389712d7c86SDaniel Stone #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1 390712d7c86SDaniel Stone #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1) 391712d7c86SDaniel Stone 392b024b542STero Kristo /* CM_IDLEST_SGX */ 393b024b542STero Kristo #define OMAP3430ES2_ST_SGX_SHIFT 1 394b024b542STero Kristo #define OMAP3430ES2_ST_SGX_MASK (1 << 1) 395b024b542STero Kristo 396712d7c86SDaniel Stone /* CM_ICLKEN_SGX */ 397712d7c86SDaniel Stone #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0 398712d7c86SDaniel Stone #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0) 399c595713dSTony Lindgren 400c595713dSTony Lindgren /* CM_CLKSEL_SGX */ 401c595713dSTony Lindgren #define OMAP3430ES2_CLKSEL_SGX_SHIFT 0 402c595713dSTony Lindgren #define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0) 403c595713dSTony Lindgren 404801954d3SPaul Walmsley /* CM_CLKSTCTRL_SGX */ 405801954d3SPaul Walmsley #define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT 0 406801954d3SPaul Walmsley #define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0) 407801954d3SPaul Walmsley 408801954d3SPaul Walmsley /* CM_CLKSTST_SGX */ 409801954d3SPaul Walmsley #define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT 0 410801954d3SPaul Walmsley #define OMAP3430ES2_CLKACTIVITY_SGX_MASK (1 << 0) 411801954d3SPaul Walmsley 412c595713dSTony Lindgren /* CM_FCLKEN_WKUP specific bits */ 413c595713dSTony Lindgren #define OMAP3430ES2_EN_USIMOCP_SHIFT 9 414da0747d4SPaul Walmsley #define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9) 415c595713dSTony Lindgren 416c595713dSTony Lindgren /* CM_ICLKEN_WKUP specific bits */ 4172bc4ef71SPaul Walmsley #define OMAP3430_EN_WDT1_MASK (1 << 4) 418c595713dSTony Lindgren #define OMAP3430_EN_WDT1_SHIFT 4 4192bc4ef71SPaul Walmsley #define OMAP3430_EN_32KSYNC_MASK (1 << 2) 420c595713dSTony Lindgren #define OMAP3430_EN_32KSYNC_SHIFT 2 421c595713dSTony Lindgren 422c595713dSTony Lindgren /* CM_IDLEST_WKUP specific bits */ 423da0747d4SPaul Walmsley #define OMAP3430ES2_ST_USIMOCP_SHIFT 9 424da0747d4SPaul Walmsley #define OMAP3430ES2_ST_USIMOCP_MASK (1 << 9) 425da0747d4SPaul Walmsley #define OMAP3430_ST_WDT2_SHIFT 5 426da0747d4SPaul Walmsley #define OMAP3430_ST_WDT2_MASK (1 << 5) 427da0747d4SPaul Walmsley #define OMAP3430_ST_WDT1_SHIFT 4 428da0747d4SPaul Walmsley #define OMAP3430_ST_WDT1_MASK (1 << 4) 429da0747d4SPaul Walmsley #define OMAP3430_ST_32KSYNC_SHIFT 2 430da0747d4SPaul Walmsley #define OMAP3430_ST_32KSYNC_MASK (1 << 2) 431c595713dSTony Lindgren 432c595713dSTony Lindgren /* CM_AUTOIDLE_WKUP */ 4332bc4ef71SPaul Walmsley #define OMAP3430ES2_AUTO_USIMOCP_MASK (1 << 9) 434da0747d4SPaul Walmsley #define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9 4352bc4ef71SPaul Walmsley #define OMAP3430_AUTO_WDT2_MASK (1 << 5) 436c595713dSTony Lindgren #define OMAP3430_AUTO_WDT2_SHIFT 5 4372bc4ef71SPaul Walmsley #define OMAP3430_AUTO_WDT1_MASK (1 << 4) 438c595713dSTony Lindgren #define OMAP3430_AUTO_WDT1_SHIFT 4 4392bc4ef71SPaul Walmsley #define OMAP3430_AUTO_GPIO1_MASK (1 << 3) 440c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO1_SHIFT 3 4412bc4ef71SPaul Walmsley #define OMAP3430_AUTO_32KSYNC_MASK (1 << 2) 442c595713dSTony Lindgren #define OMAP3430_AUTO_32KSYNC_SHIFT 2 4432bc4ef71SPaul Walmsley #define OMAP3430_AUTO_GPT12_MASK (1 << 1) 444c595713dSTony Lindgren #define OMAP3430_AUTO_GPT12_SHIFT 1 4452bc4ef71SPaul Walmsley #define OMAP3430_AUTO_GPT1_MASK (1 << 0) 446c595713dSTony Lindgren #define OMAP3430_AUTO_GPT1_SHIFT 0 447c595713dSTony Lindgren 448c595713dSTony Lindgren /* CM_CLKSEL_WKUP */ 449c595713dSTony Lindgren #define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3) 450c595713dSTony Lindgren #define OMAP3430_CLKSEL_RM_SHIFT 1 451c595713dSTony Lindgren #define OMAP3430_CLKSEL_RM_MASK (0x3 << 1) 452c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT1_SHIFT 0 453c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT1_MASK (1 << 0) 454c595713dSTony Lindgren 455c595713dSTony Lindgren /* CM_CLKEN_PLL */ 456c595713dSTony Lindgren #define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31 457c595713dSTony Lindgren #define OMAP3430_PWRDN_CAM_SHIFT 30 458c595713dSTony Lindgren #define OMAP3430_PWRDN_DSS1_SHIFT 29 459c595713dSTony Lindgren #define OMAP3430_PWRDN_TV_SHIFT 28 460c595713dSTony Lindgren #define OMAP3430_PWRDN_96M_SHIFT 27 461c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24 462c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24) 463c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20 464c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20) 465c595713dSTony Lindgren #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19 466c595713dSTony Lindgren #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19) 467c595713dSTony Lindgren #define OMAP3430_EN_PERIPH_DPLL_SHIFT 16 468c595713dSTony Lindgren #define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16) 469c595713dSTony Lindgren #define OMAP3430_PWRDN_EMU_CORE_SHIFT 12 470c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8 471c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8) 472c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4 473c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4) 474c595713dSTony Lindgren #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3 475c595713dSTony Lindgren #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3) 476c595713dSTony Lindgren #define OMAP3430_EN_CORE_DPLL_SHIFT 0 477c595713dSTony Lindgren #define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0) 478c595713dSTony Lindgren 479c595713dSTony Lindgren /* CM_CLKEN2_PLL */ 480c595713dSTony Lindgren #define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10 481c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8) 482c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4 483c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4) 484c595713dSTony Lindgren #define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3 485c595713dSTony Lindgren #define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0 486c595713dSTony Lindgren #define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0) 487c595713dSTony Lindgren 488c595713dSTony Lindgren /* CM_IDLEST_CKGEN */ 4892bc4ef71SPaul Walmsley #define OMAP3430_ST_54M_CLK_MASK (1 << 5) 4902bc4ef71SPaul Walmsley #define OMAP3430_ST_12M_CLK_MASK (1 << 4) 4912bc4ef71SPaul Walmsley #define OMAP3430_ST_48M_CLK_MASK (1 << 3) 4922bc4ef71SPaul Walmsley #define OMAP3430_ST_96M_CLK_MASK (1 << 2) 493542313ccSPaul Walmsley #define OMAP3430_ST_PERIPH_CLK_SHIFT 1 494542313ccSPaul Walmsley #define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1) 495542313ccSPaul Walmsley #define OMAP3430_ST_CORE_CLK_SHIFT 0 496542313ccSPaul Walmsley #define OMAP3430_ST_CORE_CLK_MASK (1 << 0) 497c595713dSTony Lindgren 498c595713dSTony Lindgren /* CM_IDLEST2_CKGEN */ 499da0747d4SPaul Walmsley #define OMAP3430ES2_ST_USIM_CLK_SHIFT 2 500da0747d4SPaul Walmsley #define OMAP3430ES2_ST_USIM_CLK_MASK (1 << 2) 501c595713dSTony Lindgren #define OMAP3430ES2_ST_120M_CLK_SHIFT 1 502c595713dSTony Lindgren #define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1) 503c595713dSTony Lindgren #define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0 504c595713dSTony Lindgren #define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0) 505c595713dSTony Lindgren 506c595713dSTony Lindgren /* CM_AUTOIDLE_PLL */ 507c595713dSTony Lindgren #define OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3 508c595713dSTony Lindgren #define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3) 509c595713dSTony Lindgren #define OMAP3430_AUTO_CORE_DPLL_SHIFT 0 510c595713dSTony Lindgren #define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0) 511c595713dSTony Lindgren 512542313ccSPaul Walmsley /* CM_AUTOIDLE2_PLL */ 513542313ccSPaul Walmsley #define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT 0 514542313ccSPaul Walmsley #define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0) 515542313ccSPaul Walmsley 516c595713dSTony Lindgren /* CM_CLKSEL1_PLL */ 517c595713dSTony Lindgren /* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */ 518c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27 519c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27) 520c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_MULT_SHIFT 16 521c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) 522c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_DIV_SHIFT 8 523c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8) 5249cfd985eSPaul Walmsley #define OMAP3430_SOURCE_96M_SHIFT 6 5259cfd985eSPaul Walmsley #define OMAP3430_SOURCE_96M_MASK (1 << 6) 5269cfd985eSPaul Walmsley #define OMAP3430_SOURCE_54M_SHIFT 5 5279cfd985eSPaul Walmsley #define OMAP3430_SOURCE_54M_MASK (1 << 5) 5289cfd985eSPaul Walmsley #define OMAP3430_SOURCE_48M_SHIFT 3 5299cfd985eSPaul Walmsley #define OMAP3430_SOURCE_48M_MASK (1 << 3) 530c595713dSTony Lindgren 531c595713dSTony Lindgren /* CM_CLKSEL2_PLL */ 532c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8 533c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8) 534358965d7SRichard Woodruff #define OMAP3630_PERIPH_DPLL_MULT_MASK (0xfff << 8) 535c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0 536c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0) 537358965d7SRichard Woodruff #define OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT 21 538358965d7SRichard Woodruff #define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK (0x7 << 21) 539358965d7SRichard Woodruff #define OMAP3630_PERIPH_DPLL_SD_DIV_SHIFT 24 540358965d7SRichard Woodruff #define OMAP3630_PERIPH_DPLL_SD_DIV_MASK (0xff << 24) 541c595713dSTony Lindgren 542c595713dSTony Lindgren /* CM_CLKSEL3_PLL */ 543c595713dSTony Lindgren #define OMAP3430_DIV_96M_SHIFT 0 544c595713dSTony Lindgren #define OMAP3430_DIV_96M_MASK (0x1f << 0) 545678bc9a2SVishwanath BS #define OMAP3630_DIV_96M_MASK (0x3f << 0) 546c595713dSTony Lindgren 547c595713dSTony Lindgren /* CM_CLKSEL4_PLL */ 548c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8 549c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8) 550c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0 551c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0) 552c595713dSTony Lindgren 553c595713dSTony Lindgren /* CM_CLKSEL5_PLL */ 554c595713dSTony Lindgren #define OMAP3430ES2_DIV_120M_SHIFT 0 555c595713dSTony Lindgren #define OMAP3430ES2_DIV_120M_MASK (0x1f << 0) 556c595713dSTony Lindgren 557c595713dSTony Lindgren /* CM_CLKOUT_CTRL */ 558c595713dSTony Lindgren #define OMAP3430_CLKOUT2_EN_SHIFT 7 5592bc4ef71SPaul Walmsley #define OMAP3430_CLKOUT2_EN_MASK (1 << 7) 560c595713dSTony Lindgren #define OMAP3430_CLKOUT2_DIV_SHIFT 3 561c595713dSTony Lindgren #define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3) 562c595713dSTony Lindgren #define OMAP3430_CLKOUT2SOURCE_SHIFT 0 563c595713dSTony Lindgren #define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0) 564c595713dSTony Lindgren 565c595713dSTony Lindgren /* CM_FCLKEN_DSS */ 5662bc4ef71SPaul Walmsley #define OMAP3430_EN_TV_MASK (1 << 2) 567c595713dSTony Lindgren #define OMAP3430_EN_TV_SHIFT 2 5682bc4ef71SPaul Walmsley #define OMAP3430_EN_DSS2_MASK (1 << 1) 569c595713dSTony Lindgren #define OMAP3430_EN_DSS2_SHIFT 1 5702bc4ef71SPaul Walmsley #define OMAP3430_EN_DSS1_MASK (1 << 0) 571c595713dSTony Lindgren #define OMAP3430_EN_DSS1_SHIFT 0 572c595713dSTony Lindgren 573c595713dSTony Lindgren /* CM_ICLKEN_DSS */ 5742bc4ef71SPaul Walmsley #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_MASK (1 << 0) 575c595713dSTony Lindgren #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 576c595713dSTony Lindgren 577c595713dSTony Lindgren /* CM_IDLEST_DSS */ 578da0747d4SPaul Walmsley #define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1 579da0747d4SPaul Walmsley #define OMAP3430ES2_ST_DSS_IDLE_MASK (1 << 1) 580da0747d4SPaul Walmsley #define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0 581da0747d4SPaul Walmsley #define OMAP3430ES2_ST_DSS_STDBY_MASK (1 << 0) 582da0747d4SPaul Walmsley #define OMAP3430ES1_ST_DSS_SHIFT 0 583da0747d4SPaul Walmsley #define OMAP3430ES1_ST_DSS_MASK (1 << 0) 584c595713dSTony Lindgren 585c595713dSTony Lindgren /* CM_AUTOIDLE_DSS */ 5862bc4ef71SPaul Walmsley #define OMAP3430_AUTO_DSS_MASK (1 << 0) 587c595713dSTony Lindgren #define OMAP3430_AUTO_DSS_SHIFT 0 588c595713dSTony Lindgren 589c595713dSTony Lindgren /* CM_CLKSEL_DSS */ 590c595713dSTony Lindgren #define OMAP3430_CLKSEL_TV_SHIFT 8 591c595713dSTony Lindgren #define OMAP3430_CLKSEL_TV_MASK (0x1f << 8) 592678bc9a2SVishwanath BS #define OMAP3630_CLKSEL_TV_MASK (0x3f << 8) 593c595713dSTony Lindgren #define OMAP3430_CLKSEL_DSS1_SHIFT 0 594c595713dSTony Lindgren #define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0) 595678bc9a2SVishwanath BS #define OMAP3630_CLKSEL_DSS1_MASK (0x3f << 0) 596c595713dSTony Lindgren 597c595713dSTony Lindgren /* CM_SLEEPDEP_DSS specific bits */ 598c595713dSTony Lindgren 599c595713dSTony Lindgren /* CM_CLKSTCTRL_DSS */ 600c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_DSS_SHIFT 0 601c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0) 602c595713dSTony Lindgren 603c595713dSTony Lindgren /* CM_CLKSTST_DSS */ 604801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_DSS_SHIFT 0 605801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0) 606c595713dSTony Lindgren 607c595713dSTony Lindgren /* CM_FCLKEN_CAM specific bits */ 6082bc4ef71SPaul Walmsley #define OMAP3430_EN_CSI2_MASK (1 << 1) 6096c8fe0b9SSergio Aguirre #define OMAP3430_EN_CSI2_SHIFT 1 610c595713dSTony Lindgren 611c595713dSTony Lindgren /* CM_ICLKEN_CAM specific bits */ 612c595713dSTony Lindgren 613c595713dSTony Lindgren /* CM_IDLEST_CAM */ 6142bc4ef71SPaul Walmsley #define OMAP3430_ST_CAM_MASK (1 << 0) 615c595713dSTony Lindgren 616c595713dSTony Lindgren /* CM_AUTOIDLE_CAM */ 6172bc4ef71SPaul Walmsley #define OMAP3430_AUTO_CAM_MASK (1 << 0) 618c595713dSTony Lindgren #define OMAP3430_AUTO_CAM_SHIFT 0 619c595713dSTony Lindgren 620c595713dSTony Lindgren /* CM_CLKSEL_CAM */ 621c595713dSTony Lindgren #define OMAP3430_CLKSEL_CAM_SHIFT 0 622c595713dSTony Lindgren #define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0) 623678bc9a2SVishwanath BS #define OMAP3630_CLKSEL_CAM_MASK (0x3f << 0) 624c595713dSTony Lindgren 625c595713dSTony Lindgren /* CM_SLEEPDEP_CAM specific bits */ 626c595713dSTony Lindgren 627c595713dSTony Lindgren /* CM_CLKSTCTRL_CAM */ 628c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_CAM_SHIFT 0 629c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0) 630c595713dSTony Lindgren 631c595713dSTony Lindgren /* CM_CLKSTST_CAM */ 632801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_CAM_SHIFT 0 633801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_CAM_MASK (1 << 0) 634c595713dSTony Lindgren 635c595713dSTony Lindgren /* CM_FCLKEN_PER specific bits */ 636c595713dSTony Lindgren 637c595713dSTony Lindgren /* CM_ICLKEN_PER specific bits */ 638c595713dSTony Lindgren 639c595713dSTony Lindgren /* CM_IDLEST_PER */ 640da0747d4SPaul Walmsley #define OMAP3430_ST_WDT3_SHIFT 12 641da0747d4SPaul Walmsley #define OMAP3430_ST_WDT3_MASK (1 << 12) 642da0747d4SPaul Walmsley #define OMAP3430_ST_MCBSP4_SHIFT 2 643da0747d4SPaul Walmsley #define OMAP3430_ST_MCBSP4_MASK (1 << 2) 644da0747d4SPaul Walmsley #define OMAP3430_ST_MCBSP3_SHIFT 1 645da0747d4SPaul Walmsley #define OMAP3430_ST_MCBSP3_MASK (1 << 1) 646da0747d4SPaul Walmsley #define OMAP3430_ST_MCBSP2_SHIFT 0 647da0747d4SPaul Walmsley #define OMAP3430_ST_MCBSP2_MASK (1 << 0) 648c595713dSTony Lindgren 649c595713dSTony Lindgren /* CM_AUTOIDLE_PER */ 650e5863689SGovindraj.R #define OMAP3630_AUTO_UART4_MASK (1 << 18) 651e5863689SGovindraj.R #define OMAP3630_AUTO_UART4_SHIFT 18 6522bc4ef71SPaul Walmsley #define OMAP3430_AUTO_GPIO6_MASK (1 << 17) 653c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO6_SHIFT 17 6542bc4ef71SPaul Walmsley #define OMAP3430_AUTO_GPIO5_MASK (1 << 16) 655c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO5_SHIFT 16 6562bc4ef71SPaul Walmsley #define OMAP3430_AUTO_GPIO4_MASK (1 << 15) 657c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO4_SHIFT 15 6582bc4ef71SPaul Walmsley #define OMAP3430_AUTO_GPIO3_MASK (1 << 14) 659c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO3_SHIFT 14 6602bc4ef71SPaul Walmsley #define OMAP3430_AUTO_GPIO2_MASK (1 << 13) 661c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO2_SHIFT 13 6622bc4ef71SPaul Walmsley #define OMAP3430_AUTO_WDT3_MASK (1 << 12) 663c595713dSTony Lindgren #define OMAP3430_AUTO_WDT3_SHIFT 12 6642bc4ef71SPaul Walmsley #define OMAP3430_AUTO_UART3_MASK (1 << 11) 665c595713dSTony Lindgren #define OMAP3430_AUTO_UART3_SHIFT 11 6662bc4ef71SPaul Walmsley #define OMAP3430_AUTO_GPT9_MASK (1 << 10) 667c595713dSTony Lindgren #define OMAP3430_AUTO_GPT9_SHIFT 10 6682bc4ef71SPaul Walmsley #define OMAP3430_AUTO_GPT8_MASK (1 << 9) 669c595713dSTony Lindgren #define OMAP3430_AUTO_GPT8_SHIFT 9 6702bc4ef71SPaul Walmsley #define OMAP3430_AUTO_GPT7_MASK (1 << 8) 671c595713dSTony Lindgren #define OMAP3430_AUTO_GPT7_SHIFT 8 6722bc4ef71SPaul Walmsley #define OMAP3430_AUTO_GPT6_MASK (1 << 7) 673c595713dSTony Lindgren #define OMAP3430_AUTO_GPT6_SHIFT 7 6742bc4ef71SPaul Walmsley #define OMAP3430_AUTO_GPT5_MASK (1 << 6) 675c595713dSTony Lindgren #define OMAP3430_AUTO_GPT5_SHIFT 6 6762bc4ef71SPaul Walmsley #define OMAP3430_AUTO_GPT4_MASK (1 << 5) 677c595713dSTony Lindgren #define OMAP3430_AUTO_GPT4_SHIFT 5 6782bc4ef71SPaul Walmsley #define OMAP3430_AUTO_GPT3_MASK (1 << 4) 679c595713dSTony Lindgren #define OMAP3430_AUTO_GPT3_SHIFT 4 6802bc4ef71SPaul Walmsley #define OMAP3430_AUTO_GPT2_MASK (1 << 3) 681c595713dSTony Lindgren #define OMAP3430_AUTO_GPT2_SHIFT 3 6822bc4ef71SPaul Walmsley #define OMAP3430_AUTO_MCBSP4_MASK (1 << 2) 683c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP4_SHIFT 2 6842bc4ef71SPaul Walmsley #define OMAP3430_AUTO_MCBSP3_MASK (1 << 1) 685c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP3_SHIFT 1 6862bc4ef71SPaul Walmsley #define OMAP3430_AUTO_MCBSP2_MASK (1 << 0) 687c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP2_SHIFT 0 688c595713dSTony Lindgren 689c595713dSTony Lindgren /* CM_CLKSEL_PER */ 690c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT9_MASK (1 << 7) 691c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT9_SHIFT 7 692c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT8_MASK (1 << 6) 693c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT8_SHIFT 6 694c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT7_MASK (1 << 5) 695c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT7_SHIFT 5 696c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT6_MASK (1 << 4) 697c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT6_SHIFT 4 698c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT5_MASK (1 << 3) 699c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT5_SHIFT 3 700c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT4_MASK (1 << 2) 701c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT4_SHIFT 2 702c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT3_MASK (1 << 1) 703c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT3_SHIFT 1 704c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT2_MASK (1 << 0) 705c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT2_SHIFT 0 706c595713dSTony Lindgren 707c595713dSTony Lindgren /* CM_SLEEPDEP_PER specific bits */ 7082bc4ef71SPaul Walmsley #define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2_MASK (1 << 2) 709c595713dSTony Lindgren 710c595713dSTony Lindgren /* CM_CLKSTCTRL_PER */ 711c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_PER_SHIFT 0 712c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0) 713c595713dSTony Lindgren 714c595713dSTony Lindgren /* CM_CLKSTST_PER */ 715801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_PER_SHIFT 0 716801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_PER_MASK (1 << 0) 717c595713dSTony Lindgren 718c595713dSTony Lindgren /* CM_CLKSEL1_EMU */ 719c595713dSTony Lindgren #define OMAP3430_DIV_DPLL4_SHIFT 24 720c595713dSTony Lindgren #define OMAP3430_DIV_DPLL4_MASK (0x1f << 24) 721678bc9a2SVishwanath BS #define OMAP3630_DIV_DPLL4_MASK (0x3f << 24) 722c595713dSTony Lindgren #define OMAP3430_DIV_DPLL3_SHIFT 16 723c595713dSTony Lindgren #define OMAP3430_DIV_DPLL3_MASK (0x1f << 16) 724c595713dSTony Lindgren #define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 725c595713dSTony Lindgren #define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11) 726c595713dSTony Lindgren #define OMAP3430_CLKSEL_PCLK_SHIFT 8 727c595713dSTony Lindgren #define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8) 728c595713dSTony Lindgren #define OMAP3430_CLKSEL_PCLKX2_SHIFT 6 729c595713dSTony Lindgren #define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6) 730c595713dSTony Lindgren #define OMAP3430_CLKSEL_ATCLK_SHIFT 4 731c595713dSTony Lindgren #define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4) 732c595713dSTony Lindgren #define OMAP3430_TRACE_MUX_CTRL_SHIFT 2 733c595713dSTony Lindgren #define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2) 734c595713dSTony Lindgren #define OMAP3430_MUX_CTRL_SHIFT 0 735c595713dSTony Lindgren #define OMAP3430_MUX_CTRL_MASK (0x3 << 0) 736c595713dSTony Lindgren 737c595713dSTony Lindgren /* CM_CLKSTCTRL_EMU */ 738c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_EMU_SHIFT 0 739c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0) 740c595713dSTony Lindgren 741c595713dSTony Lindgren /* CM_CLKSTST_EMU */ 742801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_EMU_SHIFT 0 743801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_EMU_MASK (1 << 0) 744c595713dSTony Lindgren 745c595713dSTony Lindgren /* CM_CLKSEL2_EMU specific bits */ 746c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8 747c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8) 748c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0 749c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0) 750c595713dSTony Lindgren 751c595713dSTony Lindgren /* CM_CLKSEL3_EMU specific bits */ 752c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8 753c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8) 754c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0 755c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0) 756c595713dSTony Lindgren 757c595713dSTony Lindgren /* CM_POLCTRL */ 7582bc4ef71SPaul Walmsley #define OMAP3430_CLKOUT2_POL_MASK (1 << 0) 759c595713dSTony Lindgren 760c595713dSTony Lindgren /* CM_IDLEST_NEON */ 7612bc4ef71SPaul Walmsley #define OMAP3430_ST_NEON_MASK (1 << 0) 762c595713dSTony Lindgren 763c595713dSTony Lindgren /* CM_CLKSTCTRL_NEON */ 764c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_NEON_SHIFT 0 765c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0) 766c595713dSTony Lindgren 767c595713dSTony Lindgren /* CM_FCLKEN_USBHOST */ 768c595713dSTony Lindgren #define OMAP3430ES2_EN_USBHOST2_SHIFT 1 769c595713dSTony Lindgren #define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1) 770c595713dSTony Lindgren #define OMAP3430ES2_EN_USBHOST1_SHIFT 0 771c595713dSTony Lindgren #define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0) 772c595713dSTony Lindgren 773c595713dSTony Lindgren /* CM_ICLKEN_USBHOST */ 774c595713dSTony Lindgren #define OMAP3430ES2_EN_USBHOST_SHIFT 0 775c595713dSTony Lindgren #define OMAP3430ES2_EN_USBHOST_MASK (1 << 0) 776c595713dSTony Lindgren 777c595713dSTony Lindgren /* CM_IDLEST_USBHOST */ 778da0747d4SPaul Walmsley #define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1 779da0747d4SPaul Walmsley #define OMAP3430ES2_ST_USBHOST_IDLE_MASK (1 << 1) 780da0747d4SPaul Walmsley #define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0 781da0747d4SPaul Walmsley #define OMAP3430ES2_ST_USBHOST_STDBY_MASK (1 << 0) 782c595713dSTony Lindgren 783c595713dSTony Lindgren /* CM_AUTOIDLE_USBHOST */ 784c595713dSTony Lindgren #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 785c595713dSTony Lindgren #define OMAP3430ES2_AUTO_USBHOST_MASK (1 << 0) 786c595713dSTony Lindgren 787c595713dSTony Lindgren /* CM_SLEEPDEP_USBHOST */ 788c595713dSTony Lindgren #define OMAP3430ES2_EN_MPU_SHIFT 1 789c595713dSTony Lindgren #define OMAP3430ES2_EN_MPU_MASK (1 << 1) 790c595713dSTony Lindgren #define OMAP3430ES2_EN_IVA2_SHIFT 2 791c595713dSTony Lindgren #define OMAP3430ES2_EN_IVA2_MASK (1 << 2) 792c595713dSTony Lindgren 793c595713dSTony Lindgren /* CM_CLKSTCTRL_USBHOST */ 794c595713dSTony Lindgren #define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0 795c595713dSTony Lindgren #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0) 796c595713dSTony Lindgren 797801954d3SPaul Walmsley /* CM_CLKSTST_USBHOST */ 798801954d3SPaul Walmsley #define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0 799801954d3SPaul Walmsley #define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0) 800c595713dSTony Lindgren 801bd2122caSPaul Walmsley /* 802bd2122caSPaul Walmsley * 803bd2122caSPaul Walmsley */ 804bd2122caSPaul Walmsley 805bd2122caSPaul Walmsley /* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */ 806bd2122caSPaul Walmsley #define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0 807bd2122caSPaul Walmsley #define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1 808bd2122caSPaul Walmsley #define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2 809bd2122caSPaul Walmsley #define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3 810bd2122caSPaul Walmsley 811bd2122caSPaul Walmsley 812c595713dSTony Lindgren #endif 813