1c595713dSTony Lindgren #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H 2c595713dSTony Lindgren #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H 3c595713dSTony Lindgren 4c595713dSTony Lindgren /* 5c595713dSTony Lindgren * OMAP3430 Clock Management register bits 6c595713dSTony Lindgren * 7c595713dSTony Lindgren * Copyright (C) 2007-2008 Texas Instruments, Inc. 8c595713dSTony Lindgren * Copyright (C) 2007-2008 Nokia Corporation 9c595713dSTony Lindgren * 10c595713dSTony Lindgren * Written by Paul Walmsley 11c595713dSTony Lindgren * 12c595713dSTony Lindgren * This program is free software; you can redistribute it and/or modify 13c595713dSTony Lindgren * it under the terms of the GNU General Public License version 2 as 14c595713dSTony Lindgren * published by the Free Software Foundation. 15c595713dSTony Lindgren */ 16c595713dSTony Lindgren 17c595713dSTony Lindgren #include "cm.h" 18c595713dSTony Lindgren 19c595713dSTony Lindgren /* Bits shared between registers */ 20c595713dSTony Lindgren 21c595713dSTony Lindgren /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ 22c595713dSTony Lindgren #define OMAP3430ES2_EN_MMC3_MASK (1 << 30) 23c595713dSTony Lindgren #define OMAP3430ES2_EN_MMC3_SHIFT 30 24c595713dSTony Lindgren #define OMAP3430_EN_MSPRO (1 << 23) 25c595713dSTony Lindgren #define OMAP3430_EN_MSPRO_SHIFT 23 26c595713dSTony Lindgren #define OMAP3430_EN_HDQ (1 << 22) 27c595713dSTony Lindgren #define OMAP3430_EN_HDQ_SHIFT 22 28c595713dSTony Lindgren #define OMAP3430ES1_EN_FSHOSTUSB (1 << 5) 29c595713dSTony Lindgren #define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5 30c595713dSTony Lindgren #define OMAP3430ES1_EN_D2D (1 << 3) 31c595713dSTony Lindgren #define OMAP3430ES1_EN_D2D_SHIFT 3 32c595713dSTony Lindgren #define OMAP3430_EN_SSI (1 << 0) 33c595713dSTony Lindgren #define OMAP3430_EN_SSI_SHIFT 0 34c595713dSTony Lindgren 35c595713dSTony Lindgren /* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */ 36c595713dSTony Lindgren #define OMAP3430ES2_EN_USBTLL_SHIFT 2 37c595713dSTony Lindgren #define OMAP3430ES2_EN_USBTLL_MASK (1 << 2) 38c595713dSTony Lindgren 39c595713dSTony Lindgren /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ 40c595713dSTony Lindgren #define OMAP3430_EN_WDT2 (1 << 5) 41c595713dSTony Lindgren #define OMAP3430_EN_WDT2_SHIFT 5 42c595713dSTony Lindgren 43c595713dSTony Lindgren /* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */ 44c595713dSTony Lindgren #define OMAP3430_EN_CAM (1 << 0) 45c595713dSTony Lindgren #define OMAP3430_EN_CAM_SHIFT 0 46c595713dSTony Lindgren 47c595713dSTony Lindgren /* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */ 48c595713dSTony Lindgren #define OMAP3430_EN_WDT3 (1 << 12) 49c595713dSTony Lindgren #define OMAP3430_EN_WDT3_SHIFT 12 50c595713dSTony Lindgren 51c595713dSTony Lindgren /* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */ 52c595713dSTony Lindgren #define OMAP3430_OVERRIDE_ENABLE (1 << 19) 53c595713dSTony Lindgren 54c595713dSTony Lindgren 55c595713dSTony Lindgren /* Bits specific to each register */ 56c595713dSTony Lindgren 57c595713dSTony Lindgren /* CM_FCLKEN_IVA2 */ 58dfa6d6f8SKevin Hilman #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0) 5931c203d4SHiroshi DOYU #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0 60c595713dSTony Lindgren 61c595713dSTony Lindgren /* CM_CLKEN_PLL_IVA2 */ 62c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8 63c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8) 64c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4 65c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4) 66c595713dSTony Lindgren #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3 67c595713dSTony Lindgren #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3) 68c595713dSTony Lindgren #define OMAP3430_EN_IVA2_DPLL_SHIFT 0 69c595713dSTony Lindgren #define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0) 70c595713dSTony Lindgren 71c595713dSTony Lindgren /* CM_IDLEST_IVA2 */ 72c595713dSTony Lindgren #define OMAP3430_ST_IVA2 (1 << 0) 73c595713dSTony Lindgren 74c595713dSTony Lindgren /* CM_IDLEST_PLL_IVA2 */ 75542313ccSPaul Walmsley #define OMAP3430_ST_IVA2_CLK_SHIFT 0 76542313ccSPaul Walmsley #define OMAP3430_ST_IVA2_CLK_MASK (1 << 0) 77c595713dSTony Lindgren 78c595713dSTony Lindgren /* CM_AUTOIDLE_PLL_IVA2 */ 79c595713dSTony Lindgren #define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0 80c595713dSTony Lindgren #define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0) 81c595713dSTony Lindgren 82c595713dSTony Lindgren /* CM_CLKSEL1_PLL_IVA2 */ 83c595713dSTony Lindgren #define OMAP3430_IVA2_CLK_SRC_SHIFT 19 84c595713dSTony Lindgren #define OMAP3430_IVA2_CLK_SRC_MASK (0x3 << 19) 85c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_MULT_SHIFT 8 86c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) 87c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_DIV_SHIFT 0 88c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0) 89c595713dSTony Lindgren 90c595713dSTony Lindgren /* CM_CLKSEL2_PLL_IVA2 */ 91c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0 92c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0) 93c595713dSTony Lindgren 94c595713dSTony Lindgren /* CM_CLKSTCTRL_IVA2 */ 95c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0 96c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0) 97c595713dSTony Lindgren 98c595713dSTony Lindgren /* CM_CLKSTST_IVA2 */ 99801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_IVA2_SHIFT 0 100801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0) 101c595713dSTony Lindgren 102c595713dSTony Lindgren /* CM_REVISION specific bits */ 103c595713dSTony Lindgren 104c595713dSTony Lindgren /* CM_SYSCONFIG specific bits */ 105c595713dSTony Lindgren 106c595713dSTony Lindgren /* CM_CLKEN_PLL_MPU */ 107c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8 108c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8) 109c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4 110c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4) 111c595713dSTony Lindgren #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3 112c595713dSTony Lindgren #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3) 113c595713dSTony Lindgren #define OMAP3430_EN_MPU_DPLL_SHIFT 0 114c595713dSTony Lindgren #define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0) 115c595713dSTony Lindgren 116c595713dSTony Lindgren /* CM_IDLEST_MPU */ 117c595713dSTony Lindgren #define OMAP3430_ST_MPU (1 << 0) 118c595713dSTony Lindgren 119c595713dSTony Lindgren /* CM_IDLEST_PLL_MPU */ 120542313ccSPaul Walmsley #define OMAP3430_ST_MPU_CLK_SHIFT 0 1213760d31fSRoman Tereshonkov #define OMAP3430_ST_MPU_CLK_MASK (1 << 0) 122c595713dSTony Lindgren 123c595713dSTony Lindgren /* CM_AUTOIDLE_PLL_MPU */ 124c595713dSTony Lindgren #define OMAP3430_AUTO_MPU_DPLL_SHIFT 0 125c595713dSTony Lindgren #define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0) 126c595713dSTony Lindgren 127c595713dSTony Lindgren /* CM_CLKSEL1_PLL_MPU */ 128c595713dSTony Lindgren #define OMAP3430_MPU_CLK_SRC_SHIFT 19 129c595713dSTony Lindgren #define OMAP3430_MPU_CLK_SRC_MASK (0x3 << 19) 130c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_MULT_SHIFT 8 131c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) 132c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_DIV_SHIFT 0 133c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0) 134c595713dSTony Lindgren 135c595713dSTony Lindgren /* CM_CLKSEL2_PLL_MPU */ 136c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0 137c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0) 138c595713dSTony Lindgren 139c595713dSTony Lindgren /* CM_CLKSTCTRL_MPU */ 140c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_MPU_SHIFT 0 141c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0) 142c595713dSTony Lindgren 143c595713dSTony Lindgren /* CM_CLKSTST_MPU */ 144801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_MPU_SHIFT 0 145801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0) 146c595713dSTony Lindgren 147c595713dSTony Lindgren /* CM_FCLKEN1_CORE specific bits */ 1488111b221SKevin Hilman #define OMAP3430_EN_MODEM (1 << 31) 1498111b221SKevin Hilman #define OMAP3430_EN_MODEM_SHIFT 31 150c595713dSTony Lindgren 151c595713dSTony Lindgren /* CM_ICLKEN1_CORE specific bits */ 152c595713dSTony Lindgren #define OMAP3430_EN_ICR (1 << 29) 153c595713dSTony Lindgren #define OMAP3430_EN_ICR_SHIFT 29 154c595713dSTony Lindgren #define OMAP3430_EN_AES2 (1 << 28) 155c595713dSTony Lindgren #define OMAP3430_EN_AES2_SHIFT 28 156c595713dSTony Lindgren #define OMAP3430_EN_SHA12 (1 << 27) 157c595713dSTony Lindgren #define OMAP3430_EN_SHA12_SHIFT 27 158c595713dSTony Lindgren #define OMAP3430_EN_DES2 (1 << 26) 159c595713dSTony Lindgren #define OMAP3430_EN_DES2_SHIFT 26 160c595713dSTony Lindgren #define OMAP3430ES1_EN_FAC (1 << 8) 161c595713dSTony Lindgren #define OMAP3430ES1_EN_FAC_SHIFT 8 162c595713dSTony Lindgren #define OMAP3430_EN_MAILBOXES (1 << 7) 163c595713dSTony Lindgren #define OMAP3430_EN_MAILBOXES_SHIFT 7 164c595713dSTony Lindgren #define OMAP3430_EN_OMAPCTRL (1 << 6) 165c595713dSTony Lindgren #define OMAP3430_EN_OMAPCTRL_SHIFT 6 1668111b221SKevin Hilman #define OMAP3430_EN_SAD2D (1 << 3) 1678111b221SKevin Hilman #define OMAP3430_EN_SAD2D_SHIFT 3 168c595713dSTony Lindgren #define OMAP3430_EN_SDRC (1 << 1) 169c595713dSTony Lindgren #define OMAP3430_EN_SDRC_SHIFT 1 170c595713dSTony Lindgren 1713cc4a2fcSRanjith Lohithakshan /* AM35XX specific CM_ICLKEN1_CORE bits */ 1723cc4a2fcSRanjith Lohithakshan #define AM35XX_EN_IPSS_MASK (1 << 4) 1733cc4a2fcSRanjith Lohithakshan #define AM35XX_EN_IPSS_SHIFT 4 1743cc4a2fcSRanjith Lohithakshan #define AM35XX_EN_UART4_MASK (1 << 23) 1753cc4a2fcSRanjith Lohithakshan #define AM35XX_EN_UART4_SHIFT 23 1763cc4a2fcSRanjith Lohithakshan 177c595713dSTony Lindgren /* CM_ICLKEN2_CORE */ 178c595713dSTony Lindgren #define OMAP3430_EN_PKA (1 << 4) 179c595713dSTony Lindgren #define OMAP3430_EN_PKA_SHIFT 4 180c595713dSTony Lindgren #define OMAP3430_EN_AES1 (1 << 3) 181c595713dSTony Lindgren #define OMAP3430_EN_AES1_SHIFT 3 182c595713dSTony Lindgren #define OMAP3430_EN_RNG (1 << 2) 183c595713dSTony Lindgren #define OMAP3430_EN_RNG_SHIFT 2 184c595713dSTony Lindgren #define OMAP3430_EN_SHA11 (1 << 1) 185c595713dSTony Lindgren #define OMAP3430_EN_SHA11_SHIFT 1 186c595713dSTony Lindgren #define OMAP3430_EN_DES1 (1 << 0) 187c595713dSTony Lindgren #define OMAP3430_EN_DES1_SHIFT 0 188c595713dSTony Lindgren 1898111b221SKevin Hilman /* CM_ICLKEN3_CORE */ 1908111b221SKevin Hilman #define OMAP3430_EN_MAD2D_SHIFT 3 1918111b221SKevin Hilman #define OMAP3430_EN_MAD2D (1 << 3) 1928111b221SKevin Hilman 193c595713dSTony Lindgren /* CM_FCLKEN3_CORE specific bits */ 194c595713dSTony Lindgren #define OMAP3430ES2_EN_TS_SHIFT 1 195c595713dSTony Lindgren #define OMAP3430ES2_EN_TS_MASK (1 << 1) 196c595713dSTony Lindgren #define OMAP3430ES2_EN_CPEFUSE_SHIFT 0 197c595713dSTony Lindgren #define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0) 198c595713dSTony Lindgren 199c595713dSTony Lindgren /* CM_IDLEST1_CORE specific bits */ 200da0747d4SPaul Walmsley #define OMAP3430ES2_ST_MMC3_SHIFT 30 201da0747d4SPaul Walmsley #define OMAP3430ES2_ST_MMC3_MASK (1 << 30) 202da0747d4SPaul Walmsley #define OMAP3430_ST_ICR_SHIFT 29 203da0747d4SPaul Walmsley #define OMAP3430_ST_ICR_MASK (1 << 29) 204da0747d4SPaul Walmsley #define OMAP3430_ST_AES2_SHIFT 28 205da0747d4SPaul Walmsley #define OMAP3430_ST_AES2_MASK (1 << 28) 206da0747d4SPaul Walmsley #define OMAP3430_ST_SHA12_SHIFT 27 207da0747d4SPaul Walmsley #define OMAP3430_ST_SHA12_MASK (1 << 27) 208da0747d4SPaul Walmsley #define OMAP3430_ST_DES2_SHIFT 26 209da0747d4SPaul Walmsley #define OMAP3430_ST_DES2_MASK (1 << 26) 210da0747d4SPaul Walmsley #define OMAP3430_ST_MSPRO_SHIFT 23 211da0747d4SPaul Walmsley #define OMAP3430_ST_MSPRO_MASK (1 << 23) 212da0747d4SPaul Walmsley #define OMAP3430_ST_HDQ_SHIFT 22 213da0747d4SPaul Walmsley #define OMAP3430_ST_HDQ_MASK (1 << 22) 214da0747d4SPaul Walmsley #define OMAP3430ES1_ST_FAC_SHIFT 8 215da0747d4SPaul Walmsley #define OMAP3430ES1_ST_FAC_MASK (1 << 8) 216da0747d4SPaul Walmsley #define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8 217da0747d4SPaul Walmsley #define OMAP3430ES2_ST_SSI_IDLE_MASK (1 << 8) 218da0747d4SPaul Walmsley #define OMAP3430_ST_MAILBOXES_SHIFT 7 219da0747d4SPaul Walmsley #define OMAP3430_ST_MAILBOXES_MASK (1 << 7) 220da0747d4SPaul Walmsley #define OMAP3430_ST_OMAPCTRL_SHIFT 6 221da0747d4SPaul Walmsley #define OMAP3430_ST_OMAPCTRL_MASK (1 << 6) 222da0747d4SPaul Walmsley #define OMAP3430_ST_SDMA_SHIFT 2 223da0747d4SPaul Walmsley #define OMAP3430_ST_SDMA_MASK (1 << 2) 224da0747d4SPaul Walmsley #define OMAP3430_ST_SDRC_SHIFT 1 225da0747d4SPaul Walmsley #define OMAP3430_ST_SDRC_MASK (1 << 1) 226da0747d4SPaul Walmsley #define OMAP3430_ST_SSI_STDBY_SHIFT 0 227da0747d4SPaul Walmsley #define OMAP3430_ST_SSI_STDBY_MASK (1 << 0) 228c595713dSTony Lindgren 2293cc4a2fcSRanjith Lohithakshan /* AM35xx specific CM_IDLEST1_CORE bits */ 2303cc4a2fcSRanjith Lohithakshan #define AM35XX_ST_IPSS_SHIFT 5 2313cc4a2fcSRanjith Lohithakshan #define AM35XX_ST_IPSS_MASK (1 << 5) 2323cc4a2fcSRanjith Lohithakshan 233c595713dSTony Lindgren /* CM_IDLEST2_CORE */ 234da0747d4SPaul Walmsley #define OMAP3430_ST_PKA_SHIFT 4 235da0747d4SPaul Walmsley #define OMAP3430_ST_PKA_MASK (1 << 4) 236da0747d4SPaul Walmsley #define OMAP3430_ST_AES1_SHIFT 3 237da0747d4SPaul Walmsley #define OMAP3430_ST_AES1_MASK (1 << 3) 238da0747d4SPaul Walmsley #define OMAP3430_ST_RNG_SHIFT 2 239da0747d4SPaul Walmsley #define OMAP3430_ST_RNG_MASK (1 << 2) 240da0747d4SPaul Walmsley #define OMAP3430_ST_SHA11_SHIFT 1 241da0747d4SPaul Walmsley #define OMAP3430_ST_SHA11_MASK (1 << 1) 242da0747d4SPaul Walmsley #define OMAP3430_ST_DES1_SHIFT 0 243da0747d4SPaul Walmsley #define OMAP3430_ST_DES1_MASK (1 << 0) 244c595713dSTony Lindgren 245c595713dSTony Lindgren /* CM_IDLEST3_CORE */ 246c595713dSTony Lindgren #define OMAP3430ES2_ST_USBTLL_SHIFT 2 247c595713dSTony Lindgren #define OMAP3430ES2_ST_USBTLL_MASK (1 << 2) 248da0747d4SPaul Walmsley #define OMAP3430ES2_ST_CPEFUSE_SHIFT 0 249da0747d4SPaul Walmsley #define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0) 250c595713dSTony Lindgren 251c595713dSTony Lindgren /* CM_AUTOIDLE1_CORE */ 2528111b221SKevin Hilman #define OMAP3430_AUTO_MODEM (1 << 31) 2538111b221SKevin Hilman #define OMAP3430_AUTO_MODEM_SHIFT 31 254027d8dedSJouni Hogander #define OMAP3430ES2_AUTO_MMC3 (1 << 30) 255027d8dedSJouni Hogander #define OMAP3430ES2_AUTO_MMC3_SHIFT 30 256027d8dedSJouni Hogander #define OMAP3430ES2_AUTO_ICR (1 << 29) 257027d8dedSJouni Hogander #define OMAP3430ES2_AUTO_ICR_SHIFT 29 258c595713dSTony Lindgren #define OMAP3430_AUTO_AES2 (1 << 28) 259c595713dSTony Lindgren #define OMAP3430_AUTO_AES2_SHIFT 28 260c595713dSTony Lindgren #define OMAP3430_AUTO_SHA12 (1 << 27) 261c595713dSTony Lindgren #define OMAP3430_AUTO_SHA12_SHIFT 27 262c595713dSTony Lindgren #define OMAP3430_AUTO_DES2 (1 << 26) 263c595713dSTony Lindgren #define OMAP3430_AUTO_DES2_SHIFT 26 264c595713dSTony Lindgren #define OMAP3430_AUTO_MMC2 (1 << 25) 265c595713dSTony Lindgren #define OMAP3430_AUTO_MMC2_SHIFT 25 266c595713dSTony Lindgren #define OMAP3430_AUTO_MMC1 (1 << 24) 267c595713dSTony Lindgren #define OMAP3430_AUTO_MMC1_SHIFT 24 268c595713dSTony Lindgren #define OMAP3430_AUTO_MSPRO (1 << 23) 269c595713dSTony Lindgren #define OMAP3430_AUTO_MSPRO_SHIFT 23 270c595713dSTony Lindgren #define OMAP3430_AUTO_HDQ (1 << 22) 271c595713dSTony Lindgren #define OMAP3430_AUTO_HDQ_SHIFT 22 272c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI4 (1 << 21) 273c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI4_SHIFT 21 274c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI3 (1 << 20) 275c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI3_SHIFT 20 276c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI2 (1 << 19) 277c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI2_SHIFT 19 278c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI1 (1 << 18) 279c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI1_SHIFT 18 280c595713dSTony Lindgren #define OMAP3430_AUTO_I2C3 (1 << 17) 281c595713dSTony Lindgren #define OMAP3430_AUTO_I2C3_SHIFT 17 282c595713dSTony Lindgren #define OMAP3430_AUTO_I2C2 (1 << 16) 283c595713dSTony Lindgren #define OMAP3430_AUTO_I2C2_SHIFT 16 284c595713dSTony Lindgren #define OMAP3430_AUTO_I2C1 (1 << 15) 285c595713dSTony Lindgren #define OMAP3430_AUTO_I2C1_SHIFT 15 286c595713dSTony Lindgren #define OMAP3430_AUTO_UART2 (1 << 14) 287c595713dSTony Lindgren #define OMAP3430_AUTO_UART2_SHIFT 14 288c595713dSTony Lindgren #define OMAP3430_AUTO_UART1 (1 << 13) 289c595713dSTony Lindgren #define OMAP3430_AUTO_UART1_SHIFT 13 290c595713dSTony Lindgren #define OMAP3430_AUTO_GPT11 (1 << 12) 291c595713dSTony Lindgren #define OMAP3430_AUTO_GPT11_SHIFT 12 292c595713dSTony Lindgren #define OMAP3430_AUTO_GPT10 (1 << 11) 293c595713dSTony Lindgren #define OMAP3430_AUTO_GPT10_SHIFT 11 294c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP5 (1 << 10) 295c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP5_SHIFT 10 296c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP1 (1 << 9) 297c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP1_SHIFT 9 298c595713dSTony Lindgren #define OMAP3430ES1_AUTO_FAC (1 << 8) 299c595713dSTony Lindgren #define OMAP3430ES1_AUTO_FAC_SHIFT 8 300c595713dSTony Lindgren #define OMAP3430_AUTO_MAILBOXES (1 << 7) 301c595713dSTony Lindgren #define OMAP3430_AUTO_MAILBOXES_SHIFT 7 302c595713dSTony Lindgren #define OMAP3430_AUTO_OMAPCTRL (1 << 6) 303c595713dSTony Lindgren #define OMAP3430_AUTO_OMAPCTRL_SHIFT 6 304c595713dSTony Lindgren #define OMAP3430ES1_AUTO_FSHOSTUSB (1 << 5) 305c595713dSTony Lindgren #define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5 306c595713dSTony Lindgren #define OMAP3430_AUTO_HSOTGUSB (1 << 4) 307c595713dSTony Lindgren #define OMAP3430_AUTO_HSOTGUSB_SHIFT 4 308c595713dSTony Lindgren #define OMAP3430ES1_AUTO_D2D (1 << 3) 309c595713dSTony Lindgren #define OMAP3430ES1_AUTO_D2D_SHIFT 3 3108111b221SKevin Hilman #define OMAP3430_AUTO_SAD2D (1 << 3) 3118111b221SKevin Hilman #define OMAP3430_AUTO_SAD2D_SHIFT 3 312c595713dSTony Lindgren #define OMAP3430_AUTO_SSI (1 << 0) 313c595713dSTony Lindgren #define OMAP3430_AUTO_SSI_SHIFT 0 314c595713dSTony Lindgren 315c595713dSTony Lindgren /* CM_AUTOIDLE2_CORE */ 316c595713dSTony Lindgren #define OMAP3430_AUTO_PKA (1 << 4) 317c595713dSTony Lindgren #define OMAP3430_AUTO_PKA_SHIFT 4 318c595713dSTony Lindgren #define OMAP3430_AUTO_AES1 (1 << 3) 319c595713dSTony Lindgren #define OMAP3430_AUTO_AES1_SHIFT 3 320c595713dSTony Lindgren #define OMAP3430_AUTO_RNG (1 << 2) 321c595713dSTony Lindgren #define OMAP3430_AUTO_RNG_SHIFT 2 322c595713dSTony Lindgren #define OMAP3430_AUTO_SHA11 (1 << 1) 323c595713dSTony Lindgren #define OMAP3430_AUTO_SHA11_SHIFT 1 324c595713dSTony Lindgren #define OMAP3430_AUTO_DES1 (1 << 0) 325c595713dSTony Lindgren #define OMAP3430_AUTO_DES1_SHIFT 0 326c595713dSTony Lindgren 327c595713dSTony Lindgren /* CM_AUTOIDLE3_CORE */ 328027d8dedSJouni Hogander #define OMAP3430ES2_AUTO_USBHOST (1 << 0) 329027d8dedSJouni Hogander #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 330027d8dedSJouni Hogander #define OMAP3430ES2_AUTO_USBTLL (1 << 2) 331c595713dSTony Lindgren #define OMAP3430ES2_AUTO_USBTLL_SHIFT 2 332c595713dSTony Lindgren #define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2) 3338111b221SKevin Hilman #define OMAP3430_AUTO_MAD2D_SHIFT 3 3348111b221SKevin Hilman #define OMAP3430_AUTO_MAD2D (1 << 3) 335c595713dSTony Lindgren 336c595713dSTony Lindgren /* CM_CLKSEL_CORE */ 337c595713dSTony Lindgren #define OMAP3430_CLKSEL_SSI_SHIFT 8 338c595713dSTony Lindgren #define OMAP3430_CLKSEL_SSI_MASK (0xf << 8) 339c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT11_MASK (1 << 7) 340c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT11_SHIFT 7 341c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT10_MASK (1 << 6) 342c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT10_SHIFT 6 343c595713dSTony Lindgren #define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4 344c595713dSTony Lindgren #define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4) 345c595713dSTony Lindgren #define OMAP3430_CLKSEL_L4_SHIFT 2 346c595713dSTony Lindgren #define OMAP3430_CLKSEL_L4_MASK (0x3 << 2) 347c595713dSTony Lindgren #define OMAP3430_CLKSEL_L3_SHIFT 0 348c595713dSTony Lindgren #define OMAP3430_CLKSEL_L3_MASK (0x3 << 0) 349c595713dSTony Lindgren 350c595713dSTony Lindgren /* CM_CLKSTCTRL_CORE */ 351c595713dSTony Lindgren #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4 352c595713dSTony Lindgren #define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4) 353c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_L4_SHIFT 2 354c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2) 355c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_L3_SHIFT 0 356c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0) 357c595713dSTony Lindgren 358c595713dSTony Lindgren /* CM_CLKSTST_CORE */ 359801954d3SPaul Walmsley #define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT 2 360801954d3SPaul Walmsley #define OMAP3430ES1_CLKACTIVITY_D2D_MASK (1 << 2) 361801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_L4_SHIFT 1 362801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_L4_MASK (1 << 1) 363801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_L3_SHIFT 0 364801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0) 365c595713dSTony Lindgren 366c595713dSTony Lindgren /* CM_FCLKEN_GFX */ 367c595713dSTony Lindgren #define OMAP3430ES1_EN_3D (1 << 2) 368c595713dSTony Lindgren #define OMAP3430ES1_EN_3D_SHIFT 2 369c595713dSTony Lindgren #define OMAP3430ES1_EN_2D (1 << 1) 370c595713dSTony Lindgren #define OMAP3430ES1_EN_2D_SHIFT 1 371c595713dSTony Lindgren 372c595713dSTony Lindgren /* CM_ICLKEN_GFX specific bits */ 373c595713dSTony Lindgren 374c595713dSTony Lindgren /* CM_IDLEST_GFX specific bits */ 375c595713dSTony Lindgren 376c595713dSTony Lindgren /* CM_CLKSEL_GFX specific bits */ 377c595713dSTony Lindgren 378c595713dSTony Lindgren /* CM_SLEEPDEP_GFX specific bits */ 379c595713dSTony Lindgren 380c595713dSTony Lindgren /* CM_CLKSTCTRL_GFX */ 381c595713dSTony Lindgren #define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0 382c595713dSTony Lindgren #define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0) 383c595713dSTony Lindgren 384c595713dSTony Lindgren /* CM_CLKSTST_GFX */ 385801954d3SPaul Walmsley #define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT 0 386801954d3SPaul Walmsley #define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0) 387c595713dSTony Lindgren 388c595713dSTony Lindgren /* CM_FCLKEN_SGX */ 389712d7c86SDaniel Stone #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1 390712d7c86SDaniel Stone #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1) 391712d7c86SDaniel Stone 392b024b542STero Kristo /* CM_IDLEST_SGX */ 393b024b542STero Kristo #define OMAP3430ES2_ST_SGX_SHIFT 1 394b024b542STero Kristo #define OMAP3430ES2_ST_SGX_MASK (1 << 1) 395b024b542STero Kristo 396712d7c86SDaniel Stone /* CM_ICLKEN_SGX */ 397712d7c86SDaniel Stone #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0 398712d7c86SDaniel Stone #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0) 399c595713dSTony Lindgren 400c595713dSTony Lindgren /* CM_CLKSEL_SGX */ 401c595713dSTony Lindgren #define OMAP3430ES2_CLKSEL_SGX_SHIFT 0 402c595713dSTony Lindgren #define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0) 403c595713dSTony Lindgren 404801954d3SPaul Walmsley /* CM_CLKSTCTRL_SGX */ 405801954d3SPaul Walmsley #define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT 0 406801954d3SPaul Walmsley #define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0) 407801954d3SPaul Walmsley 408801954d3SPaul Walmsley /* CM_CLKSTST_SGX */ 409801954d3SPaul Walmsley #define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT 0 410801954d3SPaul Walmsley #define OMAP3430ES2_CLKACTIVITY_SGX_MASK (1 << 0) 411801954d3SPaul Walmsley 412c595713dSTony Lindgren /* CM_FCLKEN_WKUP specific bits */ 413c595713dSTony Lindgren #define OMAP3430ES2_EN_USIMOCP_SHIFT 9 414da0747d4SPaul Walmsley #define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9) 415c595713dSTony Lindgren 416c595713dSTony Lindgren /* CM_ICLKEN_WKUP specific bits */ 417c595713dSTony Lindgren #define OMAP3430_EN_WDT1 (1 << 4) 418c595713dSTony Lindgren #define OMAP3430_EN_WDT1_SHIFT 4 419c595713dSTony Lindgren #define OMAP3430_EN_32KSYNC (1 << 2) 420c595713dSTony Lindgren #define OMAP3430_EN_32KSYNC_SHIFT 2 421c595713dSTony Lindgren 422c595713dSTony Lindgren /* CM_IDLEST_WKUP specific bits */ 423da0747d4SPaul Walmsley #define OMAP3430ES2_ST_USIMOCP_SHIFT 9 424da0747d4SPaul Walmsley #define OMAP3430ES2_ST_USIMOCP_MASK (1 << 9) 425da0747d4SPaul Walmsley #define OMAP3430_ST_WDT2_SHIFT 5 426da0747d4SPaul Walmsley #define OMAP3430_ST_WDT2_MASK (1 << 5) 427da0747d4SPaul Walmsley #define OMAP3430_ST_WDT1_SHIFT 4 428da0747d4SPaul Walmsley #define OMAP3430_ST_WDT1_MASK (1 << 4) 429da0747d4SPaul Walmsley #define OMAP3430_ST_32KSYNC_SHIFT 2 430da0747d4SPaul Walmsley #define OMAP3430_ST_32KSYNC_MASK (1 << 2) 431c595713dSTony Lindgren 432c595713dSTony Lindgren /* CM_AUTOIDLE_WKUP */ 433da0747d4SPaul Walmsley #define OMAP3430ES2_AUTO_USIMOCP (1 << 9) 434da0747d4SPaul Walmsley #define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9 435c595713dSTony Lindgren #define OMAP3430_AUTO_WDT2 (1 << 5) 436c595713dSTony Lindgren #define OMAP3430_AUTO_WDT2_SHIFT 5 437c595713dSTony Lindgren #define OMAP3430_AUTO_WDT1 (1 << 4) 438c595713dSTony Lindgren #define OMAP3430_AUTO_WDT1_SHIFT 4 439c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO1 (1 << 3) 440c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO1_SHIFT 3 441c595713dSTony Lindgren #define OMAP3430_AUTO_32KSYNC (1 << 2) 442c595713dSTony Lindgren #define OMAP3430_AUTO_32KSYNC_SHIFT 2 443c595713dSTony Lindgren #define OMAP3430_AUTO_GPT12 (1 << 1) 444c595713dSTony Lindgren #define OMAP3430_AUTO_GPT12_SHIFT 1 445c595713dSTony Lindgren #define OMAP3430_AUTO_GPT1 (1 << 0) 446c595713dSTony Lindgren #define OMAP3430_AUTO_GPT1_SHIFT 0 447c595713dSTony Lindgren 448c595713dSTony Lindgren /* CM_CLKSEL_WKUP */ 449c595713dSTony Lindgren #define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3) 450c595713dSTony Lindgren #define OMAP3430_CLKSEL_RM_SHIFT 1 451c595713dSTony Lindgren #define OMAP3430_CLKSEL_RM_MASK (0x3 << 1) 452c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT1_SHIFT 0 453c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT1_MASK (1 << 0) 454c595713dSTony Lindgren 455c595713dSTony Lindgren /* CM_CLKEN_PLL */ 456c595713dSTony Lindgren #define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31 457c595713dSTony Lindgren #define OMAP3430_PWRDN_CAM_SHIFT 30 458c595713dSTony Lindgren #define OMAP3430_PWRDN_DSS1_SHIFT 29 459c595713dSTony Lindgren #define OMAP3430_PWRDN_TV_SHIFT 28 460c595713dSTony Lindgren #define OMAP3430_PWRDN_96M_SHIFT 27 461c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24 462c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24) 463c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20 464c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20) 465c595713dSTony Lindgren #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19 466c595713dSTony Lindgren #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19) 467c595713dSTony Lindgren #define OMAP3430_EN_PERIPH_DPLL_SHIFT 16 468c595713dSTony Lindgren #define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16) 469c595713dSTony Lindgren #define OMAP3430_PWRDN_EMU_CORE_SHIFT 12 470c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8 471c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8) 472c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4 473c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4) 474c595713dSTony Lindgren #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3 475c595713dSTony Lindgren #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3) 476c595713dSTony Lindgren #define OMAP3430_EN_CORE_DPLL_SHIFT 0 477c595713dSTony Lindgren #define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0) 478c595713dSTony Lindgren 479c595713dSTony Lindgren /* CM_CLKEN2_PLL */ 480c595713dSTony Lindgren #define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10 481c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8) 482c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4 483c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4) 484c595713dSTony Lindgren #define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3 485c595713dSTony Lindgren #define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0 486c595713dSTony Lindgren #define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0) 487c595713dSTony Lindgren 488c595713dSTony Lindgren /* CM_IDLEST_CKGEN */ 489c595713dSTony Lindgren #define OMAP3430_ST_54M_CLK (1 << 5) 490c595713dSTony Lindgren #define OMAP3430_ST_12M_CLK (1 << 4) 491c595713dSTony Lindgren #define OMAP3430_ST_48M_CLK (1 << 3) 492c595713dSTony Lindgren #define OMAP3430_ST_96M_CLK (1 << 2) 493542313ccSPaul Walmsley #define OMAP3430_ST_PERIPH_CLK_SHIFT 1 494542313ccSPaul Walmsley #define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1) 495542313ccSPaul Walmsley #define OMAP3430_ST_CORE_CLK_SHIFT 0 496542313ccSPaul Walmsley #define OMAP3430_ST_CORE_CLK_MASK (1 << 0) 497c595713dSTony Lindgren 498c595713dSTony Lindgren /* CM_IDLEST2_CKGEN */ 499da0747d4SPaul Walmsley #define OMAP3430ES2_ST_USIM_CLK_SHIFT 2 500da0747d4SPaul Walmsley #define OMAP3430ES2_ST_USIM_CLK_MASK (1 << 2) 501c595713dSTony Lindgren #define OMAP3430ES2_ST_120M_CLK_SHIFT 1 502c595713dSTony Lindgren #define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1) 503c595713dSTony Lindgren #define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0 504c595713dSTony Lindgren #define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0) 505c595713dSTony Lindgren 506c595713dSTony Lindgren /* CM_AUTOIDLE_PLL */ 507c595713dSTony Lindgren #define OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3 508c595713dSTony Lindgren #define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3) 509c595713dSTony Lindgren #define OMAP3430_AUTO_CORE_DPLL_SHIFT 0 510c595713dSTony Lindgren #define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0) 511c595713dSTony Lindgren 512542313ccSPaul Walmsley /* CM_AUTOIDLE2_PLL */ 513542313ccSPaul Walmsley #define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT 0 514542313ccSPaul Walmsley #define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0) 515542313ccSPaul Walmsley 516c595713dSTony Lindgren /* CM_CLKSEL1_PLL */ 517c595713dSTony Lindgren /* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */ 518c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27 519c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27) 520c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_MULT_SHIFT 16 521c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) 522c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_DIV_SHIFT 8 523c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8) 5249cfd985eSPaul Walmsley #define OMAP3430_SOURCE_96M_SHIFT 6 5259cfd985eSPaul Walmsley #define OMAP3430_SOURCE_96M_MASK (1 << 6) 5269cfd985eSPaul Walmsley #define OMAP3430_SOURCE_54M_SHIFT 5 5279cfd985eSPaul Walmsley #define OMAP3430_SOURCE_54M_MASK (1 << 5) 5289cfd985eSPaul Walmsley #define OMAP3430_SOURCE_48M_SHIFT 3 5299cfd985eSPaul Walmsley #define OMAP3430_SOURCE_48M_MASK (1 << 3) 530c595713dSTony Lindgren 531c595713dSTony Lindgren /* CM_CLKSEL2_PLL */ 532c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8 533c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8) 534c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0 535c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0) 536c595713dSTony Lindgren 537c595713dSTony Lindgren /* CM_CLKSEL3_PLL */ 538c595713dSTony Lindgren #define OMAP3430_DIV_96M_SHIFT 0 539c595713dSTony Lindgren #define OMAP3430_DIV_96M_MASK (0x1f << 0) 540c595713dSTony Lindgren 541c595713dSTony Lindgren /* CM_CLKSEL4_PLL */ 542c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8 543c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8) 544c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0 545c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0) 546c595713dSTony Lindgren 547c595713dSTony Lindgren /* CM_CLKSEL5_PLL */ 548c595713dSTony Lindgren #define OMAP3430ES2_DIV_120M_SHIFT 0 549c595713dSTony Lindgren #define OMAP3430ES2_DIV_120M_MASK (0x1f << 0) 550c595713dSTony Lindgren 551c595713dSTony Lindgren /* CM_CLKOUT_CTRL */ 552c595713dSTony Lindgren #define OMAP3430_CLKOUT2_EN_SHIFT 7 553c595713dSTony Lindgren #define OMAP3430_CLKOUT2_EN (1 << 7) 554c595713dSTony Lindgren #define OMAP3430_CLKOUT2_DIV_SHIFT 3 555c595713dSTony Lindgren #define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3) 556c595713dSTony Lindgren #define OMAP3430_CLKOUT2SOURCE_SHIFT 0 557c595713dSTony Lindgren #define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0) 558c595713dSTony Lindgren 559c595713dSTony Lindgren /* CM_FCLKEN_DSS */ 560c595713dSTony Lindgren #define OMAP3430_EN_TV (1 << 2) 561c595713dSTony Lindgren #define OMAP3430_EN_TV_SHIFT 2 562c595713dSTony Lindgren #define OMAP3430_EN_DSS2 (1 << 1) 563c595713dSTony Lindgren #define OMAP3430_EN_DSS2_SHIFT 1 564c595713dSTony Lindgren #define OMAP3430_EN_DSS1 (1 << 0) 565c595713dSTony Lindgren #define OMAP3430_EN_DSS1_SHIFT 0 566c595713dSTony Lindgren 567c595713dSTony Lindgren /* CM_ICLKEN_DSS */ 568c595713dSTony Lindgren #define OMAP3430_CM_ICLKEN_DSS_EN_DSS (1 << 0) 569c595713dSTony Lindgren #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 570c595713dSTony Lindgren 571c595713dSTony Lindgren /* CM_IDLEST_DSS */ 572da0747d4SPaul Walmsley #define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1 573da0747d4SPaul Walmsley #define OMAP3430ES2_ST_DSS_IDLE_MASK (1 << 1) 574da0747d4SPaul Walmsley #define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0 575da0747d4SPaul Walmsley #define OMAP3430ES2_ST_DSS_STDBY_MASK (1 << 0) 576da0747d4SPaul Walmsley #define OMAP3430ES1_ST_DSS_SHIFT 0 577da0747d4SPaul Walmsley #define OMAP3430ES1_ST_DSS_MASK (1 << 0) 578c595713dSTony Lindgren 579c595713dSTony Lindgren /* CM_AUTOIDLE_DSS */ 580c595713dSTony Lindgren #define OMAP3430_AUTO_DSS (1 << 0) 581c595713dSTony Lindgren #define OMAP3430_AUTO_DSS_SHIFT 0 582c595713dSTony Lindgren 583c595713dSTony Lindgren /* CM_CLKSEL_DSS */ 584c595713dSTony Lindgren #define OMAP3430_CLKSEL_TV_SHIFT 8 585c595713dSTony Lindgren #define OMAP3430_CLKSEL_TV_MASK (0x1f << 8) 586c595713dSTony Lindgren #define OMAP3430_CLKSEL_DSS1_SHIFT 0 587c595713dSTony Lindgren #define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0) 588c595713dSTony Lindgren 589c595713dSTony Lindgren /* CM_SLEEPDEP_DSS specific bits */ 590c595713dSTony Lindgren 591c595713dSTony Lindgren /* CM_CLKSTCTRL_DSS */ 592c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_DSS_SHIFT 0 593c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0) 594c595713dSTony Lindgren 595c595713dSTony Lindgren /* CM_CLKSTST_DSS */ 596801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_DSS_SHIFT 0 597801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0) 598c595713dSTony Lindgren 599c595713dSTony Lindgren /* CM_FCLKEN_CAM specific bits */ 6006c8fe0b9SSergio Aguirre #define OMAP3430_EN_CSI2 (1 << 1) 6016c8fe0b9SSergio Aguirre #define OMAP3430_EN_CSI2_SHIFT 1 602c595713dSTony Lindgren 603c595713dSTony Lindgren /* CM_ICLKEN_CAM specific bits */ 604c595713dSTony Lindgren 605c595713dSTony Lindgren /* CM_IDLEST_CAM */ 606c595713dSTony Lindgren #define OMAP3430_ST_CAM (1 << 0) 607c595713dSTony Lindgren 608c595713dSTony Lindgren /* CM_AUTOIDLE_CAM */ 609c595713dSTony Lindgren #define OMAP3430_AUTO_CAM (1 << 0) 610c595713dSTony Lindgren #define OMAP3430_AUTO_CAM_SHIFT 0 611c595713dSTony Lindgren 612c595713dSTony Lindgren /* CM_CLKSEL_CAM */ 613c595713dSTony Lindgren #define OMAP3430_CLKSEL_CAM_SHIFT 0 614c595713dSTony Lindgren #define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0) 615c595713dSTony Lindgren 616c595713dSTony Lindgren /* CM_SLEEPDEP_CAM specific bits */ 617c595713dSTony Lindgren 618c595713dSTony Lindgren /* CM_CLKSTCTRL_CAM */ 619c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_CAM_SHIFT 0 620c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0) 621c595713dSTony Lindgren 622c595713dSTony Lindgren /* CM_CLKSTST_CAM */ 623801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_CAM_SHIFT 0 624801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_CAM_MASK (1 << 0) 625c595713dSTony Lindgren 626c595713dSTony Lindgren /* CM_FCLKEN_PER specific bits */ 627c595713dSTony Lindgren 628c595713dSTony Lindgren /* CM_ICLKEN_PER specific bits */ 629c595713dSTony Lindgren 630c595713dSTony Lindgren /* CM_IDLEST_PER */ 631da0747d4SPaul Walmsley #define OMAP3430_ST_WDT3_SHIFT 12 632da0747d4SPaul Walmsley #define OMAP3430_ST_WDT3_MASK (1 << 12) 633da0747d4SPaul Walmsley #define OMAP3430_ST_MCBSP4_SHIFT 2 634da0747d4SPaul Walmsley #define OMAP3430_ST_MCBSP4_MASK (1 << 2) 635da0747d4SPaul Walmsley #define OMAP3430_ST_MCBSP3_SHIFT 1 636da0747d4SPaul Walmsley #define OMAP3430_ST_MCBSP3_MASK (1 << 1) 637da0747d4SPaul Walmsley #define OMAP3430_ST_MCBSP2_SHIFT 0 638da0747d4SPaul Walmsley #define OMAP3430_ST_MCBSP2_MASK (1 << 0) 639c595713dSTony Lindgren 640c595713dSTony Lindgren /* CM_AUTOIDLE_PER */ 641c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO6 (1 << 17) 642c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO6_SHIFT 17 643c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO5 (1 << 16) 644c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO5_SHIFT 16 645c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO4 (1 << 15) 646c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO4_SHIFT 15 647c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO3 (1 << 14) 648c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO3_SHIFT 14 649c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO2 (1 << 13) 650c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO2_SHIFT 13 651c595713dSTony Lindgren #define OMAP3430_AUTO_WDT3 (1 << 12) 652c595713dSTony Lindgren #define OMAP3430_AUTO_WDT3_SHIFT 12 653c595713dSTony Lindgren #define OMAP3430_AUTO_UART3 (1 << 11) 654c595713dSTony Lindgren #define OMAP3430_AUTO_UART3_SHIFT 11 655c595713dSTony Lindgren #define OMAP3430_AUTO_GPT9 (1 << 10) 656c595713dSTony Lindgren #define OMAP3430_AUTO_GPT9_SHIFT 10 657c595713dSTony Lindgren #define OMAP3430_AUTO_GPT8 (1 << 9) 658c595713dSTony Lindgren #define OMAP3430_AUTO_GPT8_SHIFT 9 659c595713dSTony Lindgren #define OMAP3430_AUTO_GPT7 (1 << 8) 660c595713dSTony Lindgren #define OMAP3430_AUTO_GPT7_SHIFT 8 661c595713dSTony Lindgren #define OMAP3430_AUTO_GPT6 (1 << 7) 662c595713dSTony Lindgren #define OMAP3430_AUTO_GPT6_SHIFT 7 663c595713dSTony Lindgren #define OMAP3430_AUTO_GPT5 (1 << 6) 664c595713dSTony Lindgren #define OMAP3430_AUTO_GPT5_SHIFT 6 665c595713dSTony Lindgren #define OMAP3430_AUTO_GPT4 (1 << 5) 666c595713dSTony Lindgren #define OMAP3430_AUTO_GPT4_SHIFT 5 667c595713dSTony Lindgren #define OMAP3430_AUTO_GPT3 (1 << 4) 668c595713dSTony Lindgren #define OMAP3430_AUTO_GPT3_SHIFT 4 669c595713dSTony Lindgren #define OMAP3430_AUTO_GPT2 (1 << 3) 670c595713dSTony Lindgren #define OMAP3430_AUTO_GPT2_SHIFT 3 671c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP4 (1 << 2) 672c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP4_SHIFT 2 673c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP3 (1 << 1) 674c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP3_SHIFT 1 675c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP2 (1 << 0) 676c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP2_SHIFT 0 677c595713dSTony Lindgren 678c595713dSTony Lindgren /* CM_CLKSEL_PER */ 679c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT9_MASK (1 << 7) 680c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT9_SHIFT 7 681c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT8_MASK (1 << 6) 682c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT8_SHIFT 6 683c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT7_MASK (1 << 5) 684c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT7_SHIFT 5 685c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT6_MASK (1 << 4) 686c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT6_SHIFT 4 687c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT5_MASK (1 << 3) 688c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT5_SHIFT 3 689c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT4_MASK (1 << 2) 690c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT4_SHIFT 2 691c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT3_MASK (1 << 1) 692c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT3_SHIFT 1 693c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT2_MASK (1 << 0) 694c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT2_SHIFT 0 695c595713dSTony Lindgren 696c595713dSTony Lindgren /* CM_SLEEPDEP_PER specific bits */ 697c595713dSTony Lindgren #define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2 (1 << 2) 698c595713dSTony Lindgren 699c595713dSTony Lindgren /* CM_CLKSTCTRL_PER */ 700c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_PER_SHIFT 0 701c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0) 702c595713dSTony Lindgren 703c595713dSTony Lindgren /* CM_CLKSTST_PER */ 704801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_PER_SHIFT 0 705801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_PER_MASK (1 << 0) 706c595713dSTony Lindgren 707c595713dSTony Lindgren /* CM_CLKSEL1_EMU */ 708c595713dSTony Lindgren #define OMAP3430_DIV_DPLL4_SHIFT 24 709c595713dSTony Lindgren #define OMAP3430_DIV_DPLL4_MASK (0x1f << 24) 710c595713dSTony Lindgren #define OMAP3430_DIV_DPLL3_SHIFT 16 711c595713dSTony Lindgren #define OMAP3430_DIV_DPLL3_MASK (0x1f << 16) 712c595713dSTony Lindgren #define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 713c595713dSTony Lindgren #define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11) 714c595713dSTony Lindgren #define OMAP3430_CLKSEL_PCLK_SHIFT 8 715c595713dSTony Lindgren #define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8) 716c595713dSTony Lindgren #define OMAP3430_CLKSEL_PCLKX2_SHIFT 6 717c595713dSTony Lindgren #define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6) 718c595713dSTony Lindgren #define OMAP3430_CLKSEL_ATCLK_SHIFT 4 719c595713dSTony Lindgren #define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4) 720c595713dSTony Lindgren #define OMAP3430_TRACE_MUX_CTRL_SHIFT 2 721c595713dSTony Lindgren #define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2) 722c595713dSTony Lindgren #define OMAP3430_MUX_CTRL_SHIFT 0 723c595713dSTony Lindgren #define OMAP3430_MUX_CTRL_MASK (0x3 << 0) 724c595713dSTony Lindgren 725c595713dSTony Lindgren /* CM_CLKSTCTRL_EMU */ 726c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_EMU_SHIFT 0 727c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0) 728c595713dSTony Lindgren 729c595713dSTony Lindgren /* CM_CLKSTST_EMU */ 730801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_EMU_SHIFT 0 731801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_EMU_MASK (1 << 0) 732c595713dSTony Lindgren 733c595713dSTony Lindgren /* CM_CLKSEL2_EMU specific bits */ 734c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8 735c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8) 736c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0 737c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0) 738c595713dSTony Lindgren 739c595713dSTony Lindgren /* CM_CLKSEL3_EMU specific bits */ 740c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8 741c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8) 742c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0 743c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0) 744c595713dSTony Lindgren 745c595713dSTony Lindgren /* CM_POLCTRL */ 746c595713dSTony Lindgren #define OMAP3430_CLKOUT2_POL (1 << 0) 747c595713dSTony Lindgren 748c595713dSTony Lindgren /* CM_IDLEST_NEON */ 749c595713dSTony Lindgren #define OMAP3430_ST_NEON (1 << 0) 750c595713dSTony Lindgren 751c595713dSTony Lindgren /* CM_CLKSTCTRL_NEON */ 752c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_NEON_SHIFT 0 753c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0) 754c595713dSTony Lindgren 755c595713dSTony Lindgren /* CM_FCLKEN_USBHOST */ 756c595713dSTony Lindgren #define OMAP3430ES2_EN_USBHOST2_SHIFT 1 757c595713dSTony Lindgren #define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1) 758c595713dSTony Lindgren #define OMAP3430ES2_EN_USBHOST1_SHIFT 0 759c595713dSTony Lindgren #define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0) 760c595713dSTony Lindgren 761c595713dSTony Lindgren /* CM_ICLKEN_USBHOST */ 762c595713dSTony Lindgren #define OMAP3430ES2_EN_USBHOST_SHIFT 0 763c595713dSTony Lindgren #define OMAP3430ES2_EN_USBHOST_MASK (1 << 0) 764c595713dSTony Lindgren 765c595713dSTony Lindgren /* CM_IDLEST_USBHOST */ 766da0747d4SPaul Walmsley #define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1 767da0747d4SPaul Walmsley #define OMAP3430ES2_ST_USBHOST_IDLE_MASK (1 << 1) 768da0747d4SPaul Walmsley #define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0 769da0747d4SPaul Walmsley #define OMAP3430ES2_ST_USBHOST_STDBY_MASK (1 << 0) 770c595713dSTony Lindgren 771c595713dSTony Lindgren /* CM_AUTOIDLE_USBHOST */ 772c595713dSTony Lindgren #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 773c595713dSTony Lindgren #define OMAP3430ES2_AUTO_USBHOST_MASK (1 << 0) 774c595713dSTony Lindgren 775c595713dSTony Lindgren /* CM_SLEEPDEP_USBHOST */ 776c595713dSTony Lindgren #define OMAP3430ES2_EN_MPU_SHIFT 1 777c595713dSTony Lindgren #define OMAP3430ES2_EN_MPU_MASK (1 << 1) 778c595713dSTony Lindgren #define OMAP3430ES2_EN_IVA2_SHIFT 2 779c595713dSTony Lindgren #define OMAP3430ES2_EN_IVA2_MASK (1 << 2) 780c595713dSTony Lindgren 781c595713dSTony Lindgren /* CM_CLKSTCTRL_USBHOST */ 782c595713dSTony Lindgren #define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0 783c595713dSTony Lindgren #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0) 784c595713dSTony Lindgren 785801954d3SPaul Walmsley /* CM_CLKSTST_USBHOST */ 786801954d3SPaul Walmsley #define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0 787801954d3SPaul Walmsley #define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0) 788c595713dSTony Lindgren 789c595713dSTony Lindgren #endif 790