1c595713dSTony Lindgren #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
2c595713dSTony Lindgren #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
3c595713dSTony Lindgren 
4c595713dSTony Lindgren /*
5c595713dSTony Lindgren  * OMAP3430 Clock Management register bits
6c595713dSTony Lindgren  *
7c595713dSTony Lindgren  * Copyright (C) 2007-2008 Texas Instruments, Inc.
8c595713dSTony Lindgren  * Copyright (C) 2007-2008 Nokia Corporation
9c595713dSTony Lindgren  *
10c595713dSTony Lindgren  * Written by Paul Walmsley
11c595713dSTony Lindgren  *
12c595713dSTony Lindgren  * This program is free software; you can redistribute it and/or modify
13c595713dSTony Lindgren  * it under the terms of the GNU General Public License version 2 as
14c595713dSTony Lindgren  * published by the Free Software Foundation.
15c595713dSTony Lindgren  */
16c595713dSTony Lindgren 
17c595713dSTony Lindgren #include "cm.h"
18c595713dSTony Lindgren 
19c595713dSTony Lindgren /* Bits shared between registers */
20c595713dSTony Lindgren 
21c595713dSTony Lindgren /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
22c595713dSTony Lindgren #define OMAP3430ES2_EN_MMC3_MASK			(1 << 30)
23c595713dSTony Lindgren #define OMAP3430ES2_EN_MMC3_SHIFT			30
24c595713dSTony Lindgren #define OMAP3430_EN_MSPRO				(1 << 23)
25c595713dSTony Lindgren #define OMAP3430_EN_MSPRO_SHIFT				23
26c595713dSTony Lindgren #define OMAP3430_EN_HDQ					(1 << 22)
27c595713dSTony Lindgren #define OMAP3430_EN_HDQ_SHIFT				22
28c595713dSTony Lindgren #define OMAP3430ES1_EN_FSHOSTUSB			(1 << 5)
29c595713dSTony Lindgren #define OMAP3430ES1_EN_FSHOSTUSB_SHIFT			5
30c595713dSTony Lindgren #define OMAP3430ES1_EN_D2D				(1 << 3)
31c595713dSTony Lindgren #define OMAP3430ES1_EN_D2D_SHIFT			3
32c595713dSTony Lindgren #define OMAP3430_EN_SSI					(1 << 0)
33c595713dSTony Lindgren #define OMAP3430_EN_SSI_SHIFT				0
34c595713dSTony Lindgren 
35c595713dSTony Lindgren /* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */
36c595713dSTony Lindgren #define OMAP3430ES2_EN_USBTLL_SHIFT			2
37c595713dSTony Lindgren #define OMAP3430ES2_EN_USBTLL_MASK			(1 << 2)
38c595713dSTony Lindgren 
39c595713dSTony Lindgren /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
40c595713dSTony Lindgren #define OMAP3430_EN_WDT2				(1 << 5)
41c595713dSTony Lindgren #define OMAP3430_EN_WDT2_SHIFT				5
42c595713dSTony Lindgren 
43c595713dSTony Lindgren /* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */
44c595713dSTony Lindgren #define OMAP3430_EN_CAM					(1 << 0)
45c595713dSTony Lindgren #define OMAP3430_EN_CAM_SHIFT				0
46c595713dSTony Lindgren 
47c595713dSTony Lindgren /* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */
48c595713dSTony Lindgren #define OMAP3430_EN_WDT3				(1 << 12)
49c595713dSTony Lindgren #define OMAP3430_EN_WDT3_SHIFT				12
50c595713dSTony Lindgren 
51c595713dSTony Lindgren /* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */
52c595713dSTony Lindgren #define OMAP3430_OVERRIDE_ENABLE			(1 << 19)
53c595713dSTony Lindgren 
54c595713dSTony Lindgren 
55c595713dSTony Lindgren /* Bits specific to each register */
56c595713dSTony Lindgren 
57c595713dSTony Lindgren /* CM_FCLKEN_IVA2 */
58c595713dSTony Lindgren #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2			(1 << 0)
5931c203d4SHiroshi DOYU #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT		0
60c595713dSTony Lindgren 
61c595713dSTony Lindgren /* CM_CLKEN_PLL_IVA2 */
62c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT		8
63c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_RAMPTIME_MASK		(0x3 << 8)
64c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT		4
65c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_FREQSEL_MASK			(0xf << 4)
66c595713dSTony Lindgren #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT		3
67c595713dSTony Lindgren #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK		(1 << 3)
68c595713dSTony Lindgren #define OMAP3430_EN_IVA2_DPLL_SHIFT			0
69c595713dSTony Lindgren #define OMAP3430_EN_IVA2_DPLL_MASK			(0x7 << 0)
70c595713dSTony Lindgren 
71c595713dSTony Lindgren /* CM_IDLEST_IVA2 */
72c595713dSTony Lindgren #define OMAP3430_ST_IVA2				(1 << 0)
73c595713dSTony Lindgren 
74c595713dSTony Lindgren /* CM_IDLEST_PLL_IVA2 */
75542313ccSPaul Walmsley #define OMAP3430_ST_IVA2_CLK_SHIFT			0
76542313ccSPaul Walmsley #define OMAP3430_ST_IVA2_CLK_MASK			(1 << 0)
77c595713dSTony Lindgren 
78c595713dSTony Lindgren /* CM_AUTOIDLE_PLL_IVA2 */
79c595713dSTony Lindgren #define OMAP3430_AUTO_IVA2_DPLL_SHIFT			0
80c595713dSTony Lindgren #define OMAP3430_AUTO_IVA2_DPLL_MASK			(0x7 << 0)
81c595713dSTony Lindgren 
82c595713dSTony Lindgren /* CM_CLKSEL1_PLL_IVA2 */
83c595713dSTony Lindgren #define OMAP3430_IVA2_CLK_SRC_SHIFT			19
84c595713dSTony Lindgren #define OMAP3430_IVA2_CLK_SRC_MASK			(0x3 << 19)
85c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_MULT_SHIFT			8
86c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_MULT_MASK			(0x7ff << 8)
87c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_DIV_SHIFT			0
88c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_DIV_MASK			(0x7f << 0)
89c595713dSTony Lindgren 
90c595713dSTony Lindgren /* CM_CLKSEL2_PLL_IVA2 */
91c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT		0
92c595713dSTony Lindgren #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK		(0x1f << 0)
93c595713dSTony Lindgren 
94c595713dSTony Lindgren /* CM_CLKSTCTRL_IVA2 */
95c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_IVA2_SHIFT			0
96c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_IVA2_MASK			(0x3 << 0)
97c595713dSTony Lindgren 
98c595713dSTony Lindgren /* CM_CLKSTST_IVA2 */
99801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_IVA2_SHIFT			0
100801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_IVA2_MASK			(1 << 0)
101c595713dSTony Lindgren 
102c595713dSTony Lindgren /* CM_REVISION specific bits */
103c595713dSTony Lindgren 
104c595713dSTony Lindgren /* CM_SYSCONFIG specific bits */
105c595713dSTony Lindgren 
106c595713dSTony Lindgren /* CM_CLKEN_PLL_MPU */
107c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT		8
108c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_RAMPTIME_MASK			(0x3 << 8)
109c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_FREQSEL_SHIFT			4
110c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_FREQSEL_MASK			(0xf << 4)
111c595713dSTony Lindgren #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT		3
112c595713dSTony Lindgren #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK		(1 << 3)
113c595713dSTony Lindgren #define OMAP3430_EN_MPU_DPLL_SHIFT			0
114c595713dSTony Lindgren #define OMAP3430_EN_MPU_DPLL_MASK			(0x7 << 0)
115c595713dSTony Lindgren 
116c595713dSTony Lindgren /* CM_IDLEST_MPU */
117c595713dSTony Lindgren #define OMAP3430_ST_MPU					(1 << 0)
118c595713dSTony Lindgren 
119c595713dSTony Lindgren /* CM_IDLEST_PLL_MPU */
120542313ccSPaul Walmsley #define OMAP3430_ST_MPU_CLK_SHIFT			0
1213760d31fSRoman Tereshonkov #define OMAP3430_ST_MPU_CLK_MASK			(1 << 0)
122c595713dSTony Lindgren 
123c595713dSTony Lindgren /* CM_AUTOIDLE_PLL_MPU */
124c595713dSTony Lindgren #define OMAP3430_AUTO_MPU_DPLL_SHIFT			0
125c595713dSTony Lindgren #define OMAP3430_AUTO_MPU_DPLL_MASK			(0x7 << 0)
126c595713dSTony Lindgren 
127c595713dSTony Lindgren /* CM_CLKSEL1_PLL_MPU */
128c595713dSTony Lindgren #define OMAP3430_MPU_CLK_SRC_SHIFT			19
129c595713dSTony Lindgren #define OMAP3430_MPU_CLK_SRC_MASK			(0x3 << 19)
130c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_MULT_SHIFT			8
131c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_MULT_MASK			(0x7ff << 8)
132c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_DIV_SHIFT			0
133c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_DIV_MASK			(0x7f << 0)
134c595713dSTony Lindgren 
135c595713dSTony Lindgren /* CM_CLKSEL2_PLL_MPU */
136c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT		0
137c595713dSTony Lindgren #define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK		(0x1f << 0)
138c595713dSTony Lindgren 
139c595713dSTony Lindgren /* CM_CLKSTCTRL_MPU */
140c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_MPU_SHIFT			0
141c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_MPU_MASK			(0x3 << 0)
142c595713dSTony Lindgren 
143c595713dSTony Lindgren /* CM_CLKSTST_MPU */
144801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_MPU_SHIFT			0
145801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_MPU_MASK			(1 << 0)
146c595713dSTony Lindgren 
147c595713dSTony Lindgren /* CM_FCLKEN1_CORE specific bits */
148c595713dSTony Lindgren 
149c595713dSTony Lindgren /* CM_ICLKEN1_CORE specific bits */
150c595713dSTony Lindgren #define OMAP3430_EN_ICR					(1 << 29)
151c595713dSTony Lindgren #define OMAP3430_EN_ICR_SHIFT				29
152c595713dSTony Lindgren #define OMAP3430_EN_AES2				(1 << 28)
153c595713dSTony Lindgren #define OMAP3430_EN_AES2_SHIFT				28
154c595713dSTony Lindgren #define OMAP3430_EN_SHA12				(1 << 27)
155c595713dSTony Lindgren #define OMAP3430_EN_SHA12_SHIFT				27
156c595713dSTony Lindgren #define OMAP3430_EN_DES2				(1 << 26)
157c595713dSTony Lindgren #define OMAP3430_EN_DES2_SHIFT				26
158c595713dSTony Lindgren #define OMAP3430ES1_EN_FAC				(1 << 8)
159c595713dSTony Lindgren #define OMAP3430ES1_EN_FAC_SHIFT			8
160c595713dSTony Lindgren #define OMAP3430_EN_MAILBOXES				(1 << 7)
161c595713dSTony Lindgren #define OMAP3430_EN_MAILBOXES_SHIFT			7
162c595713dSTony Lindgren #define OMAP3430_EN_OMAPCTRL				(1 << 6)
163c595713dSTony Lindgren #define OMAP3430_EN_OMAPCTRL_SHIFT			6
164c595713dSTony Lindgren #define OMAP3430_EN_SDRC				(1 << 1)
165c595713dSTony Lindgren #define OMAP3430_EN_SDRC_SHIFT				1
166c595713dSTony Lindgren 
167c595713dSTony Lindgren /* CM_ICLKEN2_CORE */
168c595713dSTony Lindgren #define OMAP3430_EN_PKA					(1 << 4)
169c595713dSTony Lindgren #define OMAP3430_EN_PKA_SHIFT				4
170c595713dSTony Lindgren #define OMAP3430_EN_AES1				(1 << 3)
171c595713dSTony Lindgren #define OMAP3430_EN_AES1_SHIFT				3
172c595713dSTony Lindgren #define OMAP3430_EN_RNG					(1 << 2)
173c595713dSTony Lindgren #define OMAP3430_EN_RNG_SHIFT				2
174c595713dSTony Lindgren #define OMAP3430_EN_SHA11				(1 << 1)
175c595713dSTony Lindgren #define OMAP3430_EN_SHA11_SHIFT				1
176c595713dSTony Lindgren #define OMAP3430_EN_DES1				(1 << 0)
177c595713dSTony Lindgren #define OMAP3430_EN_DES1_SHIFT				0
178c595713dSTony Lindgren 
179c595713dSTony Lindgren /* CM_FCLKEN3_CORE specific bits */
180c595713dSTony Lindgren #define OMAP3430ES2_EN_TS_SHIFT				1
181c595713dSTony Lindgren #define OMAP3430ES2_EN_TS_MASK				(1 << 1)
182c595713dSTony Lindgren #define OMAP3430ES2_EN_CPEFUSE_SHIFT			0
183c595713dSTony Lindgren #define OMAP3430ES2_EN_CPEFUSE_MASK			(1 << 0)
184c595713dSTony Lindgren 
185c595713dSTony Lindgren /* CM_IDLEST1_CORE specific bits */
186c595713dSTony Lindgren #define OMAP3430_ST_ICR					(1 << 29)
187c595713dSTony Lindgren #define OMAP3430_ST_AES2				(1 << 28)
188c595713dSTony Lindgren #define OMAP3430_ST_SHA12				(1 << 27)
189c595713dSTony Lindgren #define OMAP3430_ST_DES2				(1 << 26)
190c595713dSTony Lindgren #define OMAP3430_ST_MSPRO				(1 << 23)
191c595713dSTony Lindgren #define OMAP3430_ST_HDQ					(1 << 22)
192c595713dSTony Lindgren #define OMAP3430ES1_ST_FAC				(1 << 8)
193c595713dSTony Lindgren #define OMAP3430ES1_ST_MAILBOXES			(1 << 7)
194c595713dSTony Lindgren #define OMAP3430_ST_OMAPCTRL				(1 << 6)
195c595713dSTony Lindgren #define OMAP3430_ST_SDMA				(1 << 2)
196c595713dSTony Lindgren #define OMAP3430_ST_SDRC				(1 << 1)
197c595713dSTony Lindgren #define OMAP3430_ST_SSI					(1 << 0)
198c595713dSTony Lindgren 
199c595713dSTony Lindgren /* CM_IDLEST2_CORE */
200c595713dSTony Lindgren #define OMAP3430_ST_PKA					(1 << 4)
201c595713dSTony Lindgren #define OMAP3430_ST_AES1				(1 << 3)
202c595713dSTony Lindgren #define OMAP3430_ST_RNG					(1 << 2)
203c595713dSTony Lindgren #define OMAP3430_ST_SHA11				(1 << 1)
204c595713dSTony Lindgren #define OMAP3430_ST_DES1				(1 << 0)
205c595713dSTony Lindgren 
206c595713dSTony Lindgren /* CM_IDLEST3_CORE */
207c595713dSTony Lindgren #define OMAP3430ES2_ST_USBTLL_SHIFT			2
208c595713dSTony Lindgren #define OMAP3430ES2_ST_USBTLL_MASK			(1 << 2)
209c595713dSTony Lindgren 
210c595713dSTony Lindgren /* CM_AUTOIDLE1_CORE */
211027d8dedSJouni Hogander #define OMAP3430ES2_AUTO_MMC3				(1 << 30)
212027d8dedSJouni Hogander #define OMAP3430ES2_AUTO_MMC3_SHIFT			30
213027d8dedSJouni Hogander #define OMAP3430ES2_AUTO_ICR				(1 << 29)
214027d8dedSJouni Hogander #define OMAP3430ES2_AUTO_ICR_SHIFT			29
215c595713dSTony Lindgren #define OMAP3430_AUTO_AES2				(1 << 28)
216c595713dSTony Lindgren #define OMAP3430_AUTO_AES2_SHIFT			28
217c595713dSTony Lindgren #define OMAP3430_AUTO_SHA12				(1 << 27)
218c595713dSTony Lindgren #define OMAP3430_AUTO_SHA12_SHIFT			27
219c595713dSTony Lindgren #define OMAP3430_AUTO_DES2				(1 << 26)
220c595713dSTony Lindgren #define OMAP3430_AUTO_DES2_SHIFT			26
221c595713dSTony Lindgren #define OMAP3430_AUTO_MMC2				(1 << 25)
222c595713dSTony Lindgren #define OMAP3430_AUTO_MMC2_SHIFT			25
223c595713dSTony Lindgren #define OMAP3430_AUTO_MMC1				(1 << 24)
224c595713dSTony Lindgren #define OMAP3430_AUTO_MMC1_SHIFT			24
225c595713dSTony Lindgren #define OMAP3430_AUTO_MSPRO				(1 << 23)
226c595713dSTony Lindgren #define OMAP3430_AUTO_MSPRO_SHIFT			23
227c595713dSTony Lindgren #define OMAP3430_AUTO_HDQ				(1 << 22)
228c595713dSTony Lindgren #define OMAP3430_AUTO_HDQ_SHIFT				22
229c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI4				(1 << 21)
230c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI4_SHIFT			21
231c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI3				(1 << 20)
232c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI3_SHIFT			20
233c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI2				(1 << 19)
234c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI2_SHIFT			19
235c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI1				(1 << 18)
236c595713dSTony Lindgren #define OMAP3430_AUTO_MCSPI1_SHIFT			18
237c595713dSTony Lindgren #define OMAP3430_AUTO_I2C3				(1 << 17)
238c595713dSTony Lindgren #define OMAP3430_AUTO_I2C3_SHIFT			17
239c595713dSTony Lindgren #define OMAP3430_AUTO_I2C2				(1 << 16)
240c595713dSTony Lindgren #define OMAP3430_AUTO_I2C2_SHIFT			16
241c595713dSTony Lindgren #define OMAP3430_AUTO_I2C1				(1 << 15)
242c595713dSTony Lindgren #define OMAP3430_AUTO_I2C1_SHIFT			15
243c595713dSTony Lindgren #define OMAP3430_AUTO_UART2				(1 << 14)
244c595713dSTony Lindgren #define OMAP3430_AUTO_UART2_SHIFT			14
245c595713dSTony Lindgren #define OMAP3430_AUTO_UART1				(1 << 13)
246c595713dSTony Lindgren #define OMAP3430_AUTO_UART1_SHIFT			13
247c595713dSTony Lindgren #define OMAP3430_AUTO_GPT11				(1 << 12)
248c595713dSTony Lindgren #define OMAP3430_AUTO_GPT11_SHIFT			12
249c595713dSTony Lindgren #define OMAP3430_AUTO_GPT10				(1 << 11)
250c595713dSTony Lindgren #define OMAP3430_AUTO_GPT10_SHIFT			11
251c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP5				(1 << 10)
252c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP5_SHIFT			10
253c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP1				(1 << 9)
254c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP1_SHIFT			9
255c595713dSTony Lindgren #define OMAP3430ES1_AUTO_FAC				(1 << 8)
256c595713dSTony Lindgren #define OMAP3430ES1_AUTO_FAC_SHIFT			8
257c595713dSTony Lindgren #define OMAP3430_AUTO_MAILBOXES				(1 << 7)
258c595713dSTony Lindgren #define OMAP3430_AUTO_MAILBOXES_SHIFT			7
259c595713dSTony Lindgren #define OMAP3430_AUTO_OMAPCTRL				(1 << 6)
260c595713dSTony Lindgren #define OMAP3430_AUTO_OMAPCTRL_SHIFT			6
261c595713dSTony Lindgren #define OMAP3430ES1_AUTO_FSHOSTUSB			(1 << 5)
262c595713dSTony Lindgren #define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT		5
263c595713dSTony Lindgren #define OMAP3430_AUTO_HSOTGUSB				(1 << 4)
264c595713dSTony Lindgren #define OMAP3430_AUTO_HSOTGUSB_SHIFT			4
265c595713dSTony Lindgren #define OMAP3430ES1_AUTO_D2D				(1 << 3)
266c595713dSTony Lindgren #define OMAP3430ES1_AUTO_D2D_SHIFT			3
267c595713dSTony Lindgren #define OMAP3430_AUTO_SSI				(1 << 0)
268c595713dSTony Lindgren #define OMAP3430_AUTO_SSI_SHIFT				0
269c595713dSTony Lindgren 
270c595713dSTony Lindgren /* CM_AUTOIDLE2_CORE */
271c595713dSTony Lindgren #define OMAP3430_AUTO_PKA				(1 << 4)
272c595713dSTony Lindgren #define OMAP3430_AUTO_PKA_SHIFT				4
273c595713dSTony Lindgren #define OMAP3430_AUTO_AES1				(1 << 3)
274c595713dSTony Lindgren #define OMAP3430_AUTO_AES1_SHIFT			3
275c595713dSTony Lindgren #define OMAP3430_AUTO_RNG				(1 << 2)
276c595713dSTony Lindgren #define OMAP3430_AUTO_RNG_SHIFT				2
277c595713dSTony Lindgren #define OMAP3430_AUTO_SHA11				(1 << 1)
278c595713dSTony Lindgren #define OMAP3430_AUTO_SHA11_SHIFT			1
279c595713dSTony Lindgren #define OMAP3430_AUTO_DES1				(1 << 0)
280c595713dSTony Lindgren #define OMAP3430_AUTO_DES1_SHIFT			0
281c595713dSTony Lindgren 
282c595713dSTony Lindgren /* CM_AUTOIDLE3_CORE */
283027d8dedSJouni Hogander #define	OMAP3430ES2_AUTO_USBHOST			(1 << 0)
284027d8dedSJouni Hogander #define	OMAP3430ES2_AUTO_USBHOST_SHIFT			0
285027d8dedSJouni Hogander #define	OMAP3430ES2_AUTO_USBTLL				(1 << 2)
286c595713dSTony Lindgren #define OMAP3430ES2_AUTO_USBTLL_SHIFT			2
287c595713dSTony Lindgren #define OMAP3430ES2_AUTO_USBTLL_MASK			(1 << 2)
288c595713dSTony Lindgren 
289c595713dSTony Lindgren /* CM_CLKSEL_CORE */
290c595713dSTony Lindgren #define OMAP3430_CLKSEL_SSI_SHIFT			8
291c595713dSTony Lindgren #define OMAP3430_CLKSEL_SSI_MASK			(0xf << 8)
292c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT11_MASK			(1 << 7)
293c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT11_SHIFT			7
294c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT10_MASK			(1 << 6)
295c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT10_SHIFT			6
296c595713dSTony Lindgren #define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT		4
297c595713dSTony Lindgren #define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK		(0x3 << 4)
298c595713dSTony Lindgren #define OMAP3430_CLKSEL_L4_SHIFT			2
299c595713dSTony Lindgren #define OMAP3430_CLKSEL_L4_MASK				(0x3 << 2)
300c595713dSTony Lindgren #define OMAP3430_CLKSEL_L3_SHIFT			0
301c595713dSTony Lindgren #define OMAP3430_CLKSEL_L3_MASK				(0x3 << 0)
302c595713dSTony Lindgren 
303c595713dSTony Lindgren /* CM_CLKSTCTRL_CORE */
304c595713dSTony Lindgren #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT			4
305c595713dSTony Lindgren #define OMAP3430ES1_CLKTRCTRL_D2D_MASK			(0x3 << 4)
306c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_L4_SHIFT			2
307c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_L4_MASK			(0x3 << 2)
308c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_L3_SHIFT			0
309c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_L3_MASK			(0x3 << 0)
310c595713dSTony Lindgren 
311c595713dSTony Lindgren /* CM_CLKSTST_CORE */
312801954d3SPaul Walmsley #define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT		2
313801954d3SPaul Walmsley #define OMAP3430ES1_CLKACTIVITY_D2D_MASK		(1 << 2)
314801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_L4_SHIFT			1
315801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_L4_MASK			(1 << 1)
316801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_L3_SHIFT			0
317801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_L3_MASK			(1 << 0)
318c595713dSTony Lindgren 
319c595713dSTony Lindgren /* CM_FCLKEN_GFX */
320c595713dSTony Lindgren #define OMAP3430ES1_EN_3D				(1 << 2)
321c595713dSTony Lindgren #define OMAP3430ES1_EN_3D_SHIFT				2
322c595713dSTony Lindgren #define OMAP3430ES1_EN_2D				(1 << 1)
323c595713dSTony Lindgren #define OMAP3430ES1_EN_2D_SHIFT				1
324c595713dSTony Lindgren 
325c595713dSTony Lindgren /* CM_ICLKEN_GFX specific bits */
326c595713dSTony Lindgren 
327c595713dSTony Lindgren /* CM_IDLEST_GFX specific bits */
328c595713dSTony Lindgren 
329c595713dSTony Lindgren /* CM_CLKSEL_GFX specific bits */
330c595713dSTony Lindgren 
331c595713dSTony Lindgren /* CM_SLEEPDEP_GFX specific bits */
332c595713dSTony Lindgren 
333c595713dSTony Lindgren /* CM_CLKSTCTRL_GFX */
334c595713dSTony Lindgren #define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT			0
335c595713dSTony Lindgren #define OMAP3430ES1_CLKTRCTRL_GFX_MASK			(0x3 << 0)
336c595713dSTony Lindgren 
337c595713dSTony Lindgren /* CM_CLKSTST_GFX */
338801954d3SPaul Walmsley #define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT		0
339801954d3SPaul Walmsley #define OMAP3430ES1_CLKACTIVITY_GFX_MASK		(1 << 0)
340c595713dSTony Lindgren 
341c595713dSTony Lindgren /* CM_FCLKEN_SGX */
342712d7c86SDaniel Stone #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT		1
343712d7c86SDaniel Stone #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK		(1 << 1)
344712d7c86SDaniel Stone 
345712d7c86SDaniel Stone /* CM_ICLKEN_SGX */
346712d7c86SDaniel Stone #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT		0
347712d7c86SDaniel Stone #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK		(1 << 0)
348c595713dSTony Lindgren 
349c595713dSTony Lindgren /* CM_CLKSEL_SGX */
350c595713dSTony Lindgren #define OMAP3430ES2_CLKSEL_SGX_SHIFT			0
351c595713dSTony Lindgren #define OMAP3430ES2_CLKSEL_SGX_MASK			(0x7 << 0)
352c595713dSTony Lindgren 
353801954d3SPaul Walmsley /* CM_CLKSTCTRL_SGX */
354801954d3SPaul Walmsley #define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT			0
355801954d3SPaul Walmsley #define OMAP3430ES2_CLKTRCTRL_SGX_MASK			(0x3 << 0)
356801954d3SPaul Walmsley 
357801954d3SPaul Walmsley /* CM_CLKSTST_SGX */
358801954d3SPaul Walmsley #define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT		0
359801954d3SPaul Walmsley #define OMAP3430ES2_CLKACTIVITY_SGX_MASK		(1 << 0)
360801954d3SPaul Walmsley 
361c595713dSTony Lindgren /* CM_FCLKEN_WKUP specific bits */
362c595713dSTony Lindgren #define OMAP3430ES2_EN_USIMOCP_SHIFT			9
363c595713dSTony Lindgren 
364c595713dSTony Lindgren /* CM_ICLKEN_WKUP specific bits */
365c595713dSTony Lindgren #define OMAP3430_EN_WDT1				(1 << 4)
366c595713dSTony Lindgren #define OMAP3430_EN_WDT1_SHIFT				4
367c595713dSTony Lindgren #define OMAP3430_EN_32KSYNC				(1 << 2)
368c595713dSTony Lindgren #define OMAP3430_EN_32KSYNC_SHIFT			2
369c595713dSTony Lindgren 
370c595713dSTony Lindgren /* CM_IDLEST_WKUP specific bits */
371c595713dSTony Lindgren #define OMAP3430_ST_WDT2				(1 << 5)
372c595713dSTony Lindgren #define OMAP3430_ST_WDT1				(1 << 4)
373c595713dSTony Lindgren #define OMAP3430_ST_32KSYNC				(1 << 2)
374c595713dSTony Lindgren 
375c595713dSTony Lindgren /* CM_AUTOIDLE_WKUP */
376c595713dSTony Lindgren #define OMAP3430_AUTO_WDT2				(1 << 5)
377c595713dSTony Lindgren #define OMAP3430_AUTO_WDT2_SHIFT			5
378c595713dSTony Lindgren #define OMAP3430_AUTO_WDT1				(1 << 4)
379c595713dSTony Lindgren #define OMAP3430_AUTO_WDT1_SHIFT			4
380c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO1				(1 << 3)
381c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO1_SHIFT			3
382c595713dSTony Lindgren #define OMAP3430_AUTO_32KSYNC				(1 << 2)
383c595713dSTony Lindgren #define OMAP3430_AUTO_32KSYNC_SHIFT			2
384c595713dSTony Lindgren #define OMAP3430_AUTO_GPT12				(1 << 1)
385c595713dSTony Lindgren #define OMAP3430_AUTO_GPT12_SHIFT			1
386c595713dSTony Lindgren #define OMAP3430_AUTO_GPT1				(1 << 0)
387c595713dSTony Lindgren #define OMAP3430_AUTO_GPT1_SHIFT			0
388c595713dSTony Lindgren 
389c595713dSTony Lindgren /* CM_CLKSEL_WKUP */
390c595713dSTony Lindgren #define OMAP3430ES2_CLKSEL_USIMOCP_MASK			(0xf << 3)
391c595713dSTony Lindgren #define OMAP3430_CLKSEL_RM_SHIFT			1
392c595713dSTony Lindgren #define OMAP3430_CLKSEL_RM_MASK				(0x3 << 1)
393c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT1_SHIFT			0
394c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT1_MASK			(1 << 0)
395c595713dSTony Lindgren 
396c595713dSTony Lindgren /* CM_CLKEN_PLL */
397c595713dSTony Lindgren #define OMAP3430_PWRDN_EMU_PERIPH_SHIFT			31
398c595713dSTony Lindgren #define OMAP3430_PWRDN_CAM_SHIFT			30
399c595713dSTony Lindgren #define OMAP3430_PWRDN_DSS1_SHIFT			29
400c595713dSTony Lindgren #define OMAP3430_PWRDN_TV_SHIFT				28
401c595713dSTony Lindgren #define OMAP3430_PWRDN_96M_SHIFT			27
402c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT		24
403c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK		(0x3 << 24)
404c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT		20
405c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_FREQSEL_MASK		(0xf << 20)
406c595713dSTony Lindgren #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT	19
407c595713dSTony Lindgren #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK		(1 << 19)
408c595713dSTony Lindgren #define OMAP3430_EN_PERIPH_DPLL_SHIFT			16
409c595713dSTony Lindgren #define OMAP3430_EN_PERIPH_DPLL_MASK			(0x7 << 16)
410c595713dSTony Lindgren #define OMAP3430_PWRDN_EMU_CORE_SHIFT			12
411c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT		8
412c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_RAMPTIME_MASK		(0x3 << 8)
413c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_FREQSEL_SHIFT		4
414c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_FREQSEL_MASK			(0xf << 4)
415c595713dSTony Lindgren #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT		3
416c595713dSTony Lindgren #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK		(1 << 3)
417c595713dSTony Lindgren #define OMAP3430_EN_CORE_DPLL_SHIFT			0
418c595713dSTony Lindgren #define OMAP3430_EN_CORE_DPLL_MASK			(0x7 << 0)
419c595713dSTony Lindgren 
420c595713dSTony Lindgren /* CM_CLKEN2_PLL */
421c595713dSTony Lindgren #define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT		10
422c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK		(0x3 << 8)
423c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT		4
424c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK		(0xf << 4)
425c595713dSTony Lindgren #define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT	3
426c595713dSTony Lindgren #define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT		0
427c595713dSTony Lindgren #define OMAP3430ES2_EN_PERIPH2_DPLL_MASK		(0x7 << 0)
428c595713dSTony Lindgren 
429c595713dSTony Lindgren /* CM_IDLEST_CKGEN */
430c595713dSTony Lindgren #define OMAP3430_ST_54M_CLK				(1 << 5)
431c595713dSTony Lindgren #define OMAP3430_ST_12M_CLK				(1 << 4)
432c595713dSTony Lindgren #define OMAP3430_ST_48M_CLK				(1 << 3)
433c595713dSTony Lindgren #define OMAP3430_ST_96M_CLK				(1 << 2)
434542313ccSPaul Walmsley #define OMAP3430_ST_PERIPH_CLK_SHIFT			1
435542313ccSPaul Walmsley #define OMAP3430_ST_PERIPH_CLK_MASK			(1 << 1)
436542313ccSPaul Walmsley #define OMAP3430_ST_CORE_CLK_SHIFT			0
437542313ccSPaul Walmsley #define OMAP3430_ST_CORE_CLK_MASK			(1 << 0)
438c595713dSTony Lindgren 
439c595713dSTony Lindgren /* CM_IDLEST2_CKGEN */
440c595713dSTony Lindgren #define OMAP3430ES2_ST_120M_CLK_SHIFT			1
441c595713dSTony Lindgren #define OMAP3430ES2_ST_120M_CLK_MASK			(1 << 1)
442c595713dSTony Lindgren #define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT		0
443c595713dSTony Lindgren #define OMAP3430ES2_ST_PERIPH2_CLK_MASK			(1 << 0)
444c595713dSTony Lindgren 
445c595713dSTony Lindgren /* CM_AUTOIDLE_PLL */
446c595713dSTony Lindgren #define OMAP3430_AUTO_PERIPH_DPLL_SHIFT			3
447c595713dSTony Lindgren #define OMAP3430_AUTO_PERIPH_DPLL_MASK			(0x7 << 3)
448c595713dSTony Lindgren #define OMAP3430_AUTO_CORE_DPLL_SHIFT			0
449c595713dSTony Lindgren #define OMAP3430_AUTO_CORE_DPLL_MASK			(0x7 << 0)
450c595713dSTony Lindgren 
451542313ccSPaul Walmsley /* CM_AUTOIDLE2_PLL */
452542313ccSPaul Walmsley #define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT		0
453542313ccSPaul Walmsley #define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK		(0x7 << 0)
454542313ccSPaul Walmsley 
455c595713dSTony Lindgren /* CM_CLKSEL1_PLL */
456c595713dSTony Lindgren /* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */
457c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT		27
458c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK		(0x1f << 27)
459c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_MULT_SHIFT			16
460c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_MULT_MASK			(0x7ff << 16)
461c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_DIV_SHIFT			8
462c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_DIV_MASK			(0x7f << 8)
4639cfd985eSPaul Walmsley #define OMAP3430_SOURCE_96M_SHIFT			6
4649cfd985eSPaul Walmsley #define OMAP3430_SOURCE_96M_MASK			(1 << 6)
4659cfd985eSPaul Walmsley #define OMAP3430_SOURCE_54M_SHIFT			5
4669cfd985eSPaul Walmsley #define OMAP3430_SOURCE_54M_MASK			(1 << 5)
4679cfd985eSPaul Walmsley #define OMAP3430_SOURCE_48M_SHIFT			3
4689cfd985eSPaul Walmsley #define OMAP3430_SOURCE_48M_MASK			(1 << 3)
469c595713dSTony Lindgren 
470c595713dSTony Lindgren /* CM_CLKSEL2_PLL */
471c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_MULT_SHIFT			8
472c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_MULT_MASK			(0x7ff << 8)
473c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_DIV_SHIFT			0
474c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_DIV_MASK			(0x7f << 0)
475c595713dSTony Lindgren 
476c595713dSTony Lindgren /* CM_CLKSEL3_PLL */
477c595713dSTony Lindgren #define OMAP3430_DIV_96M_SHIFT				0
478c595713dSTony Lindgren #define OMAP3430_DIV_96M_MASK				(0x1f << 0)
479c595713dSTony Lindgren 
480c595713dSTony Lindgren /* CM_CLKSEL4_PLL */
481c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT		8
482c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK		(0x7ff << 8)
483c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT		0
484c595713dSTony Lindgren #define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK		(0x7f << 0)
485c595713dSTony Lindgren 
486c595713dSTony Lindgren /* CM_CLKSEL5_PLL */
487c595713dSTony Lindgren #define OMAP3430ES2_DIV_120M_SHIFT			0
488c595713dSTony Lindgren #define OMAP3430ES2_DIV_120M_MASK			(0x1f << 0)
489c595713dSTony Lindgren 
490c595713dSTony Lindgren /* CM_CLKOUT_CTRL */
491c595713dSTony Lindgren #define OMAP3430_CLKOUT2_EN_SHIFT			7
492c595713dSTony Lindgren #define OMAP3430_CLKOUT2_EN				(1 << 7)
493c595713dSTony Lindgren #define OMAP3430_CLKOUT2_DIV_SHIFT			3
494c595713dSTony Lindgren #define OMAP3430_CLKOUT2_DIV_MASK			(0x7 << 3)
495c595713dSTony Lindgren #define OMAP3430_CLKOUT2SOURCE_SHIFT			0
496c595713dSTony Lindgren #define OMAP3430_CLKOUT2SOURCE_MASK			(0x3 << 0)
497c595713dSTony Lindgren 
498c595713dSTony Lindgren /* CM_FCLKEN_DSS */
499c595713dSTony Lindgren #define OMAP3430_EN_TV					(1 << 2)
500c595713dSTony Lindgren #define OMAP3430_EN_TV_SHIFT				2
501c595713dSTony Lindgren #define OMAP3430_EN_DSS2				(1 << 1)
502c595713dSTony Lindgren #define OMAP3430_EN_DSS2_SHIFT				1
503c595713dSTony Lindgren #define OMAP3430_EN_DSS1				(1 << 0)
504c595713dSTony Lindgren #define OMAP3430_EN_DSS1_SHIFT				0
505c595713dSTony Lindgren 
506c595713dSTony Lindgren /* CM_ICLKEN_DSS */
507c595713dSTony Lindgren #define OMAP3430_CM_ICLKEN_DSS_EN_DSS			(1 << 0)
508c595713dSTony Lindgren #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT		0
509c595713dSTony Lindgren 
510c595713dSTony Lindgren /* CM_IDLEST_DSS */
511c595713dSTony Lindgren #define OMAP3430_ST_DSS					(1 << 0)
512c595713dSTony Lindgren 
513c595713dSTony Lindgren /* CM_AUTOIDLE_DSS */
514c595713dSTony Lindgren #define OMAP3430_AUTO_DSS				(1 << 0)
515c595713dSTony Lindgren #define OMAP3430_AUTO_DSS_SHIFT				0
516c595713dSTony Lindgren 
517c595713dSTony Lindgren /* CM_CLKSEL_DSS */
518c595713dSTony Lindgren #define OMAP3430_CLKSEL_TV_SHIFT			8
519c595713dSTony Lindgren #define OMAP3430_CLKSEL_TV_MASK				(0x1f << 8)
520c595713dSTony Lindgren #define OMAP3430_CLKSEL_DSS1_SHIFT			0
521c595713dSTony Lindgren #define OMAP3430_CLKSEL_DSS1_MASK			(0x1f << 0)
522c595713dSTony Lindgren 
523c595713dSTony Lindgren /* CM_SLEEPDEP_DSS specific bits */
524c595713dSTony Lindgren 
525c595713dSTony Lindgren /* CM_CLKSTCTRL_DSS */
526c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_DSS_SHIFT			0
527c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_DSS_MASK			(0x3 << 0)
528c595713dSTony Lindgren 
529c595713dSTony Lindgren /* CM_CLKSTST_DSS */
530801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_DSS_SHIFT			0
531801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_DSS_MASK			(1 << 0)
532c595713dSTony Lindgren 
533c595713dSTony Lindgren /* CM_FCLKEN_CAM specific bits */
5346c8fe0b9SSergio Aguirre #define OMAP3430_EN_CSI2				(1 << 1)
5356c8fe0b9SSergio Aguirre #define OMAP3430_EN_CSI2_SHIFT				1
536c595713dSTony Lindgren 
537c595713dSTony Lindgren /* CM_ICLKEN_CAM specific bits */
538c595713dSTony Lindgren 
539c595713dSTony Lindgren /* CM_IDLEST_CAM */
540c595713dSTony Lindgren #define OMAP3430_ST_CAM					(1 << 0)
541c595713dSTony Lindgren 
542c595713dSTony Lindgren /* CM_AUTOIDLE_CAM */
543c595713dSTony Lindgren #define OMAP3430_AUTO_CAM				(1 << 0)
544c595713dSTony Lindgren #define OMAP3430_AUTO_CAM_SHIFT				0
545c595713dSTony Lindgren 
546c595713dSTony Lindgren /* CM_CLKSEL_CAM */
547c595713dSTony Lindgren #define OMAP3430_CLKSEL_CAM_SHIFT			0
548c595713dSTony Lindgren #define OMAP3430_CLKSEL_CAM_MASK			(0x1f << 0)
549c595713dSTony Lindgren 
550c595713dSTony Lindgren /* CM_SLEEPDEP_CAM specific bits */
551c595713dSTony Lindgren 
552c595713dSTony Lindgren /* CM_CLKSTCTRL_CAM */
553c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_CAM_SHIFT			0
554c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_CAM_MASK			(0x3 << 0)
555c595713dSTony Lindgren 
556c595713dSTony Lindgren /* CM_CLKSTST_CAM */
557801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_CAM_SHIFT			0
558801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_CAM_MASK			(1 << 0)
559c595713dSTony Lindgren 
560c595713dSTony Lindgren /* CM_FCLKEN_PER specific bits */
561c595713dSTony Lindgren 
562c595713dSTony Lindgren /* CM_ICLKEN_PER specific bits */
563c595713dSTony Lindgren 
564c595713dSTony Lindgren /* CM_IDLEST_PER */
565c595713dSTony Lindgren #define OMAP3430_ST_WDT3				(1 << 12)
566c595713dSTony Lindgren #define OMAP3430_ST_MCBSP4				(1 << 2)
567c595713dSTony Lindgren #define OMAP3430_ST_MCBSP3				(1 << 1)
568c595713dSTony Lindgren #define OMAP3430_ST_MCBSP2				(1 << 0)
569c595713dSTony Lindgren 
570c595713dSTony Lindgren /* CM_AUTOIDLE_PER */
571c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO6				(1 << 17)
572c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO6_SHIFT			17
573c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO5				(1 << 16)
574c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO5_SHIFT			16
575c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO4				(1 << 15)
576c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO4_SHIFT			15
577c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO3				(1 << 14)
578c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO3_SHIFT			14
579c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO2				(1 << 13)
580c595713dSTony Lindgren #define OMAP3430_AUTO_GPIO2_SHIFT			13
581c595713dSTony Lindgren #define OMAP3430_AUTO_WDT3				(1 << 12)
582c595713dSTony Lindgren #define OMAP3430_AUTO_WDT3_SHIFT			12
583c595713dSTony Lindgren #define OMAP3430_AUTO_UART3				(1 << 11)
584c595713dSTony Lindgren #define OMAP3430_AUTO_UART3_SHIFT			11
585c595713dSTony Lindgren #define OMAP3430_AUTO_GPT9				(1 << 10)
586c595713dSTony Lindgren #define OMAP3430_AUTO_GPT9_SHIFT			10
587c595713dSTony Lindgren #define OMAP3430_AUTO_GPT8				(1 << 9)
588c595713dSTony Lindgren #define OMAP3430_AUTO_GPT8_SHIFT			9
589c595713dSTony Lindgren #define OMAP3430_AUTO_GPT7				(1 << 8)
590c595713dSTony Lindgren #define OMAP3430_AUTO_GPT7_SHIFT			8
591c595713dSTony Lindgren #define OMAP3430_AUTO_GPT6				(1 << 7)
592c595713dSTony Lindgren #define OMAP3430_AUTO_GPT6_SHIFT			7
593c595713dSTony Lindgren #define OMAP3430_AUTO_GPT5				(1 << 6)
594c595713dSTony Lindgren #define OMAP3430_AUTO_GPT5_SHIFT			6
595c595713dSTony Lindgren #define OMAP3430_AUTO_GPT4				(1 << 5)
596c595713dSTony Lindgren #define OMAP3430_AUTO_GPT4_SHIFT			5
597c595713dSTony Lindgren #define OMAP3430_AUTO_GPT3				(1 << 4)
598c595713dSTony Lindgren #define OMAP3430_AUTO_GPT3_SHIFT			4
599c595713dSTony Lindgren #define OMAP3430_AUTO_GPT2				(1 << 3)
600c595713dSTony Lindgren #define OMAP3430_AUTO_GPT2_SHIFT			3
601c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP4				(1 << 2)
602c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP4_SHIFT			2
603c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP3				(1 << 1)
604c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP3_SHIFT			1
605c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP2				(1 << 0)
606c595713dSTony Lindgren #define OMAP3430_AUTO_MCBSP2_SHIFT			0
607c595713dSTony Lindgren 
608c595713dSTony Lindgren /* CM_CLKSEL_PER */
609c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT9_MASK			(1 << 7)
610c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT9_SHIFT			7
611c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT8_MASK			(1 << 6)
612c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT8_SHIFT			6
613c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT7_MASK			(1 << 5)
614c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT7_SHIFT			5
615c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT6_MASK			(1 << 4)
616c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT6_SHIFT			4
617c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT5_MASK			(1 << 3)
618c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT5_SHIFT			3
619c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT4_MASK			(1 << 2)
620c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT4_SHIFT			2
621c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT3_MASK			(1 << 1)
622c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT3_SHIFT			1
623c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT2_MASK			(1 << 0)
624c595713dSTony Lindgren #define OMAP3430_CLKSEL_GPT2_SHIFT			0
625c595713dSTony Lindgren 
626c595713dSTony Lindgren /* CM_SLEEPDEP_PER specific bits */
627c595713dSTony Lindgren #define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2		(1 << 2)
628c595713dSTony Lindgren 
629c595713dSTony Lindgren /* CM_CLKSTCTRL_PER */
630c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_PER_SHIFT			0
631c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_PER_MASK			(0x3 << 0)
632c595713dSTony Lindgren 
633c595713dSTony Lindgren /* CM_CLKSTST_PER */
634801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_PER_SHIFT			0
635801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_PER_MASK			(1 << 0)
636c595713dSTony Lindgren 
637c595713dSTony Lindgren /* CM_CLKSEL1_EMU */
638c595713dSTony Lindgren #define OMAP3430_DIV_DPLL4_SHIFT			24
639c595713dSTony Lindgren #define OMAP3430_DIV_DPLL4_MASK				(0x1f << 24)
640c595713dSTony Lindgren #define OMAP3430_DIV_DPLL3_SHIFT			16
641c595713dSTony Lindgren #define OMAP3430_DIV_DPLL3_MASK				(0x1f << 16)
642c595713dSTony Lindgren #define OMAP3430_CLKSEL_TRACECLK_SHIFT			11
643c595713dSTony Lindgren #define OMAP3430_CLKSEL_TRACECLK_MASK			(0x7 << 11)
644c595713dSTony Lindgren #define OMAP3430_CLKSEL_PCLK_SHIFT			8
645c595713dSTony Lindgren #define OMAP3430_CLKSEL_PCLK_MASK			(0x7 << 8)
646c595713dSTony Lindgren #define OMAP3430_CLKSEL_PCLKX2_SHIFT			6
647c595713dSTony Lindgren #define OMAP3430_CLKSEL_PCLKX2_MASK			(0x3 << 6)
648c595713dSTony Lindgren #define OMAP3430_CLKSEL_ATCLK_SHIFT			4
649c595713dSTony Lindgren #define OMAP3430_CLKSEL_ATCLK_MASK			(0x3 << 4)
650c595713dSTony Lindgren #define OMAP3430_TRACE_MUX_CTRL_SHIFT			2
651c595713dSTony Lindgren #define OMAP3430_TRACE_MUX_CTRL_MASK			(0x3 << 2)
652c595713dSTony Lindgren #define OMAP3430_MUX_CTRL_SHIFT				0
653c595713dSTony Lindgren #define OMAP3430_MUX_CTRL_MASK				(0x3 << 0)
654c595713dSTony Lindgren 
655c595713dSTony Lindgren /* CM_CLKSTCTRL_EMU */
656c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_EMU_SHIFT			0
657c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_EMU_MASK			(0x3 << 0)
658c595713dSTony Lindgren 
659c595713dSTony Lindgren /* CM_CLKSTST_EMU */
660801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_EMU_SHIFT			0
661801954d3SPaul Walmsley #define OMAP3430_CLKACTIVITY_EMU_MASK			(1 << 0)
662c595713dSTony Lindgren 
663c595713dSTony Lindgren /* CM_CLKSEL2_EMU specific bits */
664c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT		8
665c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_EMU_MULT_MASK		(0x7ff << 8)
666c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT		0
667c595713dSTony Lindgren #define OMAP3430_CORE_DPLL_EMU_DIV_MASK			(0x7f << 0)
668c595713dSTony Lindgren 
669c595713dSTony Lindgren /* CM_CLKSEL3_EMU specific bits */
670c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT		8
671c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK		(0x7ff << 8)
672c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT		0
673c595713dSTony Lindgren #define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK		(0x7f << 0)
674c595713dSTony Lindgren 
675c595713dSTony Lindgren /* CM_POLCTRL */
676c595713dSTony Lindgren #define OMAP3430_CLKOUT2_POL				(1 << 0)
677c595713dSTony Lindgren 
678c595713dSTony Lindgren /* CM_IDLEST_NEON */
679c595713dSTony Lindgren #define OMAP3430_ST_NEON				(1 << 0)
680c595713dSTony Lindgren 
681c595713dSTony Lindgren /* CM_CLKSTCTRL_NEON */
682c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_NEON_SHIFT			0
683c595713dSTony Lindgren #define OMAP3430_CLKTRCTRL_NEON_MASK			(0x3 << 0)
684c595713dSTony Lindgren 
685c595713dSTony Lindgren /* CM_FCLKEN_USBHOST */
686c595713dSTony Lindgren #define OMAP3430ES2_EN_USBHOST2_SHIFT			1
687c595713dSTony Lindgren #define OMAP3430ES2_EN_USBHOST2_MASK			(1 << 1)
688c595713dSTony Lindgren #define OMAP3430ES2_EN_USBHOST1_SHIFT			0
689c595713dSTony Lindgren #define OMAP3430ES2_EN_USBHOST1_MASK			(1 << 0)
690c595713dSTony Lindgren 
691c595713dSTony Lindgren /* CM_ICLKEN_USBHOST */
692c595713dSTony Lindgren #define OMAP3430ES2_EN_USBHOST_SHIFT			0
693c595713dSTony Lindgren #define OMAP3430ES2_EN_USBHOST_MASK			(1 << 0)
694c595713dSTony Lindgren 
695c595713dSTony Lindgren /* CM_IDLEST_USBHOST */
696c595713dSTony Lindgren 
697c595713dSTony Lindgren /* CM_AUTOIDLE_USBHOST */
698c595713dSTony Lindgren #define OMAP3430ES2_AUTO_USBHOST_SHIFT			0
699c595713dSTony Lindgren #define OMAP3430ES2_AUTO_USBHOST_MASK			(1 << 0)
700c595713dSTony Lindgren 
701c595713dSTony Lindgren /* CM_SLEEPDEP_USBHOST */
702c595713dSTony Lindgren #define OMAP3430ES2_EN_MPU_SHIFT			1
703c595713dSTony Lindgren #define OMAP3430ES2_EN_MPU_MASK				(1 << 1)
704c595713dSTony Lindgren #define OMAP3430ES2_EN_IVA2_SHIFT			2
705c595713dSTony Lindgren #define OMAP3430ES2_EN_IVA2_MASK			(1 << 2)
706c595713dSTony Lindgren 
707c595713dSTony Lindgren /* CM_CLKSTCTRL_USBHOST */
708c595713dSTony Lindgren #define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT		0
709c595713dSTony Lindgren #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK		(3 << 0)
710c595713dSTony Lindgren 
711801954d3SPaul Walmsley /* CM_CLKSTST_USBHOST */
712801954d3SPaul Walmsley #define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT		0
713801954d3SPaul Walmsley #define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK		(1 << 0)
714c595713dSTony Lindgren 
715c595713dSTony Lindgren #endif
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