1*52e6676eSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2f969a6dcSVaibhav Hiremath /* 3f969a6dcSVaibhav Hiremath * AM33XX Power Management register bits 4f969a6dcSVaibhav Hiremath * 5f969a6dcSVaibhav Hiremath * This file is automatically generated from the AM33XX hardware databases. 6f969a6dcSVaibhav Hiremath * Vaibhav Hiremath <hvaibhav@ti.com> 7f969a6dcSVaibhav Hiremath * 883bf6db0SAlexander A. Klimov * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/ 9f969a6dcSVaibhav Hiremath */ 10f969a6dcSVaibhav Hiremath 11f969a6dcSVaibhav Hiremath 12f969a6dcSVaibhav Hiremath #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H 13f969a6dcSVaibhav Hiremath #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H 14f969a6dcSVaibhav Hiremath 15f969a6dcSVaibhav Hiremath #define AM33XX_CLKOUT2DIV_SHIFT 3 16a86c0b98SVaibhav Hiremath #define AM33XX_CLKOUT2DIV_WIDTH 3 17f969a6dcSVaibhav Hiremath #define AM33XX_CLKOUT2EN_SHIFT 7 18a86c0b98SVaibhav Hiremath #define AM33XX_CLKOUT2SOURCE_MASK (0x7 << 0) 19f969a6dcSVaibhav Hiremath #define AM33XX_CLKSEL_0_0_SHIFT 0 20a86c0b98SVaibhav Hiremath #define AM33XX_CLKSEL_0_0_WIDTH 1 21f969a6dcSVaibhav Hiremath #define AM33XX_CLKSEL_0_0_MASK (1 << 0) 22f969a6dcSVaibhav Hiremath #define AM33XX_CLKSEL_0_1_MASK (3 << 0) 23f969a6dcSVaibhav Hiremath #define AM33XX_CLKSEL_0_2_MASK (7 << 0) 24f969a6dcSVaibhav Hiremath #define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1) 25f969a6dcSVaibhav Hiremath #define AM33XX_CLKTRCTRL_SHIFT 0 26f969a6dcSVaibhav Hiremath #define AM33XX_CLKTRCTRL_MASK (0x3 << 0) 27f969a6dcSVaibhav Hiremath #define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0 28a86c0b98SVaibhav Hiremath #define AM33XX_DPLL_CLKOUT_DIV_WIDTH 5 29f969a6dcSVaibhav Hiremath #define AM33XX_DPLL_DIV_MASK (0x7f << 0) 30f969a6dcSVaibhav Hiremath #define AM33XX_DPLL_PER_DIV_MASK (0xff << 0) 31f969a6dcSVaibhav Hiremath #define AM33XX_DPLL_EN_MASK (0x7 << 0) 32f969a6dcSVaibhav Hiremath #define AM33XX_DPLL_MULT_MASK (0x7ff << 8) 33f969a6dcSVaibhav Hiremath #define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8) 34f969a6dcSVaibhav Hiremath #define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 35a86c0b98SVaibhav Hiremath #define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH 5 36f969a6dcSVaibhav Hiremath #define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 37a86c0b98SVaibhav Hiremath #define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH 5 38f969a6dcSVaibhav Hiremath #define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 39a86c0b98SVaibhav Hiremath #define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH 5 40f969a6dcSVaibhav Hiremath #define AM33XX_IDLEST_SHIFT 16 41f969a6dcSVaibhav Hiremath #define AM33XX_IDLEST_MASK (0x3 << 16) 42f969a6dcSVaibhav Hiremath #define AM33XX_MODULEMODE_SHIFT 0 43f969a6dcSVaibhav Hiremath #define AM33XX_MODULEMODE_MASK (0x3 << 0) 44f969a6dcSVaibhav Hiremath #define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30 45f969a6dcSVaibhav Hiremath #define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19 46f969a6dcSVaibhav Hiremath #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18 47f969a6dcSVaibhav Hiremath #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18 48f969a6dcSVaibhav Hiremath #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18 49f969a6dcSVaibhav Hiremath #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18 50f969a6dcSVaibhav Hiremath #define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27 51a86c0b98SVaibhav Hiremath #define AM33XX_STM_PMD_CLKDIVSEL_WIDTH 3 52f969a6dcSVaibhav Hiremath #define AM33XX_STM_PMD_CLKSEL_SHIFT 22 53a86c0b98SVaibhav Hiremath #define AM33XX_STM_PMD_CLKSEL_WIDTH 2 54f969a6dcSVaibhav Hiremath #define AM33XX_ST_DPLL_CLK_MASK (1 << 0) 55f969a6dcSVaibhav Hiremath #define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8 56f969a6dcSVaibhav Hiremath #define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24 57a86c0b98SVaibhav Hiremath #define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH 3 58f969a6dcSVaibhav Hiremath #define AM33XX_TRC_PMD_CLKSEL_SHIFT 20 59a86c0b98SVaibhav Hiremath #define AM33XX_TRC_PMD_CLKSEL_WIDTH 2 60f969a6dcSVaibhav Hiremath #endif 61