1 /* 2 * OMAP4 Clock domains framework 3 * 4 * Copyright (C) 2009 Texas Instruments, Inc. 5 * Copyright (C) 2009 Nokia Corporation 6 * 7 * Abhijit Pagare (abhijitpagare@ti.com) 8 * Benoit Cousson (b-cousson@ti.com) 9 * 10 * This file is automatically generated from the OMAP hardware databases. 11 * We respectfully ask that any modifications to this file be coordinated 12 * with the public linux-omap@vger.kernel.org mailing list and the 13 * authors above to ensure that the autogeneration scripts are kept 14 * up-to-date with the file contents. 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License version 2 as 18 * published by the Free Software Foundation. 19 */ 20 21 /* 22 * To-Do List 23 * -> Populate the Sleep/Wakeup dependencies for the domains 24 */ 25 26 #include <linux/kernel.h> 27 #include <linux/io.h> 28 29 #include "clockdomain.h" 30 #include "cm1_44xx.h" 31 #include "cm2_44xx.h" 32 33 #include "cm-regbits-44xx.h" 34 #include "prm44xx.h" 35 #include "prcm44xx.h" 36 #include "prcm_mpu44xx.h" 37 38 39 static struct clockdomain l4_cefuse_44xx_clkdm = { 40 .name = "l4_cefuse_clkdm", 41 .pwrdm = { .name = "cefuse_pwrdm" }, 42 .prcm_partition = OMAP4430_CM2_PARTITION, 43 .cm_inst = OMAP4430_CM2_CEFUSE_INST, 44 .clkdm_offs = OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS, 45 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 46 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 47 }; 48 49 static struct clockdomain l4_cfg_44xx_clkdm = { 50 .name = "l4_cfg_clkdm", 51 .pwrdm = { .name = "core_pwrdm" }, 52 .prcm_partition = OMAP4430_CM2_PARTITION, 53 .cm_inst = OMAP4430_CM2_CORE_INST, 54 .clkdm_offs = OMAP4430_CM2_CORE_L4CFG_CDOFFS, 55 .flags = CLKDM_CAN_HWSUP, 56 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 57 }; 58 59 static struct clockdomain tesla_44xx_clkdm = { 60 .name = "tesla_clkdm", 61 .pwrdm = { .name = "tesla_pwrdm" }, 62 .prcm_partition = OMAP4430_CM1_PARTITION, 63 .cm_inst = OMAP4430_CM1_TESLA_INST, 64 .clkdm_offs = OMAP4430_CM1_TESLA_TESLA_CDOFFS, 65 .flags = CLKDM_CAN_HWSUP_SWSUP, 66 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 67 }; 68 69 static struct clockdomain l3_gfx_44xx_clkdm = { 70 .name = "l3_gfx_clkdm", 71 .pwrdm = { .name = "gfx_pwrdm" }, 72 .prcm_partition = OMAP4430_CM2_PARTITION, 73 .cm_inst = OMAP4430_CM2_GFX_INST, 74 .clkdm_offs = OMAP4430_CM2_GFX_GFX_CDOFFS, 75 .flags = CLKDM_CAN_HWSUP_SWSUP, 76 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 77 }; 78 79 static struct clockdomain ivahd_44xx_clkdm = { 80 .name = "ivahd_clkdm", 81 .pwrdm = { .name = "ivahd_pwrdm" }, 82 .prcm_partition = OMAP4430_CM2_PARTITION, 83 .cm_inst = OMAP4430_CM2_IVAHD_INST, 84 .clkdm_offs = OMAP4430_CM2_IVAHD_IVAHD_CDOFFS, 85 .flags = CLKDM_CAN_HWSUP_SWSUP, 86 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 87 }; 88 89 static struct clockdomain l4_secure_44xx_clkdm = { 90 .name = "l4_secure_clkdm", 91 .pwrdm = { .name = "l4per_pwrdm" }, 92 .prcm_partition = OMAP4430_CM2_PARTITION, 93 .cm_inst = OMAP4430_CM2_L4PER_INST, 94 .clkdm_offs = OMAP4430_CM2_L4PER_L4SEC_CDOFFS, 95 .flags = CLKDM_CAN_HWSUP_SWSUP, 96 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 97 }; 98 99 static struct clockdomain l4_per_44xx_clkdm = { 100 .name = "l4_per_clkdm", 101 .pwrdm = { .name = "l4per_pwrdm" }, 102 .prcm_partition = OMAP4430_CM2_PARTITION, 103 .cm_inst = OMAP4430_CM2_L4PER_INST, 104 .clkdm_offs = OMAP4430_CM2_L4PER_L4PER_CDOFFS, 105 .flags = CLKDM_CAN_HWSUP_SWSUP, 106 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 107 }; 108 109 static struct clockdomain abe_44xx_clkdm = { 110 .name = "abe_clkdm", 111 .pwrdm = { .name = "abe_pwrdm" }, 112 .prcm_partition = OMAP4430_CM1_PARTITION, 113 .cm_inst = OMAP4430_CM1_ABE_INST, 114 .clkdm_offs = OMAP4430_CM1_ABE_ABE_CDOFFS, 115 .flags = CLKDM_CAN_HWSUP_SWSUP, 116 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 117 }; 118 119 static struct clockdomain l3_instr_44xx_clkdm = { 120 .name = "l3_instr_clkdm", 121 .pwrdm = { .name = "core_pwrdm" }, 122 .prcm_partition = OMAP4430_CM2_PARTITION, 123 .cm_inst = OMAP4430_CM2_CORE_INST, 124 .clkdm_offs = OMAP4430_CM2_CORE_L3INSTR_CDOFFS, 125 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 126 }; 127 128 static struct clockdomain l3_init_44xx_clkdm = { 129 .name = "l3_init_clkdm", 130 .pwrdm = { .name = "l3init_pwrdm" }, 131 .prcm_partition = OMAP4430_CM2_PARTITION, 132 .cm_inst = OMAP4430_CM2_L3INIT_INST, 133 .clkdm_offs = OMAP4430_CM2_L3INIT_L3INIT_CDOFFS, 134 .flags = CLKDM_CAN_HWSUP_SWSUP, 135 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 136 }; 137 138 static struct clockdomain mpuss_44xx_clkdm = { 139 .name = "mpuss_clkdm", 140 .pwrdm = { .name = "mpu_pwrdm" }, 141 .prcm_partition = OMAP4430_CM1_PARTITION, 142 .cm_inst = OMAP4430_CM1_MPU_INST, 143 .clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS, 144 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 145 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 146 }; 147 148 static struct clockdomain mpu0_44xx_clkdm = { 149 .name = "mpu0_clkdm", 150 .pwrdm = { .name = "cpu0_pwrdm" }, 151 .prcm_partition = OMAP4430_PRCM_MPU_PARTITION, 152 .cm_inst = OMAP4430_PRCM_MPU_CPU0_INST, 153 .clkdm_offs = OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS, 154 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 155 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 156 }; 157 158 static struct clockdomain mpu1_44xx_clkdm = { 159 .name = "mpu1_clkdm", 160 .pwrdm = { .name = "cpu1_pwrdm" }, 161 .prcm_partition = OMAP4430_PRCM_MPU_PARTITION, 162 .cm_inst = OMAP4430_PRCM_MPU_CPU1_INST, 163 .clkdm_offs = OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS, 164 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 165 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 166 }; 167 168 static struct clockdomain l3_emif_44xx_clkdm = { 169 .name = "l3_emif_clkdm", 170 .pwrdm = { .name = "core_pwrdm" }, 171 .prcm_partition = OMAP4430_CM2_PARTITION, 172 .cm_inst = OMAP4430_CM2_CORE_INST, 173 .clkdm_offs = OMAP4430_CM2_CORE_MEMIF_CDOFFS, 174 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 175 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 176 }; 177 178 static struct clockdomain l4_ao_44xx_clkdm = { 179 .name = "l4_ao_clkdm", 180 .pwrdm = { .name = "always_on_core_pwrdm" }, 181 .prcm_partition = OMAP4430_CM2_PARTITION, 182 .cm_inst = OMAP4430_CM2_ALWAYS_ON_INST, 183 .clkdm_offs = OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS, 184 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 185 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 186 }; 187 188 static struct clockdomain ducati_44xx_clkdm = { 189 .name = "ducati_clkdm", 190 .pwrdm = { .name = "core_pwrdm" }, 191 .prcm_partition = OMAP4430_CM2_PARTITION, 192 .cm_inst = OMAP4430_CM2_CORE_INST, 193 .clkdm_offs = OMAP4430_CM2_CORE_DUCATI_CDOFFS, 194 .flags = CLKDM_CAN_HWSUP_SWSUP, 195 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 196 }; 197 198 static struct clockdomain l3_2_44xx_clkdm = { 199 .name = "l3_2_clkdm", 200 .pwrdm = { .name = "core_pwrdm" }, 201 .prcm_partition = OMAP4430_CM2_PARTITION, 202 .cm_inst = OMAP4430_CM2_CORE_INST, 203 .clkdm_offs = OMAP4430_CM2_CORE_L3_2_CDOFFS, 204 .flags = CLKDM_CAN_HWSUP, 205 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 206 }; 207 208 static struct clockdomain l3_1_44xx_clkdm = { 209 .name = "l3_1_clkdm", 210 .pwrdm = { .name = "core_pwrdm" }, 211 .prcm_partition = OMAP4430_CM2_PARTITION, 212 .cm_inst = OMAP4430_CM2_CORE_INST, 213 .clkdm_offs = OMAP4430_CM2_CORE_L3_1_CDOFFS, 214 .flags = CLKDM_CAN_HWSUP, 215 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 216 }; 217 218 static struct clockdomain l3_d2d_44xx_clkdm = { 219 .name = "l3_d2d_clkdm", 220 .pwrdm = { .name = "core_pwrdm" }, 221 .prcm_partition = OMAP4430_CM2_PARTITION, 222 .cm_inst = OMAP4430_CM2_CORE_INST, 223 .clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS, 224 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 225 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 226 }; 227 228 static struct clockdomain iss_44xx_clkdm = { 229 .name = "iss_clkdm", 230 .pwrdm = { .name = "cam_pwrdm" }, 231 .prcm_partition = OMAP4430_CM2_PARTITION, 232 .cm_inst = OMAP4430_CM2_CAM_INST, 233 .clkdm_offs = OMAP4430_CM2_CAM_CAM_CDOFFS, 234 .flags = CLKDM_CAN_HWSUP_SWSUP, 235 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 236 }; 237 238 static struct clockdomain l3_dss_44xx_clkdm = { 239 .name = "l3_dss_clkdm", 240 .pwrdm = { .name = "dss_pwrdm" }, 241 .prcm_partition = OMAP4430_CM2_PARTITION, 242 .cm_inst = OMAP4430_CM2_DSS_INST, 243 .clkdm_offs = OMAP4430_CM2_DSS_DSS_CDOFFS, 244 .flags = CLKDM_CAN_HWSUP_SWSUP, 245 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 246 }; 247 248 static struct clockdomain l4_wkup_44xx_clkdm = { 249 .name = "l4_wkup_clkdm", 250 .pwrdm = { .name = "wkup_pwrdm" }, 251 .prcm_partition = OMAP4430_PRM_PARTITION, 252 .cm_inst = OMAP4430_PRM_WKUP_CM_INST, 253 .clkdm_offs = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS, 254 .flags = CLKDM_CAN_HWSUP, 255 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 256 }; 257 258 static struct clockdomain emu_sys_44xx_clkdm = { 259 .name = "emu_sys_clkdm", 260 .pwrdm = { .name = "emu_pwrdm" }, 261 .prcm_partition = OMAP4430_PRM_PARTITION, 262 .cm_inst = OMAP4430_PRM_EMU_CM_INST, 263 .clkdm_offs = OMAP4430_PRM_EMU_CM_EMU_CDOFFS, 264 .flags = CLKDM_CAN_HWSUP, 265 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 266 }; 267 268 static struct clockdomain l3_dma_44xx_clkdm = { 269 .name = "l3_dma_clkdm", 270 .pwrdm = { .name = "core_pwrdm" }, 271 .prcm_partition = OMAP4430_CM2_PARTITION, 272 .cm_inst = OMAP4430_CM2_CORE_INST, 273 .clkdm_offs = OMAP4430_CM2_CORE_SDMA_CDOFFS, 274 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 275 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 276 }; 277 278 static struct clockdomain *clockdomains_omap44xx[] __initdata = { 279 &l4_cefuse_44xx_clkdm, 280 &l4_cfg_44xx_clkdm, 281 &tesla_44xx_clkdm, 282 &l3_gfx_44xx_clkdm, 283 &ivahd_44xx_clkdm, 284 &l4_secure_44xx_clkdm, 285 &l4_per_44xx_clkdm, 286 &abe_44xx_clkdm, 287 &l3_instr_44xx_clkdm, 288 &l3_init_44xx_clkdm, 289 &mpuss_44xx_clkdm, 290 &mpu0_44xx_clkdm, 291 &mpu1_44xx_clkdm, 292 &l3_emif_44xx_clkdm, 293 &l4_ao_44xx_clkdm, 294 &ducati_44xx_clkdm, 295 &l3_2_44xx_clkdm, 296 &l3_1_44xx_clkdm, 297 &l3_d2d_44xx_clkdm, 298 &iss_44xx_clkdm, 299 &l3_dss_44xx_clkdm, 300 &l4_wkup_44xx_clkdm, 301 &emu_sys_44xx_clkdm, 302 &l3_dma_44xx_clkdm, 303 NULL, 304 }; 305 306 void __init omap44xx_clockdomains_init(void) 307 { 308 clkdm_init(clockdomains_omap44xx, NULL); 309 } 310