1 /* 2 * linux/arch/arm/mach-omap2/clock.h 3 * 4 * Copyright (C) 2005-2009 Texas Instruments, Inc. 5 * Copyright (C) 2004-2009 Nokia Corporation 6 * 7 * Contacts: 8 * Richard Woodruff <r-woodruff2@ti.com> 9 * Paul Walmsley 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 16 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H 17 #define __ARCH_ARM_MACH_OMAP2_CLOCK_H 18 19 #include <plat/clock.h> 20 21 /* The maximum error between a target DPLL rate and the rounded rate in Hz */ 22 #define DEFAULT_DPLL_RATE_TOLERANCE 50000 23 24 /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ 25 #define CORE_CLK_SRC_32K 0x0 26 #define CORE_CLK_SRC_DPLL 0x1 27 #define CORE_CLK_SRC_DPLL_X2 0x2 28 29 /* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */ 30 #define OMAP2XXX_EN_DPLL_LPBYPASS 0x1 31 #define OMAP2XXX_EN_DPLL_FRBYPASS 0x2 32 #define OMAP2XXX_EN_DPLL_LOCKED 0x3 33 34 /* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */ 35 #define OMAP3XXX_EN_DPLL_LPBYPASS 0x5 36 #define OMAP3XXX_EN_DPLL_FRBYPASS 0x6 37 #define OMAP3XXX_EN_DPLL_LOCKED 0x7 38 39 /* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */ 40 #define OMAP4XXX_EN_DPLL_MNBYPASS 0x4 41 #define OMAP4XXX_EN_DPLL_LPBYPASS 0x5 42 #define OMAP4XXX_EN_DPLL_FRBYPASS 0x6 43 #define OMAP4XXX_EN_DPLL_LOCKED 0x7 44 45 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ 46 #define DPLL_LOW_POWER_STOP 0x1 47 #define DPLL_LOW_POWER_BYPASS 0x5 48 #define DPLL_LOCKED 0x7 49 50 int omap2_clk_init(void); 51 int omap2_clk_enable(struct clk *clk); 52 void omap2_clk_disable(struct clk *clk); 53 long omap2_clk_round_rate(struct clk *clk, unsigned long rate); 54 int omap2_clk_set_rate(struct clk *clk, unsigned long rate); 55 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); 56 int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance); 57 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); 58 unsigned long omap3_dpll_recalc(struct clk *clk); 59 unsigned long omap3_clkoutx2_recalc(struct clk *clk); 60 void omap3_dpll_allow_idle(struct clk *clk); 61 void omap3_dpll_deny_idle(struct clk *clk); 62 u32 omap3_dpll_autoidle_read(struct clk *clk); 63 int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate); 64 int omap3_noncore_dpll_enable(struct clk *clk); 65 void omap3_noncore_dpll_disable(struct clk *clk); 66 67 #ifdef CONFIG_OMAP_RESET_CLOCKS 68 void omap2_clk_disable_unused(struct clk *clk); 69 #else 70 #define omap2_clk_disable_unused NULL 71 #endif 72 73 unsigned long omap2_clksel_recalc(struct clk *clk); 74 void omap2_init_clk_clkdm(struct clk *clk); 75 void omap2_init_clksel_parent(struct clk *clk); 76 u32 omap2_clksel_get_divisor(struct clk *clk); 77 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, 78 u32 *new_div); 79 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val); 80 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div); 81 unsigned long omap2_fixed_divisor_recalc(struct clk *clk); 82 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); 83 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); 84 u32 omap2_get_dpll_rate(struct clk *clk); 85 void omap2_init_dpll_parent(struct clk *clk); 86 int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name); 87 void omap2_clk_prepare_for_reboot(void); 88 int omap2_dflt_clk_enable(struct clk *clk); 89 void omap2_dflt_clk_disable(struct clk *clk); 90 void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, 91 u8 *other_bit); 92 void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, 93 u8 *idlest_bit); 94 95 extern u8 cpu_mask; 96 97 extern const struct clkops clkops_omap2_dflt_wait; 98 extern const struct clkops clkops_omap2_dflt; 99 100 extern struct clk_functions omap2_clk_functions; 101 extern struct clk *vclk, *sclk; 102 103 extern const struct clksel_rate gpt_32k_rates[]; 104 extern const struct clksel_rate gpt_sys_rates[]; 105 extern const struct clksel_rate gfx_l3_rates[]; 106 107 108 #endif 109