1 /* 2 * linux/arch/arm/mach-omap2/clock.c 3 * 4 * Copyright (C) 2005-2008 Texas Instruments, Inc. 5 * Copyright (C) 2004-2008 Nokia Corporation 6 * 7 * Contacts: 8 * Richard Woodruff <r-woodruff2@ti.com> 9 * Paul Walmsley 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 #undef DEBUG 16 17 #include <linux/module.h> 18 #include <linux/kernel.h> 19 #include <linux/device.h> 20 #include <linux/list.h> 21 #include <linux/errno.h> 22 #include <linux/delay.h> 23 #include <linux/clk.h> 24 #include <linux/io.h> 25 #include <linux/bitops.h> 26 27 #include <plat/clock.h> 28 #include <plat/clockdomain.h> 29 #include <plat/cpu.h> 30 #include <plat/prcm.h> 31 #include <asm/div64.h> 32 33 #include <plat/sdrc.h> 34 #include "sdrc.h" 35 #include "clock.h" 36 #include "prm.h" 37 #include "prm-regbits-24xx.h" 38 #include "cm.h" 39 #include "cm-regbits-24xx.h" 40 #include "cm-regbits-34xx.h" 41 42 /* DPLL rate rounding: minimum DPLL multiplier, divider values */ 43 #define DPLL_MIN_MULTIPLIER 1 44 #define DPLL_MIN_DIVIDER 1 45 46 /* Possible error results from _dpll_test_mult */ 47 #define DPLL_MULT_UNDERFLOW -1 48 49 /* 50 * Scale factor to mitigate roundoff errors in DPLL rate rounding. 51 * The higher the scale factor, the greater the risk of arithmetic overflow, 52 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR 53 * must be a power of DPLL_SCALE_BASE. 54 */ 55 #define DPLL_SCALE_FACTOR 64 56 #define DPLL_SCALE_BASE 2 57 #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \ 58 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE)) 59 60 /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ 61 #define DPLL_FINT_BAND1_MIN 750000 62 #define DPLL_FINT_BAND1_MAX 2100000 63 #define DPLL_FINT_BAND2_MIN 7500000 64 #define DPLL_FINT_BAND2_MAX 21000000 65 66 /* _dpll_test_fint() return codes */ 67 #define DPLL_FINT_UNDERFLOW -1 68 #define DPLL_FINT_INVALID -2 69 70 u8 cpu_mask; 71 72 /*------------------------------------------------------------------------- 73 * OMAP2/3/4 specific clock functions 74 *-------------------------------------------------------------------------*/ 75 76 void omap2_init_dpll_parent(struct clk *clk) 77 { 78 u32 v; 79 struct dpll_data *dd; 80 81 dd = clk->dpll_data; 82 if (!dd) 83 return; 84 85 /* Return bypass rate if DPLL is bypassed */ 86 v = __raw_readl(dd->control_reg); 87 v &= dd->enable_mask; 88 v >>= __ffs(dd->enable_mask); 89 90 /* Reparent in case the dpll is in bypass */ 91 if (cpu_is_omap24xx()) { 92 if (v == OMAP2XXX_EN_DPLL_LPBYPASS || 93 v == OMAP2XXX_EN_DPLL_FRBYPASS) 94 clk_reparent(clk, dd->clk_bypass); 95 } else if (cpu_is_omap34xx()) { 96 if (v == OMAP3XXX_EN_DPLL_LPBYPASS || 97 v == OMAP3XXX_EN_DPLL_FRBYPASS) 98 clk_reparent(clk, dd->clk_bypass); 99 } else if (cpu_is_omap44xx()) { 100 if (v == OMAP4XXX_EN_DPLL_LPBYPASS || 101 v == OMAP4XXX_EN_DPLL_FRBYPASS || 102 v == OMAP4XXX_EN_DPLL_MNBYPASS) 103 clk_reparent(clk, dd->clk_bypass); 104 } 105 return; 106 } 107 108 /** 109 * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware 110 * @clk: struct clk * 111 * 112 * If @clk has the DELAYED_APP flag set, meaning that parent/rate changes 113 * don't take effect until the VALID_CONFIG bit is written, write the 114 * VALID_CONFIG bit and wait for the write to complete. No return value. 115 */ 116 static void _omap2xxx_clk_commit(struct clk *clk) 117 { 118 if (!cpu_is_omap24xx()) 119 return; 120 121 if (!(clk->flags & DELAYED_APP)) 122 return; 123 124 prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD, 125 OMAP2_PRCM_CLKCFG_CTRL_OFFSET); 126 /* OCP barrier */ 127 prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP2_PRCM_CLKCFG_CTRL_OFFSET); 128 } 129 130 /* 131 * _dpll_test_fint - test whether an Fint value is valid for the DPLL 132 * @clk: DPLL struct clk to test 133 * @n: divider value (N) to test 134 * 135 * Tests whether a particular divider @n will result in a valid DPLL 136 * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter 137 * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate 138 * (assuming that it is counting N upwards), or -2 if the enclosing loop 139 * should skip to the next iteration (again assuming N is increasing). 140 */ 141 static int _dpll_test_fint(struct clk *clk, u8 n) 142 { 143 struct dpll_data *dd; 144 long fint; 145 int ret = 0; 146 147 dd = clk->dpll_data; 148 149 /* DPLL divider must result in a valid jitter correction val */ 150 fint = clk->parent->rate / (n + 1); 151 if (fint < DPLL_FINT_BAND1_MIN) { 152 153 pr_debug("rejecting n=%d due to Fint failure, " 154 "lowering max_divider\n", n); 155 dd->max_divider = n; 156 ret = DPLL_FINT_UNDERFLOW; 157 158 } else if (fint > DPLL_FINT_BAND1_MAX && 159 fint < DPLL_FINT_BAND2_MIN) { 160 161 pr_debug("rejecting n=%d due to Fint failure\n", n); 162 ret = DPLL_FINT_INVALID; 163 164 } else if (fint > DPLL_FINT_BAND2_MAX) { 165 166 pr_debug("rejecting n=%d due to Fint failure, " 167 "boosting min_divider\n", n); 168 dd->min_divider = n; 169 ret = DPLL_FINT_INVALID; 170 171 } 172 173 return ret; 174 } 175 176 /** 177 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk 178 * @clk: OMAP clock struct ptr to use 179 * 180 * Convert a clockdomain name stored in a struct clk 'clk' into a 181 * clockdomain pointer, and save it into the struct clk. Intended to be 182 * called during clk_register(). No return value. 183 */ 184 #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */ 185 void omap2_init_clk_clkdm(struct clk *clk) 186 { 187 struct clockdomain *clkdm; 188 189 if (!clk->clkdm_name) 190 return; 191 192 clkdm = clkdm_lookup(clk->clkdm_name); 193 if (clkdm) { 194 pr_debug("clock: associated clk %s to clkdm %s\n", 195 clk->name, clk->clkdm_name); 196 clk->clkdm = clkdm; 197 } else { 198 pr_debug("clock: could not associate clk %s to " 199 "clkdm %s\n", clk->name, clk->clkdm_name); 200 } 201 } 202 #endif 203 204 /** 205 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware 206 * @clk: OMAP clock struct ptr to use 207 * 208 * Given a pointer to a source-selectable struct clk, read the hardware 209 * register and determine what its parent is currently set to. Update the 210 * clk->parent field with the appropriate clk ptr. 211 */ 212 void omap2_init_clksel_parent(struct clk *clk) 213 { 214 const struct clksel *clks; 215 const struct clksel_rate *clkr; 216 u32 r, found = 0; 217 218 if (!clk->clksel) 219 return; 220 221 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; 222 r >>= __ffs(clk->clksel_mask); 223 224 for (clks = clk->clksel; clks->parent && !found; clks++) { 225 for (clkr = clks->rates; clkr->div && !found; clkr++) { 226 if ((clkr->flags & cpu_mask) && (clkr->val == r)) { 227 if (clk->parent != clks->parent) { 228 pr_debug("clock: inited %s parent " 229 "to %s (was %s)\n", 230 clk->name, clks->parent->name, 231 ((clk->parent) ? 232 clk->parent->name : "NULL")); 233 clk_reparent(clk, clks->parent); 234 }; 235 found = 1; 236 } 237 } 238 } 239 240 if (!found) 241 printk(KERN_ERR "clock: init parent: could not find " 242 "regval %0x for clock %s\n", r, clk->name); 243 244 return; 245 } 246 247 /** 248 * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate 249 * @clk: struct clk * of a DPLL 250 * 251 * DPLLs can be locked or bypassed - basically, enabled or disabled. 252 * When locked, the DPLL output depends on the M and N values. When 253 * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock 254 * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and 255 * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively 256 * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk. 257 * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is 258 * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0 259 * if the clock @clk is not a DPLL. 260 */ 261 u32 omap2_get_dpll_rate(struct clk *clk) 262 { 263 long long dpll_clk; 264 u32 dpll_mult, dpll_div, v; 265 struct dpll_data *dd; 266 267 dd = clk->dpll_data; 268 if (!dd) 269 return 0; 270 271 /* Return bypass rate if DPLL is bypassed */ 272 v = __raw_readl(dd->control_reg); 273 v &= dd->enable_mask; 274 v >>= __ffs(dd->enable_mask); 275 276 if (cpu_is_omap24xx()) { 277 if (v == OMAP2XXX_EN_DPLL_LPBYPASS || 278 v == OMAP2XXX_EN_DPLL_FRBYPASS) 279 return dd->clk_bypass->rate; 280 } else if (cpu_is_omap34xx()) { 281 if (v == OMAP3XXX_EN_DPLL_LPBYPASS || 282 v == OMAP3XXX_EN_DPLL_FRBYPASS) 283 return dd->clk_bypass->rate; 284 } else if (cpu_is_omap44xx()) { 285 if (v == OMAP4XXX_EN_DPLL_LPBYPASS || 286 v == OMAP4XXX_EN_DPLL_FRBYPASS || 287 v == OMAP4XXX_EN_DPLL_MNBYPASS) 288 return dd->clk_bypass->rate; 289 } 290 291 v = __raw_readl(dd->mult_div1_reg); 292 dpll_mult = v & dd->mult_mask; 293 dpll_mult >>= __ffs(dd->mult_mask); 294 dpll_div = v & dd->div1_mask; 295 dpll_div >>= __ffs(dd->div1_mask); 296 297 dpll_clk = (long long)dd->clk_ref->rate * dpll_mult; 298 do_div(dpll_clk, dpll_div + 1); 299 300 return dpll_clk; 301 } 302 303 /** 304 * omap2_clk_dflt_find_companion - find companion clock to @clk 305 * @clk: struct clk * to find the companion clock of 306 * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in 307 * @other_bit: u8 ** to return the companion clock bit shift in 308 * 309 * Note: We don't need special code here for INVERT_ENABLE for the 310 * time being since INVERT_ENABLE only applies to clocks enabled by 311 * CM_CLKEN_PLL 312 * 313 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's 314 * just a matter of XORing the bits. 315 * 316 * Some clocks don't have companion clocks. For example, modules with 317 * only an interface clock (such as MAILBOXES) don't have a companion 318 * clock. Right now, this code relies on the hardware exporting a bit 319 * in the correct companion register that indicates that the 320 * nonexistent 'companion clock' is active. Future patches will 321 * associate this type of code with per-module data structures to 322 * avoid this issue, and remove the casts. No return value. 323 */ 324 void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, 325 u8 *other_bit) 326 { 327 u32 r; 328 329 /* 330 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes 331 * it's just a matter of XORing the bits. 332 */ 333 r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN)); 334 335 *other_reg = (__force void __iomem *)r; 336 *other_bit = clk->enable_bit; 337 } 338 339 /** 340 * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk 341 * @clk: struct clk * to find IDLEST info for 342 * @idlest_reg: void __iomem ** to return the CM_IDLEST va in 343 * @idlest_bit: u8 ** to return the CM_IDLEST bit shift in 344 * 345 * Return the CM_IDLEST register address and bit shift corresponding 346 * to the module that "owns" this clock. This default code assumes 347 * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that 348 * the IDLEST register address ID corresponds to the CM_*CLKEN 349 * register address ID (e.g., that CM_FCLKEN2 corresponds to 350 * CM_IDLEST2). This is not true for all modules. No return value. 351 */ 352 void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, 353 u8 *idlest_bit) 354 { 355 u32 r; 356 357 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); 358 *idlest_reg = (__force void __iomem *)r; 359 *idlest_bit = clk->enable_bit; 360 } 361 362 /** 363 * omap2_module_wait_ready - wait for an OMAP module to leave IDLE 364 * @clk: struct clk * belonging to the module 365 * 366 * If the necessary clocks for the OMAP hardware IP block that 367 * corresponds to clock @clk are enabled, then wait for the module to 368 * indicate readiness (i.e., to leave IDLE). This code does not 369 * belong in the clock code and will be moved in the medium term to 370 * module-dependent code. No return value. 371 */ 372 static void omap2_module_wait_ready(struct clk *clk) 373 { 374 void __iomem *companion_reg, *idlest_reg; 375 u8 other_bit, idlest_bit; 376 377 /* Not all modules have multiple clocks that their IDLEST depends on */ 378 if (clk->ops->find_companion) { 379 clk->ops->find_companion(clk, &companion_reg, &other_bit); 380 if (!(__raw_readl(companion_reg) & (1 << other_bit))) 381 return; 382 } 383 384 clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit); 385 386 omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), clk->name); 387 } 388 389 int omap2_dflt_clk_enable(struct clk *clk) 390 { 391 u32 v; 392 393 if (unlikely(clk->enable_reg == NULL)) { 394 pr_err("clock.c: Enable for %s without enable code\n", 395 clk->name); 396 return 0; /* REVISIT: -EINVAL */ 397 } 398 399 v = __raw_readl(clk->enable_reg); 400 if (clk->flags & INVERT_ENABLE) 401 v &= ~(1 << clk->enable_bit); 402 else 403 v |= (1 << clk->enable_bit); 404 __raw_writel(v, clk->enable_reg); 405 v = __raw_readl(clk->enable_reg); /* OCP barrier */ 406 407 if (clk->ops->find_idlest) 408 omap2_module_wait_ready(clk); 409 410 return 0; 411 } 412 413 void omap2_dflt_clk_disable(struct clk *clk) 414 { 415 u32 v; 416 417 if (!clk->enable_reg) { 418 /* 419 * 'Independent' here refers to a clock which is not 420 * controlled by its parent. 421 */ 422 printk(KERN_ERR "clock: clk_disable called on independent " 423 "clock %s which has no enable_reg\n", clk->name); 424 return; 425 } 426 427 v = __raw_readl(clk->enable_reg); 428 if (clk->flags & INVERT_ENABLE) 429 v |= (1 << clk->enable_bit); 430 else 431 v &= ~(1 << clk->enable_bit); 432 __raw_writel(v, clk->enable_reg); 433 /* No OCP barrier needed here since it is a disable operation */ 434 } 435 436 const struct clkops clkops_omap2_dflt_wait = { 437 .enable = omap2_dflt_clk_enable, 438 .disable = omap2_dflt_clk_disable, 439 .find_companion = omap2_clk_dflt_find_companion, 440 .find_idlest = omap2_clk_dflt_find_idlest, 441 }; 442 443 const struct clkops clkops_omap2_dflt = { 444 .enable = omap2_dflt_clk_enable, 445 .disable = omap2_dflt_clk_disable, 446 }; 447 448 /* Enables clock without considering parent dependencies or use count 449 * REVISIT: Maybe change this to use clk->enable like on omap1? 450 */ 451 static int _omap2_clk_enable(struct clk *clk) 452 { 453 return clk->ops->enable(clk); 454 } 455 456 /* Disables clock without considering parent dependencies or use count */ 457 static void _omap2_clk_disable(struct clk *clk) 458 { 459 clk->ops->disable(clk); 460 } 461 462 void omap2_clk_disable(struct clk *clk) 463 { 464 if (clk->usecount > 0 && !(--clk->usecount)) { 465 _omap2_clk_disable(clk); 466 if (clk->parent) 467 omap2_clk_disable(clk->parent); 468 #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */ 469 if (clk->clkdm) 470 omap2_clkdm_clk_disable(clk->clkdm, clk); 471 #endif 472 473 } 474 } 475 476 int omap2_clk_enable(struct clk *clk) 477 { 478 int ret = 0; 479 480 if (clk->usecount++ == 0) { 481 #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */ 482 if (clk->clkdm) 483 omap2_clkdm_clk_enable(clk->clkdm, clk); 484 #endif 485 486 if (clk->parent) { 487 ret = omap2_clk_enable(clk->parent); 488 if (ret) 489 goto err; 490 } 491 492 ret = _omap2_clk_enable(clk); 493 if (ret) { 494 if (clk->parent) 495 omap2_clk_disable(clk->parent); 496 497 goto err; 498 } 499 } 500 return ret; 501 502 err: 503 #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */ 504 if (clk->clkdm) 505 omap2_clkdm_clk_disable(clk->clkdm, clk); 506 #endif 507 clk->usecount--; 508 return ret; 509 } 510 511 /* 512 * Used for clocks that are part of CLKSEL_xyz governed clocks. 513 * REVISIT: Maybe change to use clk->enable() functions like on omap1? 514 */ 515 unsigned long omap2_clksel_recalc(struct clk *clk) 516 { 517 unsigned long rate; 518 u32 div = 0; 519 520 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name); 521 522 div = omap2_clksel_get_divisor(clk); 523 if (div == 0) 524 return clk->rate; 525 526 rate = clk->parent->rate / div; 527 528 pr_debug("clock: new clock rate is %ld (div %d)\n", rate, div); 529 530 return rate; 531 } 532 533 /** 534 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent 535 * @clk: OMAP struct clk ptr to inspect 536 * @src_clk: OMAP struct clk ptr of the parent clk to search for 537 * 538 * Scan the struct clksel array associated with the clock to find 539 * the element associated with the supplied parent clock address. 540 * Returns a pointer to the struct clksel on success or NULL on error. 541 */ 542 static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk, 543 struct clk *src_clk) 544 { 545 const struct clksel *clks; 546 547 if (!clk->clksel) 548 return NULL; 549 550 for (clks = clk->clksel; clks->parent; clks++) { 551 if (clks->parent == src_clk) 552 break; /* Found the requested parent */ 553 } 554 555 if (!clks->parent) { 556 printk(KERN_ERR "clock: Could not find parent clock %s in " 557 "clksel array of clock %s\n", src_clk->name, 558 clk->name); 559 return NULL; 560 } 561 562 return clks; 563 } 564 565 /** 566 * omap2_clksel_round_rate_div - find divisor for the given clock and rate 567 * @clk: OMAP struct clk to use 568 * @target_rate: desired clock rate 569 * @new_div: ptr to where we should store the divisor 570 * 571 * Finds 'best' divider value in an array based on the source and target 572 * rates. The divider array must be sorted with smallest divider first. 573 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, 574 * they are only settable as part of virtual_prcm set. 575 * 576 * Returns the rounded clock rate or returns 0xffffffff on error. 577 */ 578 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, 579 u32 *new_div) 580 { 581 unsigned long test_rate; 582 const struct clksel *clks; 583 const struct clksel_rate *clkr; 584 u32 last_div = 0; 585 586 pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n", 587 clk->name, target_rate); 588 589 *new_div = 1; 590 591 clks = omap2_get_clksel_by_parent(clk, clk->parent); 592 if (!clks) 593 return ~0; 594 595 for (clkr = clks->rates; clkr->div; clkr++) { 596 if (!(clkr->flags & cpu_mask)) 597 continue; 598 599 /* Sanity check */ 600 if (clkr->div <= last_div) 601 pr_err("clock: clksel_rate table not sorted " 602 "for clock %s", clk->name); 603 604 last_div = clkr->div; 605 606 test_rate = clk->parent->rate / clkr->div; 607 608 if (test_rate <= target_rate) 609 break; /* found it */ 610 } 611 612 if (!clkr->div) { 613 pr_err("clock: Could not find divisor for target " 614 "rate %ld for clock %s parent %s\n", target_rate, 615 clk->name, clk->parent->name); 616 return ~0; 617 } 618 619 *new_div = clkr->div; 620 621 pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div, 622 (clk->parent->rate / clkr->div)); 623 624 return (clk->parent->rate / clkr->div); 625 } 626 627 /** 628 * omap2_clksel_round_rate - find rounded rate for the given clock and rate 629 * @clk: OMAP struct clk to use 630 * @target_rate: desired clock rate 631 * 632 * Compatibility wrapper for OMAP clock framework 633 * Finds best target rate based on the source clock and possible dividers. 634 * rates. The divider array must be sorted with smallest divider first. 635 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, 636 * they are only settable as part of virtual_prcm set. 637 * 638 * Returns the rounded clock rate or returns 0xffffffff on error. 639 */ 640 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) 641 { 642 u32 new_div; 643 644 return omap2_clksel_round_rate_div(clk, target_rate, &new_div); 645 } 646 647 648 /* Given a clock and a rate apply a clock specific rounding function */ 649 long omap2_clk_round_rate(struct clk *clk, unsigned long rate) 650 { 651 if (clk->round_rate) 652 return clk->round_rate(clk, rate); 653 654 if (clk->flags & RATE_FIXED) 655 printk(KERN_ERR "clock: generic omap2_clk_round_rate called " 656 "on fixed-rate clock %s\n", clk->name); 657 658 return clk->rate; 659 } 660 661 /** 662 * omap2_clksel_to_divisor() - turn clksel field value into integer divider 663 * @clk: OMAP struct clk to use 664 * @field_val: register field value to find 665 * 666 * Given a struct clk of a rate-selectable clksel clock, and a register field 667 * value to search for, find the corresponding clock divisor. The register 668 * field value should be pre-masked and shifted down so the LSB is at bit 0 669 * before calling. Returns 0 on error 670 */ 671 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val) 672 { 673 const struct clksel *clks; 674 const struct clksel_rate *clkr; 675 676 clks = omap2_get_clksel_by_parent(clk, clk->parent); 677 if (!clks) 678 return 0; 679 680 for (clkr = clks->rates; clkr->div; clkr++) { 681 if ((clkr->flags & cpu_mask) && (clkr->val == field_val)) 682 break; 683 } 684 685 if (!clkr->div) { 686 printk(KERN_ERR "clock: Could not find fieldval %d for " 687 "clock %s parent %s\n", field_val, clk->name, 688 clk->parent->name); 689 return 0; 690 } 691 692 return clkr->div; 693 } 694 695 /** 696 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value 697 * @clk: OMAP struct clk to use 698 * @div: integer divisor to search for 699 * 700 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor, 701 * find the corresponding register field value. The return register value is 702 * the value before left-shifting. Returns ~0 on error 703 */ 704 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div) 705 { 706 const struct clksel *clks; 707 const struct clksel_rate *clkr; 708 709 /* should never happen */ 710 WARN_ON(div == 0); 711 712 clks = omap2_get_clksel_by_parent(clk, clk->parent); 713 if (!clks) 714 return ~0; 715 716 for (clkr = clks->rates; clkr->div; clkr++) { 717 if ((clkr->flags & cpu_mask) && (clkr->div == div)) 718 break; 719 } 720 721 if (!clkr->div) { 722 printk(KERN_ERR "clock: Could not find divisor %d for " 723 "clock %s parent %s\n", div, clk->name, 724 clk->parent->name); 725 return ~0; 726 } 727 728 return clkr->val; 729 } 730 731 /** 732 * omap2_clksel_get_divisor - get current divider applied to parent clock. 733 * @clk: OMAP struct clk to use. 734 * 735 * Returns the integer divisor upon success or 0 on error. 736 */ 737 u32 omap2_clksel_get_divisor(struct clk *clk) 738 { 739 u32 v; 740 741 if (!clk->clksel_mask) 742 return 0; 743 744 v = __raw_readl(clk->clksel_reg) & clk->clksel_mask; 745 v >>= __ffs(clk->clksel_mask); 746 747 return omap2_clksel_to_divisor(clk, v); 748 } 749 750 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) 751 { 752 u32 v, field_val, validrate, new_div = 0; 753 754 if (!clk->clksel_mask) 755 return -EINVAL; 756 757 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); 758 if (validrate != rate) 759 return -EINVAL; 760 761 field_val = omap2_divisor_to_clksel(clk, new_div); 762 if (field_val == ~0) 763 return -EINVAL; 764 765 v = __raw_readl(clk->clksel_reg); 766 v &= ~clk->clksel_mask; 767 v |= field_val << __ffs(clk->clksel_mask); 768 __raw_writel(v, clk->clksel_reg); 769 v = __raw_readl(clk->clksel_reg); /* OCP barrier */ 770 771 clk->rate = clk->parent->rate / new_div; 772 773 _omap2xxx_clk_commit(clk); 774 775 return 0; 776 } 777 778 779 /* Set the clock rate for a clock source */ 780 int omap2_clk_set_rate(struct clk *clk, unsigned long rate) 781 { 782 int ret = -EINVAL; 783 784 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate); 785 786 /* CONFIG_PARTICIPANT clocks are changed only in sets via the 787 rate table mechanism, driven by mpu_speed */ 788 if (clk->flags & CONFIG_PARTICIPANT) 789 return -EINVAL; 790 791 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ 792 if (clk->set_rate) 793 ret = clk->set_rate(clk, rate); 794 795 return ret; 796 } 797 798 /* 799 * Converts encoded control register address into a full address 800 * On error, the return value (parent_div) will be 0. 801 */ 802 static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk, 803 u32 *field_val) 804 { 805 const struct clksel *clks; 806 const struct clksel_rate *clkr; 807 808 clks = omap2_get_clksel_by_parent(clk, src_clk); 809 if (!clks) 810 return 0; 811 812 for (clkr = clks->rates; clkr->div; clkr++) { 813 if (clkr->flags & cpu_mask && clkr->flags & DEFAULT_RATE) 814 break; /* Found the default rate for this platform */ 815 } 816 817 if (!clkr->div) { 818 printk(KERN_ERR "clock: Could not find default rate for " 819 "clock %s parent %s\n", clk->name, 820 src_clk->parent->name); 821 return 0; 822 } 823 824 /* Should never happen. Add a clksel mask to the struct clk. */ 825 WARN_ON(clk->clksel_mask == 0); 826 827 *field_val = clkr->val; 828 829 return clkr->div; 830 } 831 832 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) 833 { 834 u32 field_val, v, parent_div; 835 836 if (clk->flags & CONFIG_PARTICIPANT) 837 return -EINVAL; 838 839 if (!clk->clksel) 840 return -EINVAL; 841 842 parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val); 843 if (!parent_div) 844 return -EINVAL; 845 846 /* Set new source value (previous dividers if any in effect) */ 847 v = __raw_readl(clk->clksel_reg); 848 v &= ~clk->clksel_mask; 849 v |= field_val << __ffs(clk->clksel_mask); 850 __raw_writel(v, clk->clksel_reg); 851 v = __raw_readl(clk->clksel_reg); /* OCP barrier */ 852 853 _omap2xxx_clk_commit(clk); 854 855 clk_reparent(clk, new_parent); 856 857 /* CLKSEL clocks follow their parents' rates, divided by a divisor */ 858 clk->rate = new_parent->rate; 859 860 if (parent_div > 0) 861 clk->rate /= parent_div; 862 863 pr_debug("clock: set parent of %s to %s (new rate %ld)\n", 864 clk->name, clk->parent->name, clk->rate); 865 866 return 0; 867 } 868 869 /* DPLL rate rounding code */ 870 871 /** 872 * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding 873 * @clk: struct clk * of the DPLL 874 * @tolerance: maximum rate error tolerance 875 * 876 * Set the maximum DPLL rate error tolerance for the rate rounding 877 * algorithm. The rate tolerance is an attempt to balance DPLL power 878 * saving (the least divider value "n") vs. rate fidelity (the least 879 * difference between the desired DPLL target rate and the rounded 880 * rate out of the algorithm). So, increasing the tolerance is likely 881 * to decrease DPLL power consumption and increase DPLL rate error. 882 * Returns -EINVAL if provided a null clock ptr or a clk that is not a 883 * DPLL; or 0 upon success. 884 */ 885 int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance) 886 { 887 if (!clk || !clk->dpll_data) 888 return -EINVAL; 889 890 clk->dpll_data->rate_tolerance = tolerance; 891 892 return 0; 893 } 894 895 static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, 896 unsigned int m, unsigned int n) 897 { 898 unsigned long long num; 899 900 num = (unsigned long long)parent_rate * m; 901 do_div(num, n); 902 return num; 903 } 904 905 /* 906 * _dpll_test_mult - test a DPLL multiplier value 907 * @m: pointer to the DPLL m (multiplier) value under test 908 * @n: current DPLL n (divider) value under test 909 * @new_rate: pointer to storage for the resulting rounded rate 910 * @target_rate: the desired DPLL rate 911 * @parent_rate: the DPLL's parent clock rate 912 * 913 * This code tests a DPLL multiplier value, ensuring that the 914 * resulting rate will not be higher than the target_rate, and that 915 * the multiplier value itself is valid for the DPLL. Initially, the 916 * integer pointed to by the m argument should be prescaled by 917 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with 918 * a non-scaled m upon return. This non-scaled m will result in a 919 * new_rate as close as possible to target_rate (but not greater than 920 * target_rate) given the current (parent_rate, n, prescaled m) 921 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the 922 * non-scaled m attempted to underflow, which can allow the calling 923 * function to bail out early; or 0 upon success. 924 */ 925 static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, 926 unsigned long target_rate, 927 unsigned long parent_rate) 928 { 929 int r = 0, carry = 0; 930 931 /* Unscale m and round if necessary */ 932 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL) 933 carry = 1; 934 *m = (*m / DPLL_SCALE_FACTOR) + carry; 935 936 /* 937 * The new rate must be <= the target rate to avoid programming 938 * a rate that is impossible for the hardware to handle 939 */ 940 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); 941 if (*new_rate > target_rate) { 942 (*m)--; 943 *new_rate = 0; 944 } 945 946 /* Guard against m underflow */ 947 if (*m < DPLL_MIN_MULTIPLIER) { 948 *m = DPLL_MIN_MULTIPLIER; 949 *new_rate = 0; 950 r = DPLL_MULT_UNDERFLOW; 951 } 952 953 if (*new_rate == 0) 954 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); 955 956 return r; 957 } 958 959 /** 960 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL 961 * @clk: struct clk * for a DPLL 962 * @target_rate: desired DPLL clock rate 963 * 964 * Given a DPLL, a desired target rate, and a rate tolerance, round 965 * the target rate to a possible, programmable rate for this DPLL. 966 * Rate tolerance is assumed to be set by the caller before this 967 * function is called. Attempts to select the minimum possible n 968 * within the tolerance to reduce power consumption. Stores the 969 * computed (m, n) in the DPLL's dpll_data structure so set_rate() 970 * will not need to call this (expensive) function again. Returns ~0 971 * if the target rate cannot be rounded, either because the rate is 972 * too low or because the rate tolerance is set too tightly; or the 973 * rounded rate upon success. 974 */ 975 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) 976 { 977 int m, n, r, e, scaled_max_m; 978 unsigned long scaled_rt_rp, new_rate; 979 int min_e = -1, min_e_m = -1, min_e_n = -1; 980 struct dpll_data *dd; 981 982 if (!clk || !clk->dpll_data) 983 return ~0; 984 985 dd = clk->dpll_data; 986 987 pr_debug("clock: starting DPLL round_rate for clock %s, target rate " 988 "%ld\n", clk->name, target_rate); 989 990 scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR); 991 scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR; 992 993 dd->last_rounded_rate = 0; 994 995 for (n = dd->min_divider; n <= dd->max_divider; n++) { 996 997 /* Is the (input clk, divider) pair valid for the DPLL? */ 998 r = _dpll_test_fint(clk, n); 999 if (r == DPLL_FINT_UNDERFLOW) 1000 break; 1001 else if (r == DPLL_FINT_INVALID) 1002 continue; 1003 1004 /* Compute the scaled DPLL multiplier, based on the divider */ 1005 m = scaled_rt_rp * n; 1006 1007 /* 1008 * Since we're counting n up, a m overflow means we 1009 * can bail out completely (since as n increases in 1010 * the next iteration, there's no way that m can 1011 * increase beyond the current m) 1012 */ 1013 if (m > scaled_max_m) 1014 break; 1015 1016 r = _dpll_test_mult(&m, n, &new_rate, target_rate, 1017 dd->clk_ref->rate); 1018 1019 /* m can't be set low enough for this n - try with a larger n */ 1020 if (r == DPLL_MULT_UNDERFLOW) 1021 continue; 1022 1023 e = target_rate - new_rate; 1024 pr_debug("clock: n = %d: m = %d: rate error is %d " 1025 "(new_rate = %ld)\n", n, m, e, new_rate); 1026 1027 if (min_e == -1 || 1028 min_e >= (int)(abs(e) - dd->rate_tolerance)) { 1029 min_e = e; 1030 min_e_m = m; 1031 min_e_n = n; 1032 1033 pr_debug("clock: found new least error %d\n", min_e); 1034 1035 /* We found good settings -- bail out now */ 1036 if (min_e <= dd->rate_tolerance) 1037 break; 1038 } 1039 } 1040 1041 if (min_e < 0) { 1042 pr_debug("clock: error: target rate or tolerance too low\n"); 1043 return ~0; 1044 } 1045 1046 dd->last_rounded_m = min_e_m; 1047 dd->last_rounded_n = min_e_n; 1048 dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate, 1049 min_e_m, min_e_n); 1050 1051 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n", 1052 min_e, min_e_m, min_e_n); 1053 pr_debug("clock: final rate: %ld (target rate: %ld)\n", 1054 dd->last_rounded_rate, target_rate); 1055 1056 return dd->last_rounded_rate; 1057 } 1058 1059 /*------------------------------------------------------------------------- 1060 * Omap2 clock reset and init functions 1061 *-------------------------------------------------------------------------*/ 1062 1063 #ifdef CONFIG_OMAP_RESET_CLOCKS 1064 void omap2_clk_disable_unused(struct clk *clk) 1065 { 1066 u32 regval32, v; 1067 1068 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0; 1069 1070 regval32 = __raw_readl(clk->enable_reg); 1071 if ((regval32 & (1 << clk->enable_bit)) == v) 1072 return; 1073 1074 printk(KERN_DEBUG "Disabling unused clock \"%s\"\n", clk->name); 1075 if (cpu_is_omap34xx()) { 1076 omap2_clk_enable(clk); 1077 omap2_clk_disable(clk); 1078 } else 1079 _omap2_clk_disable(clk); 1080 if (clk->clkdm != NULL) 1081 pwrdm_clkdm_state_switch(clk->clkdm); 1082 } 1083 #endif 1084