1 /* 2 * linux/arch/arm/mach-omap2/clock.c 3 * 4 * Copyright (C) 2005-2008 Texas Instruments, Inc. 5 * Copyright (C) 2004-2008 Nokia Corporation 6 * 7 * Contacts: 8 * Richard Woodruff <r-woodruff2@ti.com> 9 * Paul Walmsley 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 #undef DEBUG 16 17 #include <linux/module.h> 18 #include <linux/kernel.h> 19 #include <linux/device.h> 20 #include <linux/list.h> 21 #include <linux/errno.h> 22 #include <linux/delay.h> 23 #include <linux/clk.h> 24 #include <linux/io.h> 25 #include <linux/bitops.h> 26 27 #include <plat/clock.h> 28 #include <plat/clockdomain.h> 29 #include <plat/cpu.h> 30 #include <plat/prcm.h> 31 #include <asm/div64.h> 32 33 #include <plat/sdrc.h> 34 #include "sdrc.h" 35 #include "clock.h" 36 #include "prm.h" 37 #include "prm-regbits-24xx.h" 38 #include "cm.h" 39 #include "cm-regbits-24xx.h" 40 #include "cm-regbits-34xx.h" 41 42 /* DPLL rate rounding: minimum DPLL multiplier, divider values */ 43 #define DPLL_MIN_MULTIPLIER 1 44 #define DPLL_MIN_DIVIDER 1 45 46 /* Possible error results from _dpll_test_mult */ 47 #define DPLL_MULT_UNDERFLOW -1 48 49 /* 50 * Scale factor to mitigate roundoff errors in DPLL rate rounding. 51 * The higher the scale factor, the greater the risk of arithmetic overflow, 52 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR 53 * must be a power of DPLL_SCALE_BASE. 54 */ 55 #define DPLL_SCALE_FACTOR 64 56 #define DPLL_SCALE_BASE 2 57 #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \ 58 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE)) 59 60 /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ 61 #define DPLL_FINT_BAND1_MIN 750000 62 #define DPLL_FINT_BAND1_MAX 2100000 63 #define DPLL_FINT_BAND2_MIN 7500000 64 #define DPLL_FINT_BAND2_MAX 21000000 65 66 /* _dpll_test_fint() return codes */ 67 #define DPLL_FINT_UNDERFLOW -1 68 #define DPLL_FINT_INVALID -2 69 70 u8 cpu_mask; 71 72 /*------------------------------------------------------------------------- 73 * OMAP2/3 specific clock functions 74 *-------------------------------------------------------------------------*/ 75 76 /** 77 * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware 78 * @clk: struct clk * 79 * 80 * If @clk has the DELAYED_APP flag set, meaning that parent/rate changes 81 * don't take effect until the VALID_CONFIG bit is written, write the 82 * VALID_CONFIG bit and wait for the write to complete. No return value. 83 */ 84 static void _omap2xxx_clk_commit(struct clk *clk) 85 { 86 if (!cpu_is_omap24xx()) 87 return; 88 89 if (!(clk->flags & DELAYED_APP)) 90 return; 91 92 prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD, 93 OMAP2_PRCM_CLKCFG_CTRL_OFFSET); 94 /* OCP barrier */ 95 prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP2_PRCM_CLKCFG_CTRL_OFFSET); 96 } 97 98 /* 99 * _dpll_test_fint - test whether an Fint value is valid for the DPLL 100 * @clk: DPLL struct clk to test 101 * @n: divider value (N) to test 102 * 103 * Tests whether a particular divider @n will result in a valid DPLL 104 * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter 105 * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate 106 * (assuming that it is counting N upwards), or -2 if the enclosing loop 107 * should skip to the next iteration (again assuming N is increasing). 108 */ 109 static int _dpll_test_fint(struct clk *clk, u8 n) 110 { 111 struct dpll_data *dd; 112 long fint; 113 int ret = 0; 114 115 dd = clk->dpll_data; 116 117 /* DPLL divider must result in a valid jitter correction val */ 118 fint = clk->parent->rate / (n + 1); 119 if (fint < DPLL_FINT_BAND1_MIN) { 120 121 pr_debug("rejecting n=%d due to Fint failure, " 122 "lowering max_divider\n", n); 123 dd->max_divider = n; 124 ret = DPLL_FINT_UNDERFLOW; 125 126 } else if (fint > DPLL_FINT_BAND1_MAX && 127 fint < DPLL_FINT_BAND2_MIN) { 128 129 pr_debug("rejecting n=%d due to Fint failure\n", n); 130 ret = DPLL_FINT_INVALID; 131 132 } else if (fint > DPLL_FINT_BAND2_MAX) { 133 134 pr_debug("rejecting n=%d due to Fint failure, " 135 "boosting min_divider\n", n); 136 dd->min_divider = n; 137 ret = DPLL_FINT_INVALID; 138 139 } 140 141 return ret; 142 } 143 144 /** 145 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk 146 * @clk: OMAP clock struct ptr to use 147 * 148 * Convert a clockdomain name stored in a struct clk 'clk' into a 149 * clockdomain pointer, and save it into the struct clk. Intended to be 150 * called during clk_register(). No return value. 151 */ 152 #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */ 153 void omap2_init_clk_clkdm(struct clk *clk) 154 { 155 struct clockdomain *clkdm; 156 157 if (!clk->clkdm_name) 158 return; 159 160 clkdm = clkdm_lookup(clk->clkdm_name); 161 if (clkdm) { 162 pr_debug("clock: associated clk %s to clkdm %s\n", 163 clk->name, clk->clkdm_name); 164 clk->clkdm = clkdm; 165 } else { 166 pr_debug("clock: could not associate clk %s to " 167 "clkdm %s\n", clk->name, clk->clkdm_name); 168 } 169 } 170 #endif 171 172 /** 173 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware 174 * @clk: OMAP clock struct ptr to use 175 * 176 * Given a pointer to a source-selectable struct clk, read the hardware 177 * register and determine what its parent is currently set to. Update the 178 * clk->parent field with the appropriate clk ptr. 179 */ 180 void omap2_init_clksel_parent(struct clk *clk) 181 { 182 const struct clksel *clks; 183 const struct clksel_rate *clkr; 184 u32 r, found = 0; 185 186 if (!clk->clksel) 187 return; 188 189 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; 190 r >>= __ffs(clk->clksel_mask); 191 192 for (clks = clk->clksel; clks->parent && !found; clks++) { 193 for (clkr = clks->rates; clkr->div && !found; clkr++) { 194 if ((clkr->flags & cpu_mask) && (clkr->val == r)) { 195 if (clk->parent != clks->parent) { 196 pr_debug("clock: inited %s parent " 197 "to %s (was %s)\n", 198 clk->name, clks->parent->name, 199 ((clk->parent) ? 200 clk->parent->name : "NULL")); 201 clk_reparent(clk, clks->parent); 202 }; 203 found = 1; 204 } 205 } 206 } 207 208 if (!found) 209 printk(KERN_ERR "clock: init parent: could not find " 210 "regval %0x for clock %s\n", r, clk->name); 211 212 return; 213 } 214 215 /** 216 * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate 217 * @clk: struct clk * of a DPLL 218 * 219 * DPLLs can be locked or bypassed - basically, enabled or disabled. 220 * When locked, the DPLL output depends on the M and N values. When 221 * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock 222 * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and 223 * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively 224 * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk. 225 * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is 226 * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0 227 * if the clock @clk is not a DPLL. 228 */ 229 u32 omap2_get_dpll_rate(struct clk *clk) 230 { 231 long long dpll_clk; 232 u32 dpll_mult, dpll_div, v; 233 struct dpll_data *dd; 234 235 dd = clk->dpll_data; 236 if (!dd) 237 return 0; 238 239 /* Return bypass rate if DPLL is bypassed */ 240 v = __raw_readl(dd->control_reg); 241 v &= dd->enable_mask; 242 v >>= __ffs(dd->enable_mask); 243 244 if (cpu_is_omap24xx()) { 245 if (v == OMAP2XXX_EN_DPLL_LPBYPASS || 246 v == OMAP2XXX_EN_DPLL_FRBYPASS) 247 return dd->clk_bypass->rate; 248 } else if (cpu_is_omap34xx()) { 249 if (v == OMAP3XXX_EN_DPLL_LPBYPASS || 250 v == OMAP3XXX_EN_DPLL_FRBYPASS) 251 return dd->clk_bypass->rate; 252 } 253 254 v = __raw_readl(dd->mult_div1_reg); 255 dpll_mult = v & dd->mult_mask; 256 dpll_mult >>= __ffs(dd->mult_mask); 257 dpll_div = v & dd->div1_mask; 258 dpll_div >>= __ffs(dd->div1_mask); 259 260 dpll_clk = (long long)dd->clk_ref->rate * dpll_mult; 261 do_div(dpll_clk, dpll_div + 1); 262 263 return dpll_clk; 264 } 265 266 /* 267 * Used for clocks that have the same value as the parent clock, 268 * divided by some factor 269 */ 270 unsigned long omap2_fixed_divisor_recalc(struct clk *clk) 271 { 272 WARN_ON(!clk->fixed_div); 273 274 return clk->parent->rate / clk->fixed_div; 275 } 276 277 /** 278 * omap2_clk_dflt_find_companion - find companion clock to @clk 279 * @clk: struct clk * to find the companion clock of 280 * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in 281 * @other_bit: u8 ** to return the companion clock bit shift in 282 * 283 * Note: We don't need special code here for INVERT_ENABLE for the 284 * time being since INVERT_ENABLE only applies to clocks enabled by 285 * CM_CLKEN_PLL 286 * 287 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's 288 * just a matter of XORing the bits. 289 * 290 * Some clocks don't have companion clocks. For example, modules with 291 * only an interface clock (such as MAILBOXES) don't have a companion 292 * clock. Right now, this code relies on the hardware exporting a bit 293 * in the correct companion register that indicates that the 294 * nonexistent 'companion clock' is active. Future patches will 295 * associate this type of code with per-module data structures to 296 * avoid this issue, and remove the casts. No return value. 297 */ 298 void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, 299 u8 *other_bit) 300 { 301 u32 r; 302 303 /* 304 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes 305 * it's just a matter of XORing the bits. 306 */ 307 r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN)); 308 309 *other_reg = (__force void __iomem *)r; 310 *other_bit = clk->enable_bit; 311 } 312 313 /** 314 * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk 315 * @clk: struct clk * to find IDLEST info for 316 * @idlest_reg: void __iomem ** to return the CM_IDLEST va in 317 * @idlest_bit: u8 ** to return the CM_IDLEST bit shift in 318 * 319 * Return the CM_IDLEST register address and bit shift corresponding 320 * to the module that "owns" this clock. This default code assumes 321 * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that 322 * the IDLEST register address ID corresponds to the CM_*CLKEN 323 * register address ID (e.g., that CM_FCLKEN2 corresponds to 324 * CM_IDLEST2). This is not true for all modules. No return value. 325 */ 326 void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, 327 u8 *idlest_bit) 328 { 329 u32 r; 330 331 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); 332 *idlest_reg = (__force void __iomem *)r; 333 *idlest_bit = clk->enable_bit; 334 } 335 336 /** 337 * omap2_module_wait_ready - wait for an OMAP module to leave IDLE 338 * @clk: struct clk * belonging to the module 339 * 340 * If the necessary clocks for the OMAP hardware IP block that 341 * corresponds to clock @clk are enabled, then wait for the module to 342 * indicate readiness (i.e., to leave IDLE). This code does not 343 * belong in the clock code and will be moved in the medium term to 344 * module-dependent code. No return value. 345 */ 346 static void omap2_module_wait_ready(struct clk *clk) 347 { 348 void __iomem *companion_reg, *idlest_reg; 349 u8 other_bit, idlest_bit; 350 351 /* Not all modules have multiple clocks that their IDLEST depends on */ 352 if (clk->ops->find_companion) { 353 clk->ops->find_companion(clk, &companion_reg, &other_bit); 354 if (!(__raw_readl(companion_reg) & (1 << other_bit))) 355 return; 356 } 357 358 clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit); 359 360 omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), clk->name); 361 } 362 363 int omap2_dflt_clk_enable(struct clk *clk) 364 { 365 u32 v; 366 367 if (unlikely(clk->enable_reg == NULL)) { 368 pr_err("clock.c: Enable for %s without enable code\n", 369 clk->name); 370 return 0; /* REVISIT: -EINVAL */ 371 } 372 373 v = __raw_readl(clk->enable_reg); 374 if (clk->flags & INVERT_ENABLE) 375 v &= ~(1 << clk->enable_bit); 376 else 377 v |= (1 << clk->enable_bit); 378 __raw_writel(v, clk->enable_reg); 379 v = __raw_readl(clk->enable_reg); /* OCP barrier */ 380 381 if (clk->ops->find_idlest) 382 omap2_module_wait_ready(clk); 383 384 return 0; 385 } 386 387 void omap2_dflt_clk_disable(struct clk *clk) 388 { 389 u32 v; 390 391 if (!clk->enable_reg) { 392 /* 393 * 'Independent' here refers to a clock which is not 394 * controlled by its parent. 395 */ 396 printk(KERN_ERR "clock: clk_disable called on independent " 397 "clock %s which has no enable_reg\n", clk->name); 398 return; 399 } 400 401 v = __raw_readl(clk->enable_reg); 402 if (clk->flags & INVERT_ENABLE) 403 v |= (1 << clk->enable_bit); 404 else 405 v &= ~(1 << clk->enable_bit); 406 __raw_writel(v, clk->enable_reg); 407 /* No OCP barrier needed here since it is a disable operation */ 408 } 409 410 const struct clkops clkops_omap2_dflt_wait = { 411 .enable = omap2_dflt_clk_enable, 412 .disable = omap2_dflt_clk_disable, 413 .find_companion = omap2_clk_dflt_find_companion, 414 .find_idlest = omap2_clk_dflt_find_idlest, 415 }; 416 417 const struct clkops clkops_omap2_dflt = { 418 .enable = omap2_dflt_clk_enable, 419 .disable = omap2_dflt_clk_disable, 420 }; 421 422 /* Enables clock without considering parent dependencies or use count 423 * REVISIT: Maybe change this to use clk->enable like on omap1? 424 */ 425 static int _omap2_clk_enable(struct clk *clk) 426 { 427 return clk->ops->enable(clk); 428 } 429 430 /* Disables clock without considering parent dependencies or use count */ 431 static void _omap2_clk_disable(struct clk *clk) 432 { 433 clk->ops->disable(clk); 434 } 435 436 void omap2_clk_disable(struct clk *clk) 437 { 438 if (clk->usecount > 0 && !(--clk->usecount)) { 439 _omap2_clk_disable(clk); 440 if (clk->parent) 441 omap2_clk_disable(clk->parent); 442 #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */ 443 if (clk->clkdm) 444 omap2_clkdm_clk_disable(clk->clkdm, clk); 445 #endif 446 447 } 448 } 449 450 int omap2_clk_enable(struct clk *clk) 451 { 452 int ret = 0; 453 454 if (clk->usecount++ == 0) { 455 #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */ 456 if (clk->clkdm) 457 omap2_clkdm_clk_enable(clk->clkdm, clk); 458 #endif 459 460 if (clk->parent) { 461 ret = omap2_clk_enable(clk->parent); 462 if (ret) 463 goto err; 464 } 465 466 ret = _omap2_clk_enable(clk); 467 if (ret) { 468 if (clk->parent) 469 omap2_clk_disable(clk->parent); 470 471 goto err; 472 } 473 } 474 return ret; 475 476 err: 477 #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */ 478 if (clk->clkdm) 479 omap2_clkdm_clk_disable(clk->clkdm, clk); 480 #endif 481 clk->usecount--; 482 return ret; 483 } 484 485 /* 486 * Used for clocks that are part of CLKSEL_xyz governed clocks. 487 * REVISIT: Maybe change to use clk->enable() functions like on omap1? 488 */ 489 unsigned long omap2_clksel_recalc(struct clk *clk) 490 { 491 unsigned long rate; 492 u32 div = 0; 493 494 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name); 495 496 div = omap2_clksel_get_divisor(clk); 497 if (div == 0) 498 return clk->rate; 499 500 rate = clk->parent->rate / div; 501 502 pr_debug("clock: new clock rate is %ld (div %d)\n", rate, div); 503 504 return rate; 505 } 506 507 /** 508 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent 509 * @clk: OMAP struct clk ptr to inspect 510 * @src_clk: OMAP struct clk ptr of the parent clk to search for 511 * 512 * Scan the struct clksel array associated with the clock to find 513 * the element associated with the supplied parent clock address. 514 * Returns a pointer to the struct clksel on success or NULL on error. 515 */ 516 static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk, 517 struct clk *src_clk) 518 { 519 const struct clksel *clks; 520 521 if (!clk->clksel) 522 return NULL; 523 524 for (clks = clk->clksel; clks->parent; clks++) { 525 if (clks->parent == src_clk) 526 break; /* Found the requested parent */ 527 } 528 529 if (!clks->parent) { 530 printk(KERN_ERR "clock: Could not find parent clock %s in " 531 "clksel array of clock %s\n", src_clk->name, 532 clk->name); 533 return NULL; 534 } 535 536 return clks; 537 } 538 539 /** 540 * omap2_clksel_round_rate_div - find divisor for the given clock and rate 541 * @clk: OMAP struct clk to use 542 * @target_rate: desired clock rate 543 * @new_div: ptr to where we should store the divisor 544 * 545 * Finds 'best' divider value in an array based on the source and target 546 * rates. The divider array must be sorted with smallest divider first. 547 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, 548 * they are only settable as part of virtual_prcm set. 549 * 550 * Returns the rounded clock rate or returns 0xffffffff on error. 551 */ 552 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, 553 u32 *new_div) 554 { 555 unsigned long test_rate; 556 const struct clksel *clks; 557 const struct clksel_rate *clkr; 558 u32 last_div = 0; 559 560 pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n", 561 clk->name, target_rate); 562 563 *new_div = 1; 564 565 clks = omap2_get_clksel_by_parent(clk, clk->parent); 566 if (!clks) 567 return ~0; 568 569 for (clkr = clks->rates; clkr->div; clkr++) { 570 if (!(clkr->flags & cpu_mask)) 571 continue; 572 573 /* Sanity check */ 574 if (clkr->div <= last_div) 575 pr_err("clock: clksel_rate table not sorted " 576 "for clock %s", clk->name); 577 578 last_div = clkr->div; 579 580 test_rate = clk->parent->rate / clkr->div; 581 582 if (test_rate <= target_rate) 583 break; /* found it */ 584 } 585 586 if (!clkr->div) { 587 pr_err("clock: Could not find divisor for target " 588 "rate %ld for clock %s parent %s\n", target_rate, 589 clk->name, clk->parent->name); 590 return ~0; 591 } 592 593 *new_div = clkr->div; 594 595 pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div, 596 (clk->parent->rate / clkr->div)); 597 598 return (clk->parent->rate / clkr->div); 599 } 600 601 /** 602 * omap2_clksel_round_rate - find rounded rate for the given clock and rate 603 * @clk: OMAP struct clk to use 604 * @target_rate: desired clock rate 605 * 606 * Compatibility wrapper for OMAP clock framework 607 * Finds best target rate based on the source clock and possible dividers. 608 * rates. The divider array must be sorted with smallest divider first. 609 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, 610 * they are only settable as part of virtual_prcm set. 611 * 612 * Returns the rounded clock rate or returns 0xffffffff on error. 613 */ 614 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) 615 { 616 u32 new_div; 617 618 return omap2_clksel_round_rate_div(clk, target_rate, &new_div); 619 } 620 621 622 /* Given a clock and a rate apply a clock specific rounding function */ 623 long omap2_clk_round_rate(struct clk *clk, unsigned long rate) 624 { 625 if (clk->round_rate) 626 return clk->round_rate(clk, rate); 627 628 if (clk->flags & RATE_FIXED) 629 printk(KERN_ERR "clock: generic omap2_clk_round_rate called " 630 "on fixed-rate clock %s\n", clk->name); 631 632 return clk->rate; 633 } 634 635 /** 636 * omap2_clksel_to_divisor() - turn clksel field value into integer divider 637 * @clk: OMAP struct clk to use 638 * @field_val: register field value to find 639 * 640 * Given a struct clk of a rate-selectable clksel clock, and a register field 641 * value to search for, find the corresponding clock divisor. The register 642 * field value should be pre-masked and shifted down so the LSB is at bit 0 643 * before calling. Returns 0 on error 644 */ 645 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val) 646 { 647 const struct clksel *clks; 648 const struct clksel_rate *clkr; 649 650 clks = omap2_get_clksel_by_parent(clk, clk->parent); 651 if (!clks) 652 return 0; 653 654 for (clkr = clks->rates; clkr->div; clkr++) { 655 if ((clkr->flags & cpu_mask) && (clkr->val == field_val)) 656 break; 657 } 658 659 if (!clkr->div) { 660 printk(KERN_ERR "clock: Could not find fieldval %d for " 661 "clock %s parent %s\n", field_val, clk->name, 662 clk->parent->name); 663 return 0; 664 } 665 666 return clkr->div; 667 } 668 669 /** 670 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value 671 * @clk: OMAP struct clk to use 672 * @div: integer divisor to search for 673 * 674 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor, 675 * find the corresponding register field value. The return register value is 676 * the value before left-shifting. Returns ~0 on error 677 */ 678 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div) 679 { 680 const struct clksel *clks; 681 const struct clksel_rate *clkr; 682 683 /* should never happen */ 684 WARN_ON(div == 0); 685 686 clks = omap2_get_clksel_by_parent(clk, clk->parent); 687 if (!clks) 688 return ~0; 689 690 for (clkr = clks->rates; clkr->div; clkr++) { 691 if ((clkr->flags & cpu_mask) && (clkr->div == div)) 692 break; 693 } 694 695 if (!clkr->div) { 696 printk(KERN_ERR "clock: Could not find divisor %d for " 697 "clock %s parent %s\n", div, clk->name, 698 clk->parent->name); 699 return ~0; 700 } 701 702 return clkr->val; 703 } 704 705 /** 706 * omap2_clksel_get_divisor - get current divider applied to parent clock. 707 * @clk: OMAP struct clk to use. 708 * 709 * Returns the integer divisor upon success or 0 on error. 710 */ 711 u32 omap2_clksel_get_divisor(struct clk *clk) 712 { 713 u32 v; 714 715 if (!clk->clksel_mask) 716 return 0; 717 718 v = __raw_readl(clk->clksel_reg) & clk->clksel_mask; 719 v >>= __ffs(clk->clksel_mask); 720 721 return omap2_clksel_to_divisor(clk, v); 722 } 723 724 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) 725 { 726 u32 v, field_val, validrate, new_div = 0; 727 728 if (!clk->clksel_mask) 729 return -EINVAL; 730 731 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); 732 if (validrate != rate) 733 return -EINVAL; 734 735 field_val = omap2_divisor_to_clksel(clk, new_div); 736 if (field_val == ~0) 737 return -EINVAL; 738 739 v = __raw_readl(clk->clksel_reg); 740 v &= ~clk->clksel_mask; 741 v |= field_val << __ffs(clk->clksel_mask); 742 __raw_writel(v, clk->clksel_reg); 743 v = __raw_readl(clk->clksel_reg); /* OCP barrier */ 744 745 clk->rate = clk->parent->rate / new_div; 746 747 _omap2xxx_clk_commit(clk); 748 749 return 0; 750 } 751 752 753 /* Set the clock rate for a clock source */ 754 int omap2_clk_set_rate(struct clk *clk, unsigned long rate) 755 { 756 int ret = -EINVAL; 757 758 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate); 759 760 /* CONFIG_PARTICIPANT clocks are changed only in sets via the 761 rate table mechanism, driven by mpu_speed */ 762 if (clk->flags & CONFIG_PARTICIPANT) 763 return -EINVAL; 764 765 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ 766 if (clk->set_rate) 767 ret = clk->set_rate(clk, rate); 768 769 return ret; 770 } 771 772 /* 773 * Converts encoded control register address into a full address 774 * On error, the return value (parent_div) will be 0. 775 */ 776 static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk, 777 u32 *field_val) 778 { 779 const struct clksel *clks; 780 const struct clksel_rate *clkr; 781 782 clks = omap2_get_clksel_by_parent(clk, src_clk); 783 if (!clks) 784 return 0; 785 786 for (clkr = clks->rates; clkr->div; clkr++) { 787 if (clkr->flags & cpu_mask && clkr->flags & DEFAULT_RATE) 788 break; /* Found the default rate for this platform */ 789 } 790 791 if (!clkr->div) { 792 printk(KERN_ERR "clock: Could not find default rate for " 793 "clock %s parent %s\n", clk->name, 794 src_clk->parent->name); 795 return 0; 796 } 797 798 /* Should never happen. Add a clksel mask to the struct clk. */ 799 WARN_ON(clk->clksel_mask == 0); 800 801 *field_val = clkr->val; 802 803 return clkr->div; 804 } 805 806 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) 807 { 808 u32 field_val, v, parent_div; 809 810 if (clk->flags & CONFIG_PARTICIPANT) 811 return -EINVAL; 812 813 if (!clk->clksel) 814 return -EINVAL; 815 816 parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val); 817 if (!parent_div) 818 return -EINVAL; 819 820 /* Set new source value (previous dividers if any in effect) */ 821 v = __raw_readl(clk->clksel_reg); 822 v &= ~clk->clksel_mask; 823 v |= field_val << __ffs(clk->clksel_mask); 824 __raw_writel(v, clk->clksel_reg); 825 v = __raw_readl(clk->clksel_reg); /* OCP barrier */ 826 827 _omap2xxx_clk_commit(clk); 828 829 clk_reparent(clk, new_parent); 830 831 /* CLKSEL clocks follow their parents' rates, divided by a divisor */ 832 clk->rate = new_parent->rate; 833 834 if (parent_div > 0) 835 clk->rate /= parent_div; 836 837 pr_debug("clock: set parent of %s to %s (new rate %ld)\n", 838 clk->name, clk->parent->name, clk->rate); 839 840 return 0; 841 } 842 843 /* DPLL rate rounding code */ 844 845 /** 846 * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding 847 * @clk: struct clk * of the DPLL 848 * @tolerance: maximum rate error tolerance 849 * 850 * Set the maximum DPLL rate error tolerance for the rate rounding 851 * algorithm. The rate tolerance is an attempt to balance DPLL power 852 * saving (the least divider value "n") vs. rate fidelity (the least 853 * difference between the desired DPLL target rate and the rounded 854 * rate out of the algorithm). So, increasing the tolerance is likely 855 * to decrease DPLL power consumption and increase DPLL rate error. 856 * Returns -EINVAL if provided a null clock ptr or a clk that is not a 857 * DPLL; or 0 upon success. 858 */ 859 int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance) 860 { 861 if (!clk || !clk->dpll_data) 862 return -EINVAL; 863 864 clk->dpll_data->rate_tolerance = tolerance; 865 866 return 0; 867 } 868 869 static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, 870 unsigned int m, unsigned int n) 871 { 872 unsigned long long num; 873 874 num = (unsigned long long)parent_rate * m; 875 do_div(num, n); 876 return num; 877 } 878 879 /* 880 * _dpll_test_mult - test a DPLL multiplier value 881 * @m: pointer to the DPLL m (multiplier) value under test 882 * @n: current DPLL n (divider) value under test 883 * @new_rate: pointer to storage for the resulting rounded rate 884 * @target_rate: the desired DPLL rate 885 * @parent_rate: the DPLL's parent clock rate 886 * 887 * This code tests a DPLL multiplier value, ensuring that the 888 * resulting rate will not be higher than the target_rate, and that 889 * the multiplier value itself is valid for the DPLL. Initially, the 890 * integer pointed to by the m argument should be prescaled by 891 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with 892 * a non-scaled m upon return. This non-scaled m will result in a 893 * new_rate as close as possible to target_rate (but not greater than 894 * target_rate) given the current (parent_rate, n, prescaled m) 895 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the 896 * non-scaled m attempted to underflow, which can allow the calling 897 * function to bail out early; or 0 upon success. 898 */ 899 static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, 900 unsigned long target_rate, 901 unsigned long parent_rate) 902 { 903 int r = 0, carry = 0; 904 905 /* Unscale m and round if necessary */ 906 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL) 907 carry = 1; 908 *m = (*m / DPLL_SCALE_FACTOR) + carry; 909 910 /* 911 * The new rate must be <= the target rate to avoid programming 912 * a rate that is impossible for the hardware to handle 913 */ 914 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); 915 if (*new_rate > target_rate) { 916 (*m)--; 917 *new_rate = 0; 918 } 919 920 /* Guard against m underflow */ 921 if (*m < DPLL_MIN_MULTIPLIER) { 922 *m = DPLL_MIN_MULTIPLIER; 923 *new_rate = 0; 924 r = DPLL_MULT_UNDERFLOW; 925 } 926 927 if (*new_rate == 0) 928 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); 929 930 return r; 931 } 932 933 /** 934 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL 935 * @clk: struct clk * for a DPLL 936 * @target_rate: desired DPLL clock rate 937 * 938 * Given a DPLL, a desired target rate, and a rate tolerance, round 939 * the target rate to a possible, programmable rate for this DPLL. 940 * Rate tolerance is assumed to be set by the caller before this 941 * function is called. Attempts to select the minimum possible n 942 * within the tolerance to reduce power consumption. Stores the 943 * computed (m, n) in the DPLL's dpll_data structure so set_rate() 944 * will not need to call this (expensive) function again. Returns ~0 945 * if the target rate cannot be rounded, either because the rate is 946 * too low or because the rate tolerance is set too tightly; or the 947 * rounded rate upon success. 948 */ 949 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) 950 { 951 int m, n, r, e, scaled_max_m; 952 unsigned long scaled_rt_rp, new_rate; 953 int min_e = -1, min_e_m = -1, min_e_n = -1; 954 struct dpll_data *dd; 955 956 if (!clk || !clk->dpll_data) 957 return ~0; 958 959 dd = clk->dpll_data; 960 961 pr_debug("clock: starting DPLL round_rate for clock %s, target rate " 962 "%ld\n", clk->name, target_rate); 963 964 scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR); 965 scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR; 966 967 dd->last_rounded_rate = 0; 968 969 for (n = dd->min_divider; n <= dd->max_divider; n++) { 970 971 /* Is the (input clk, divider) pair valid for the DPLL? */ 972 r = _dpll_test_fint(clk, n); 973 if (r == DPLL_FINT_UNDERFLOW) 974 break; 975 else if (r == DPLL_FINT_INVALID) 976 continue; 977 978 /* Compute the scaled DPLL multiplier, based on the divider */ 979 m = scaled_rt_rp * n; 980 981 /* 982 * Since we're counting n up, a m overflow means we 983 * can bail out completely (since as n increases in 984 * the next iteration, there's no way that m can 985 * increase beyond the current m) 986 */ 987 if (m > scaled_max_m) 988 break; 989 990 r = _dpll_test_mult(&m, n, &new_rate, target_rate, 991 dd->clk_ref->rate); 992 993 /* m can't be set low enough for this n - try with a larger n */ 994 if (r == DPLL_MULT_UNDERFLOW) 995 continue; 996 997 e = target_rate - new_rate; 998 pr_debug("clock: n = %d: m = %d: rate error is %d " 999 "(new_rate = %ld)\n", n, m, e, new_rate); 1000 1001 if (min_e == -1 || 1002 min_e >= (int)(abs(e) - dd->rate_tolerance)) { 1003 min_e = e; 1004 min_e_m = m; 1005 min_e_n = n; 1006 1007 pr_debug("clock: found new least error %d\n", min_e); 1008 1009 /* We found good settings -- bail out now */ 1010 if (min_e <= dd->rate_tolerance) 1011 break; 1012 } 1013 } 1014 1015 if (min_e < 0) { 1016 pr_debug("clock: error: target rate or tolerance too low\n"); 1017 return ~0; 1018 } 1019 1020 dd->last_rounded_m = min_e_m; 1021 dd->last_rounded_n = min_e_n; 1022 dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate, 1023 min_e_m, min_e_n); 1024 1025 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n", 1026 min_e, min_e_m, min_e_n); 1027 pr_debug("clock: final rate: %ld (target rate: %ld)\n", 1028 dd->last_rounded_rate, target_rate); 1029 1030 return dd->last_rounded_rate; 1031 } 1032 1033 /*------------------------------------------------------------------------- 1034 * Omap2 clock reset and init functions 1035 *-------------------------------------------------------------------------*/ 1036 1037 #ifdef CONFIG_OMAP_RESET_CLOCKS 1038 void omap2_clk_disable_unused(struct clk *clk) 1039 { 1040 u32 regval32, v; 1041 1042 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0; 1043 1044 regval32 = __raw_readl(clk->enable_reg); 1045 if ((regval32 & (1 << clk->enable_bit)) == v) 1046 return; 1047 1048 printk(KERN_DEBUG "Disabling unused clock \"%s\"\n", clk->name); 1049 if (cpu_is_omap34xx()) { 1050 omap2_clk_enable(clk); 1051 omap2_clk_disable(clk); 1052 } else 1053 _omap2_clk_disable(clk); 1054 if (clk->clkdm != NULL) 1055 pwrdm_clkdm_state_switch(clk->clkdm); 1056 } 1057 #endif 1058