1 /* 2 * linux/arch/arm/mach-omap2/clock.c 3 * 4 * Copyright (C) 2005-2008 Texas Instruments, Inc. 5 * Copyright (C) 2004-2008 Nokia Corporation 6 * 7 * Contacts: 8 * Richard Woodruff <r-woodruff2@ti.com> 9 * Paul Walmsley 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 #undef DEBUG 16 17 #include <linux/module.h> 18 #include <linux/kernel.h> 19 #include <linux/device.h> 20 #include <linux/list.h> 21 #include <linux/errno.h> 22 #include <linux/delay.h> 23 #include <linux/clk.h> 24 #include <linux/io.h> 25 #include <linux/bitops.h> 26 27 #include <plat/clock.h> 28 #include <plat/clockdomain.h> 29 #include <plat/cpu.h> 30 #include <plat/prcm.h> 31 #include <asm/div64.h> 32 33 #include <plat/sdrc.h> 34 #include "sdrc.h" 35 #include "clock.h" 36 #include "prm.h" 37 #include "prm-regbits-24xx.h" 38 #include "cm.h" 39 #include "cm-regbits-24xx.h" 40 #include "cm-regbits-34xx.h" 41 42 /* DPLL rate rounding: minimum DPLL multiplier, divider values */ 43 #define DPLL_MIN_MULTIPLIER 1 44 #define DPLL_MIN_DIVIDER 1 45 46 /* Possible error results from _dpll_test_mult */ 47 #define DPLL_MULT_UNDERFLOW -1 48 49 /* 50 * Scale factor to mitigate roundoff errors in DPLL rate rounding. 51 * The higher the scale factor, the greater the risk of arithmetic overflow, 52 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR 53 * must be a power of DPLL_SCALE_BASE. 54 */ 55 #define DPLL_SCALE_FACTOR 64 56 #define DPLL_SCALE_BASE 2 57 #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \ 58 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE)) 59 60 /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ 61 #define DPLL_FINT_BAND1_MIN 750000 62 #define DPLL_FINT_BAND1_MAX 2100000 63 #define DPLL_FINT_BAND2_MIN 7500000 64 #define DPLL_FINT_BAND2_MAX 21000000 65 66 /* _dpll_test_fint() return codes */ 67 #define DPLL_FINT_UNDERFLOW -1 68 #define DPLL_FINT_INVALID -2 69 70 u8 cpu_mask; 71 72 /*------------------------------------------------------------------------- 73 * OMAP2/3/4 specific clock functions 74 *-------------------------------------------------------------------------*/ 75 76 void omap2_init_dpll_parent(struct clk *clk) 77 { 78 u32 v; 79 struct dpll_data *dd; 80 81 dd = clk->dpll_data; 82 if (!dd) 83 return; 84 85 /* Return bypass rate if DPLL is bypassed */ 86 v = __raw_readl(dd->control_reg); 87 v &= dd->enable_mask; 88 v >>= __ffs(dd->enable_mask); 89 90 /* Reparent in case the dpll is in bypass */ 91 if (cpu_is_omap24xx()) { 92 if (v == OMAP2XXX_EN_DPLL_LPBYPASS || 93 v == OMAP2XXX_EN_DPLL_FRBYPASS) 94 clk_reparent(clk, dd->clk_bypass); 95 } else if (cpu_is_omap34xx()) { 96 if (v == OMAP3XXX_EN_DPLL_LPBYPASS || 97 v == OMAP3XXX_EN_DPLL_FRBYPASS) 98 clk_reparent(clk, dd->clk_bypass); 99 } else if (cpu_is_omap44xx()) { 100 if (v == OMAP4XXX_EN_DPLL_LPBYPASS || 101 v == OMAP4XXX_EN_DPLL_FRBYPASS || 102 v == OMAP4XXX_EN_DPLL_MNBYPASS) 103 clk_reparent(clk, dd->clk_bypass); 104 } 105 return; 106 } 107 108 /** 109 * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware 110 * @clk: struct clk * 111 * 112 * If @clk has the DELAYED_APP flag set, meaning that parent/rate changes 113 * don't take effect until the VALID_CONFIG bit is written, write the 114 * VALID_CONFIG bit and wait for the write to complete. No return value. 115 */ 116 static void _omap2xxx_clk_commit(struct clk *clk) 117 { 118 if (!cpu_is_omap24xx()) 119 return; 120 121 if (!(clk->flags & DELAYED_APP)) 122 return; 123 124 prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD, 125 OMAP2_PRCM_CLKCFG_CTRL_OFFSET); 126 /* OCP barrier */ 127 prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP2_PRCM_CLKCFG_CTRL_OFFSET); 128 } 129 130 /* 131 * _dpll_test_fint - test whether an Fint value is valid for the DPLL 132 * @clk: DPLL struct clk to test 133 * @n: divider value (N) to test 134 * 135 * Tests whether a particular divider @n will result in a valid DPLL 136 * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter 137 * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate 138 * (assuming that it is counting N upwards), or -2 if the enclosing loop 139 * should skip to the next iteration (again assuming N is increasing). 140 */ 141 static int _dpll_test_fint(struct clk *clk, u8 n) 142 { 143 struct dpll_data *dd; 144 long fint; 145 int ret = 0; 146 147 dd = clk->dpll_data; 148 149 /* DPLL divider must result in a valid jitter correction val */ 150 fint = clk->parent->rate / (n + 1); 151 if (fint < DPLL_FINT_BAND1_MIN) { 152 153 pr_debug("rejecting n=%d due to Fint failure, " 154 "lowering max_divider\n", n); 155 dd->max_divider = n; 156 ret = DPLL_FINT_UNDERFLOW; 157 158 } else if (fint > DPLL_FINT_BAND1_MAX && 159 fint < DPLL_FINT_BAND2_MIN) { 160 161 pr_debug("rejecting n=%d due to Fint failure\n", n); 162 ret = DPLL_FINT_INVALID; 163 164 } else if (fint > DPLL_FINT_BAND2_MAX) { 165 166 pr_debug("rejecting n=%d due to Fint failure, " 167 "boosting min_divider\n", n); 168 dd->min_divider = n; 169 ret = DPLL_FINT_INVALID; 170 171 } 172 173 return ret; 174 } 175 176 /** 177 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk 178 * @clk: OMAP clock struct ptr to use 179 * 180 * Convert a clockdomain name stored in a struct clk 'clk' into a 181 * clockdomain pointer, and save it into the struct clk. Intended to be 182 * called during clk_register(). No return value. 183 */ 184 void omap2_init_clk_clkdm(struct clk *clk) 185 { 186 struct clockdomain *clkdm; 187 188 if (!clk->clkdm_name) 189 return; 190 191 clkdm = clkdm_lookup(clk->clkdm_name); 192 if (clkdm) { 193 pr_debug("clock: associated clk %s to clkdm %s\n", 194 clk->name, clk->clkdm_name); 195 clk->clkdm = clkdm; 196 } else { 197 pr_debug("clock: could not associate clk %s to " 198 "clkdm %s\n", clk->name, clk->clkdm_name); 199 } 200 } 201 202 /** 203 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware 204 * @clk: OMAP clock struct ptr to use 205 * 206 * Given a pointer to a source-selectable struct clk, read the hardware 207 * register and determine what its parent is currently set to. Update the 208 * clk->parent field with the appropriate clk ptr. 209 */ 210 void omap2_init_clksel_parent(struct clk *clk) 211 { 212 const struct clksel *clks; 213 const struct clksel_rate *clkr; 214 u32 r, found = 0; 215 216 if (!clk->clksel) 217 return; 218 219 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; 220 r >>= __ffs(clk->clksel_mask); 221 222 for (clks = clk->clksel; clks->parent && !found; clks++) { 223 for (clkr = clks->rates; clkr->div && !found; clkr++) { 224 if ((clkr->flags & cpu_mask) && (clkr->val == r)) { 225 if (clk->parent != clks->parent) { 226 pr_debug("clock: inited %s parent " 227 "to %s (was %s)\n", 228 clk->name, clks->parent->name, 229 ((clk->parent) ? 230 clk->parent->name : "NULL")); 231 clk_reparent(clk, clks->parent); 232 }; 233 found = 1; 234 } 235 } 236 } 237 238 if (!found) 239 printk(KERN_ERR "clock: init parent: could not find " 240 "regval %0x for clock %s\n", r, clk->name); 241 242 return; 243 } 244 245 /** 246 * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate 247 * @clk: struct clk * of a DPLL 248 * 249 * DPLLs can be locked or bypassed - basically, enabled or disabled. 250 * When locked, the DPLL output depends on the M and N values. When 251 * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock 252 * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and 253 * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively 254 * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk. 255 * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is 256 * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0 257 * if the clock @clk is not a DPLL. 258 */ 259 u32 omap2_get_dpll_rate(struct clk *clk) 260 { 261 long long dpll_clk; 262 u32 dpll_mult, dpll_div, v; 263 struct dpll_data *dd; 264 265 dd = clk->dpll_data; 266 if (!dd) 267 return 0; 268 269 /* Return bypass rate if DPLL is bypassed */ 270 v = __raw_readl(dd->control_reg); 271 v &= dd->enable_mask; 272 v >>= __ffs(dd->enable_mask); 273 274 if (cpu_is_omap24xx()) { 275 if (v == OMAP2XXX_EN_DPLL_LPBYPASS || 276 v == OMAP2XXX_EN_DPLL_FRBYPASS) 277 return dd->clk_bypass->rate; 278 } else if (cpu_is_omap34xx()) { 279 if (v == OMAP3XXX_EN_DPLL_LPBYPASS || 280 v == OMAP3XXX_EN_DPLL_FRBYPASS) 281 return dd->clk_bypass->rate; 282 } else if (cpu_is_omap44xx()) { 283 if (v == OMAP4XXX_EN_DPLL_LPBYPASS || 284 v == OMAP4XXX_EN_DPLL_FRBYPASS || 285 v == OMAP4XXX_EN_DPLL_MNBYPASS) 286 return dd->clk_bypass->rate; 287 } 288 289 v = __raw_readl(dd->mult_div1_reg); 290 dpll_mult = v & dd->mult_mask; 291 dpll_mult >>= __ffs(dd->mult_mask); 292 dpll_div = v & dd->div1_mask; 293 dpll_div >>= __ffs(dd->div1_mask); 294 295 dpll_clk = (long long)dd->clk_ref->rate * dpll_mult; 296 do_div(dpll_clk, dpll_div + 1); 297 298 return dpll_clk; 299 } 300 301 /** 302 * omap2_clk_dflt_find_companion - find companion clock to @clk 303 * @clk: struct clk * to find the companion clock of 304 * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in 305 * @other_bit: u8 ** to return the companion clock bit shift in 306 * 307 * Note: We don't need special code here for INVERT_ENABLE for the 308 * time being since INVERT_ENABLE only applies to clocks enabled by 309 * CM_CLKEN_PLL 310 * 311 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's 312 * just a matter of XORing the bits. 313 * 314 * Some clocks don't have companion clocks. For example, modules with 315 * only an interface clock (such as MAILBOXES) don't have a companion 316 * clock. Right now, this code relies on the hardware exporting a bit 317 * in the correct companion register that indicates that the 318 * nonexistent 'companion clock' is active. Future patches will 319 * associate this type of code with per-module data structures to 320 * avoid this issue, and remove the casts. No return value. 321 */ 322 void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, 323 u8 *other_bit) 324 { 325 u32 r; 326 327 /* 328 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes 329 * it's just a matter of XORing the bits. 330 */ 331 r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN)); 332 333 *other_reg = (__force void __iomem *)r; 334 *other_bit = clk->enable_bit; 335 } 336 337 /** 338 * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk 339 * @clk: struct clk * to find IDLEST info for 340 * @idlest_reg: void __iomem ** to return the CM_IDLEST va in 341 * @idlest_bit: u8 ** to return the CM_IDLEST bit shift in 342 * 343 * Return the CM_IDLEST register address and bit shift corresponding 344 * to the module that "owns" this clock. This default code assumes 345 * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that 346 * the IDLEST register address ID corresponds to the CM_*CLKEN 347 * register address ID (e.g., that CM_FCLKEN2 corresponds to 348 * CM_IDLEST2). This is not true for all modules. No return value. 349 */ 350 void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, 351 u8 *idlest_bit) 352 { 353 u32 r; 354 355 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); 356 *idlest_reg = (__force void __iomem *)r; 357 *idlest_bit = clk->enable_bit; 358 } 359 360 /** 361 * omap2_module_wait_ready - wait for an OMAP module to leave IDLE 362 * @clk: struct clk * belonging to the module 363 * 364 * If the necessary clocks for the OMAP hardware IP block that 365 * corresponds to clock @clk are enabled, then wait for the module to 366 * indicate readiness (i.e., to leave IDLE). This code does not 367 * belong in the clock code and will be moved in the medium term to 368 * module-dependent code. No return value. 369 */ 370 static void omap2_module_wait_ready(struct clk *clk) 371 { 372 void __iomem *companion_reg, *idlest_reg; 373 u8 other_bit, idlest_bit; 374 375 /* Not all modules have multiple clocks that their IDLEST depends on */ 376 if (clk->ops->find_companion) { 377 clk->ops->find_companion(clk, &companion_reg, &other_bit); 378 if (!(__raw_readl(companion_reg) & (1 << other_bit))) 379 return; 380 } 381 382 clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit); 383 384 omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), clk->name); 385 } 386 387 int omap2_dflt_clk_enable(struct clk *clk) 388 { 389 u32 v; 390 391 if (unlikely(clk->enable_reg == NULL)) { 392 pr_err("clock.c: Enable for %s without enable code\n", 393 clk->name); 394 return 0; /* REVISIT: -EINVAL */ 395 } 396 397 v = __raw_readl(clk->enable_reg); 398 if (clk->flags & INVERT_ENABLE) 399 v &= ~(1 << clk->enable_bit); 400 else 401 v |= (1 << clk->enable_bit); 402 __raw_writel(v, clk->enable_reg); 403 v = __raw_readl(clk->enable_reg); /* OCP barrier */ 404 405 if (clk->ops->find_idlest) 406 omap2_module_wait_ready(clk); 407 408 return 0; 409 } 410 411 void omap2_dflt_clk_disable(struct clk *clk) 412 { 413 u32 v; 414 415 if (!clk->enable_reg) { 416 /* 417 * 'Independent' here refers to a clock which is not 418 * controlled by its parent. 419 */ 420 printk(KERN_ERR "clock: clk_disable called on independent " 421 "clock %s which has no enable_reg\n", clk->name); 422 return; 423 } 424 425 v = __raw_readl(clk->enable_reg); 426 if (clk->flags & INVERT_ENABLE) 427 v |= (1 << clk->enable_bit); 428 else 429 v &= ~(1 << clk->enable_bit); 430 __raw_writel(v, clk->enable_reg); 431 /* No OCP barrier needed here since it is a disable operation */ 432 } 433 434 const struct clkops clkops_omap2_dflt_wait = { 435 .enable = omap2_dflt_clk_enable, 436 .disable = omap2_dflt_clk_disable, 437 .find_companion = omap2_clk_dflt_find_companion, 438 .find_idlest = omap2_clk_dflt_find_idlest, 439 }; 440 441 const struct clkops clkops_omap2_dflt = { 442 .enable = omap2_dflt_clk_enable, 443 .disable = omap2_dflt_clk_disable, 444 }; 445 446 /* Enables clock without considering parent dependencies or use count 447 * REVISIT: Maybe change this to use clk->enable like on omap1? 448 */ 449 static int _omap2_clk_enable(struct clk *clk) 450 { 451 return clk->ops->enable(clk); 452 } 453 454 /* Disables clock without considering parent dependencies or use count */ 455 static void _omap2_clk_disable(struct clk *clk) 456 { 457 clk->ops->disable(clk); 458 } 459 460 void omap2_clk_disable(struct clk *clk) 461 { 462 if (clk->usecount > 0 && !(--clk->usecount)) { 463 _omap2_clk_disable(clk); 464 if (clk->parent) 465 omap2_clk_disable(clk->parent); 466 if (clk->clkdm) 467 omap2_clkdm_clk_disable(clk->clkdm, clk); 468 469 } 470 } 471 472 int omap2_clk_enable(struct clk *clk) 473 { 474 int ret = 0; 475 476 if (clk->usecount++ == 0) { 477 if (clk->clkdm) 478 omap2_clkdm_clk_enable(clk->clkdm, clk); 479 480 if (clk->parent) { 481 ret = omap2_clk_enable(clk->parent); 482 if (ret) 483 goto err; 484 } 485 486 ret = _omap2_clk_enable(clk); 487 if (ret) { 488 if (clk->parent) 489 omap2_clk_disable(clk->parent); 490 491 goto err; 492 } 493 } 494 return ret; 495 496 err: 497 if (clk->clkdm) 498 omap2_clkdm_clk_disable(clk->clkdm, clk); 499 clk->usecount--; 500 return ret; 501 } 502 503 /* 504 * Used for clocks that are part of CLKSEL_xyz governed clocks. 505 * REVISIT: Maybe change to use clk->enable() functions like on omap1? 506 */ 507 unsigned long omap2_clksel_recalc(struct clk *clk) 508 { 509 unsigned long rate; 510 u32 div = 0; 511 512 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name); 513 514 div = omap2_clksel_get_divisor(clk); 515 if (div == 0) 516 return clk->rate; 517 518 rate = clk->parent->rate / div; 519 520 pr_debug("clock: new clock rate is %ld (div %d)\n", rate, div); 521 522 return rate; 523 } 524 525 /** 526 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent 527 * @clk: OMAP struct clk ptr to inspect 528 * @src_clk: OMAP struct clk ptr of the parent clk to search for 529 * 530 * Scan the struct clksel array associated with the clock to find 531 * the element associated with the supplied parent clock address. 532 * Returns a pointer to the struct clksel on success or NULL on error. 533 */ 534 static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk, 535 struct clk *src_clk) 536 { 537 const struct clksel *clks; 538 539 if (!clk->clksel) 540 return NULL; 541 542 for (clks = clk->clksel; clks->parent; clks++) { 543 if (clks->parent == src_clk) 544 break; /* Found the requested parent */ 545 } 546 547 if (!clks->parent) { 548 printk(KERN_ERR "clock: Could not find parent clock %s in " 549 "clksel array of clock %s\n", src_clk->name, 550 clk->name); 551 return NULL; 552 } 553 554 return clks; 555 } 556 557 /** 558 * omap2_clksel_round_rate_div - find divisor for the given clock and rate 559 * @clk: OMAP struct clk to use 560 * @target_rate: desired clock rate 561 * @new_div: ptr to where we should store the divisor 562 * 563 * Finds 'best' divider value in an array based on the source and target 564 * rates. The divider array must be sorted with smallest divider first. 565 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, 566 * they are only settable as part of virtual_prcm set. 567 * 568 * Returns the rounded clock rate or returns 0xffffffff on error. 569 */ 570 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, 571 u32 *new_div) 572 { 573 unsigned long test_rate; 574 const struct clksel *clks; 575 const struct clksel_rate *clkr; 576 u32 last_div = 0; 577 578 pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n", 579 clk->name, target_rate); 580 581 *new_div = 1; 582 583 clks = omap2_get_clksel_by_parent(clk, clk->parent); 584 if (!clks) 585 return ~0; 586 587 for (clkr = clks->rates; clkr->div; clkr++) { 588 if (!(clkr->flags & cpu_mask)) 589 continue; 590 591 /* Sanity check */ 592 if (clkr->div <= last_div) 593 pr_err("clock: clksel_rate table not sorted " 594 "for clock %s", clk->name); 595 596 last_div = clkr->div; 597 598 test_rate = clk->parent->rate / clkr->div; 599 600 if (test_rate <= target_rate) 601 break; /* found it */ 602 } 603 604 if (!clkr->div) { 605 pr_err("clock: Could not find divisor for target " 606 "rate %ld for clock %s parent %s\n", target_rate, 607 clk->name, clk->parent->name); 608 return ~0; 609 } 610 611 *new_div = clkr->div; 612 613 pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div, 614 (clk->parent->rate / clkr->div)); 615 616 return (clk->parent->rate / clkr->div); 617 } 618 619 /** 620 * omap2_clksel_round_rate - find rounded rate for the given clock and rate 621 * @clk: OMAP struct clk to use 622 * @target_rate: desired clock rate 623 * 624 * Compatibility wrapper for OMAP clock framework 625 * Finds best target rate based on the source clock and possible dividers. 626 * rates. The divider array must be sorted with smallest divider first. 627 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, 628 * they are only settable as part of virtual_prcm set. 629 * 630 * Returns the rounded clock rate or returns 0xffffffff on error. 631 */ 632 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) 633 { 634 u32 new_div; 635 636 return omap2_clksel_round_rate_div(clk, target_rate, &new_div); 637 } 638 639 640 /* Given a clock and a rate apply a clock specific rounding function */ 641 long omap2_clk_round_rate(struct clk *clk, unsigned long rate) 642 { 643 if (clk->round_rate) 644 return clk->round_rate(clk, rate); 645 646 if (clk->flags & RATE_FIXED) 647 printk(KERN_ERR "clock: generic omap2_clk_round_rate called " 648 "on fixed-rate clock %s\n", clk->name); 649 650 return clk->rate; 651 } 652 653 /** 654 * omap2_clksel_to_divisor() - turn clksel field value into integer divider 655 * @clk: OMAP struct clk to use 656 * @field_val: register field value to find 657 * 658 * Given a struct clk of a rate-selectable clksel clock, and a register field 659 * value to search for, find the corresponding clock divisor. The register 660 * field value should be pre-masked and shifted down so the LSB is at bit 0 661 * before calling. Returns 0 on error 662 */ 663 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val) 664 { 665 const struct clksel *clks; 666 const struct clksel_rate *clkr; 667 668 clks = omap2_get_clksel_by_parent(clk, clk->parent); 669 if (!clks) 670 return 0; 671 672 for (clkr = clks->rates; clkr->div; clkr++) { 673 if ((clkr->flags & cpu_mask) && (clkr->val == field_val)) 674 break; 675 } 676 677 if (!clkr->div) { 678 printk(KERN_ERR "clock: Could not find fieldval %d for " 679 "clock %s parent %s\n", field_val, clk->name, 680 clk->parent->name); 681 return 0; 682 } 683 684 return clkr->div; 685 } 686 687 /** 688 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value 689 * @clk: OMAP struct clk to use 690 * @div: integer divisor to search for 691 * 692 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor, 693 * find the corresponding register field value. The return register value is 694 * the value before left-shifting. Returns ~0 on error 695 */ 696 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div) 697 { 698 const struct clksel *clks; 699 const struct clksel_rate *clkr; 700 701 /* should never happen */ 702 WARN_ON(div == 0); 703 704 clks = omap2_get_clksel_by_parent(clk, clk->parent); 705 if (!clks) 706 return ~0; 707 708 for (clkr = clks->rates; clkr->div; clkr++) { 709 if ((clkr->flags & cpu_mask) && (clkr->div == div)) 710 break; 711 } 712 713 if (!clkr->div) { 714 printk(KERN_ERR "clock: Could not find divisor %d for " 715 "clock %s parent %s\n", div, clk->name, 716 clk->parent->name); 717 return ~0; 718 } 719 720 return clkr->val; 721 } 722 723 /** 724 * omap2_clksel_get_divisor - get current divider applied to parent clock. 725 * @clk: OMAP struct clk to use. 726 * 727 * Returns the integer divisor upon success or 0 on error. 728 */ 729 u32 omap2_clksel_get_divisor(struct clk *clk) 730 { 731 u32 v; 732 733 if (!clk->clksel_mask) 734 return 0; 735 736 v = __raw_readl(clk->clksel_reg) & clk->clksel_mask; 737 v >>= __ffs(clk->clksel_mask); 738 739 return omap2_clksel_to_divisor(clk, v); 740 } 741 742 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) 743 { 744 u32 v, field_val, validrate, new_div = 0; 745 746 if (!clk->clksel_mask) 747 return -EINVAL; 748 749 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); 750 if (validrate != rate) 751 return -EINVAL; 752 753 field_val = omap2_divisor_to_clksel(clk, new_div); 754 if (field_val == ~0) 755 return -EINVAL; 756 757 v = __raw_readl(clk->clksel_reg); 758 v &= ~clk->clksel_mask; 759 v |= field_val << __ffs(clk->clksel_mask); 760 __raw_writel(v, clk->clksel_reg); 761 v = __raw_readl(clk->clksel_reg); /* OCP barrier */ 762 763 clk->rate = clk->parent->rate / new_div; 764 765 _omap2xxx_clk_commit(clk); 766 767 return 0; 768 } 769 770 771 /* Set the clock rate for a clock source */ 772 int omap2_clk_set_rate(struct clk *clk, unsigned long rate) 773 { 774 int ret = -EINVAL; 775 776 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate); 777 778 /* CONFIG_PARTICIPANT clocks are changed only in sets via the 779 rate table mechanism, driven by mpu_speed */ 780 if (clk->flags & CONFIG_PARTICIPANT) 781 return -EINVAL; 782 783 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ 784 if (clk->set_rate) 785 ret = clk->set_rate(clk, rate); 786 787 return ret; 788 } 789 790 /* 791 * Converts encoded control register address into a full address 792 * On error, the return value (parent_div) will be 0. 793 */ 794 static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk, 795 u32 *field_val) 796 { 797 const struct clksel *clks; 798 const struct clksel_rate *clkr; 799 800 clks = omap2_get_clksel_by_parent(clk, src_clk); 801 if (!clks) 802 return 0; 803 804 for (clkr = clks->rates; clkr->div; clkr++) { 805 if (clkr->flags & cpu_mask && clkr->flags & DEFAULT_RATE) 806 break; /* Found the default rate for this platform */ 807 } 808 809 if (!clkr->div) { 810 printk(KERN_ERR "clock: Could not find default rate for " 811 "clock %s parent %s\n", clk->name, 812 src_clk->parent->name); 813 return 0; 814 } 815 816 /* Should never happen. Add a clksel mask to the struct clk. */ 817 WARN_ON(clk->clksel_mask == 0); 818 819 *field_val = clkr->val; 820 821 return clkr->div; 822 } 823 824 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) 825 { 826 u32 field_val, v, parent_div; 827 828 if (clk->flags & CONFIG_PARTICIPANT) 829 return -EINVAL; 830 831 if (!clk->clksel) 832 return -EINVAL; 833 834 parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val); 835 if (!parent_div) 836 return -EINVAL; 837 838 /* Set new source value (previous dividers if any in effect) */ 839 v = __raw_readl(clk->clksel_reg); 840 v &= ~clk->clksel_mask; 841 v |= field_val << __ffs(clk->clksel_mask); 842 __raw_writel(v, clk->clksel_reg); 843 v = __raw_readl(clk->clksel_reg); /* OCP barrier */ 844 845 _omap2xxx_clk_commit(clk); 846 847 clk_reparent(clk, new_parent); 848 849 /* CLKSEL clocks follow their parents' rates, divided by a divisor */ 850 clk->rate = new_parent->rate; 851 852 if (parent_div > 0) 853 clk->rate /= parent_div; 854 855 pr_debug("clock: set parent of %s to %s (new rate %ld)\n", 856 clk->name, clk->parent->name, clk->rate); 857 858 return 0; 859 } 860 861 /* DPLL rate rounding code */ 862 863 /** 864 * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding 865 * @clk: struct clk * of the DPLL 866 * @tolerance: maximum rate error tolerance 867 * 868 * Set the maximum DPLL rate error tolerance for the rate rounding 869 * algorithm. The rate tolerance is an attempt to balance DPLL power 870 * saving (the least divider value "n") vs. rate fidelity (the least 871 * difference between the desired DPLL target rate and the rounded 872 * rate out of the algorithm). So, increasing the tolerance is likely 873 * to decrease DPLL power consumption and increase DPLL rate error. 874 * Returns -EINVAL if provided a null clock ptr or a clk that is not a 875 * DPLL; or 0 upon success. 876 */ 877 int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance) 878 { 879 if (!clk || !clk->dpll_data) 880 return -EINVAL; 881 882 clk->dpll_data->rate_tolerance = tolerance; 883 884 return 0; 885 } 886 887 static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, 888 unsigned int m, unsigned int n) 889 { 890 unsigned long long num; 891 892 num = (unsigned long long)parent_rate * m; 893 do_div(num, n); 894 return num; 895 } 896 897 /* 898 * _dpll_test_mult - test a DPLL multiplier value 899 * @m: pointer to the DPLL m (multiplier) value under test 900 * @n: current DPLL n (divider) value under test 901 * @new_rate: pointer to storage for the resulting rounded rate 902 * @target_rate: the desired DPLL rate 903 * @parent_rate: the DPLL's parent clock rate 904 * 905 * This code tests a DPLL multiplier value, ensuring that the 906 * resulting rate will not be higher than the target_rate, and that 907 * the multiplier value itself is valid for the DPLL. Initially, the 908 * integer pointed to by the m argument should be prescaled by 909 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with 910 * a non-scaled m upon return. This non-scaled m will result in a 911 * new_rate as close as possible to target_rate (but not greater than 912 * target_rate) given the current (parent_rate, n, prescaled m) 913 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the 914 * non-scaled m attempted to underflow, which can allow the calling 915 * function to bail out early; or 0 upon success. 916 */ 917 static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, 918 unsigned long target_rate, 919 unsigned long parent_rate) 920 { 921 int r = 0, carry = 0; 922 923 /* Unscale m and round if necessary */ 924 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL) 925 carry = 1; 926 *m = (*m / DPLL_SCALE_FACTOR) + carry; 927 928 /* 929 * The new rate must be <= the target rate to avoid programming 930 * a rate that is impossible for the hardware to handle 931 */ 932 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); 933 if (*new_rate > target_rate) { 934 (*m)--; 935 *new_rate = 0; 936 } 937 938 /* Guard against m underflow */ 939 if (*m < DPLL_MIN_MULTIPLIER) { 940 *m = DPLL_MIN_MULTIPLIER; 941 *new_rate = 0; 942 r = DPLL_MULT_UNDERFLOW; 943 } 944 945 if (*new_rate == 0) 946 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); 947 948 return r; 949 } 950 951 /** 952 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL 953 * @clk: struct clk * for a DPLL 954 * @target_rate: desired DPLL clock rate 955 * 956 * Given a DPLL, a desired target rate, and a rate tolerance, round 957 * the target rate to a possible, programmable rate for this DPLL. 958 * Rate tolerance is assumed to be set by the caller before this 959 * function is called. Attempts to select the minimum possible n 960 * within the tolerance to reduce power consumption. Stores the 961 * computed (m, n) in the DPLL's dpll_data structure so set_rate() 962 * will not need to call this (expensive) function again. Returns ~0 963 * if the target rate cannot be rounded, either because the rate is 964 * too low or because the rate tolerance is set too tightly; or the 965 * rounded rate upon success. 966 */ 967 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) 968 { 969 int m, n, r, e, scaled_max_m; 970 unsigned long scaled_rt_rp, new_rate; 971 int min_e = -1, min_e_m = -1, min_e_n = -1; 972 struct dpll_data *dd; 973 974 if (!clk || !clk->dpll_data) 975 return ~0; 976 977 dd = clk->dpll_data; 978 979 pr_debug("clock: starting DPLL round_rate for clock %s, target rate " 980 "%ld\n", clk->name, target_rate); 981 982 scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR); 983 scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR; 984 985 dd->last_rounded_rate = 0; 986 987 for (n = dd->min_divider; n <= dd->max_divider; n++) { 988 989 /* Is the (input clk, divider) pair valid for the DPLL? */ 990 r = _dpll_test_fint(clk, n); 991 if (r == DPLL_FINT_UNDERFLOW) 992 break; 993 else if (r == DPLL_FINT_INVALID) 994 continue; 995 996 /* Compute the scaled DPLL multiplier, based on the divider */ 997 m = scaled_rt_rp * n; 998 999 /* 1000 * Since we're counting n up, a m overflow means we 1001 * can bail out completely (since as n increases in 1002 * the next iteration, there's no way that m can 1003 * increase beyond the current m) 1004 */ 1005 if (m > scaled_max_m) 1006 break; 1007 1008 r = _dpll_test_mult(&m, n, &new_rate, target_rate, 1009 dd->clk_ref->rate); 1010 1011 /* m can't be set low enough for this n - try with a larger n */ 1012 if (r == DPLL_MULT_UNDERFLOW) 1013 continue; 1014 1015 e = target_rate - new_rate; 1016 pr_debug("clock: n = %d: m = %d: rate error is %d " 1017 "(new_rate = %ld)\n", n, m, e, new_rate); 1018 1019 if (min_e == -1 || 1020 min_e >= (int)(abs(e) - dd->rate_tolerance)) { 1021 min_e = e; 1022 min_e_m = m; 1023 min_e_n = n; 1024 1025 pr_debug("clock: found new least error %d\n", min_e); 1026 1027 /* We found good settings -- bail out now */ 1028 if (min_e <= dd->rate_tolerance) 1029 break; 1030 } 1031 } 1032 1033 if (min_e < 0) { 1034 pr_debug("clock: error: target rate or tolerance too low\n"); 1035 return ~0; 1036 } 1037 1038 dd->last_rounded_m = min_e_m; 1039 dd->last_rounded_n = min_e_n; 1040 dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate, 1041 min_e_m, min_e_n); 1042 1043 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n", 1044 min_e, min_e_m, min_e_n); 1045 pr_debug("clock: final rate: %ld (target rate: %ld)\n", 1046 dd->last_rounded_rate, target_rate); 1047 1048 return dd->last_rounded_rate; 1049 } 1050 1051 /*------------------------------------------------------------------------- 1052 * Omap2 clock reset and init functions 1053 *-------------------------------------------------------------------------*/ 1054 1055 #ifdef CONFIG_OMAP_RESET_CLOCKS 1056 void omap2_clk_disable_unused(struct clk *clk) 1057 { 1058 u32 regval32, v; 1059 1060 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0; 1061 1062 regval32 = __raw_readl(clk->enable_reg); 1063 if ((regval32 & (1 << clk->enable_bit)) == v) 1064 return; 1065 1066 printk(KERN_DEBUG "Disabling unused clock \"%s\"\n", clk->name); 1067 if (cpu_is_omap34xx()) { 1068 omap2_clk_enable(clk); 1069 omap2_clk_disable(clk); 1070 } else 1071 _omap2_clk_disable(clk); 1072 if (clk->clkdm != NULL) 1073 pwrdm_clkdm_state_switch(clk->clkdm); 1074 } 1075 #endif 1076