1 /* 2 * linux/arch/arm/mach-omap2/clock.c 3 * 4 * Copyright (C) 2005-2008 Texas Instruments, Inc. 5 * Copyright (C) 2004-2008 Nokia Corporation 6 * 7 * Contacts: 8 * Richard Woodruff <r-woodruff2@ti.com> 9 * Paul Walmsley 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 #undef DEBUG 16 17 #include <linux/module.h> 18 #include <linux/kernel.h> 19 #include <linux/device.h> 20 #include <linux/list.h> 21 #include <linux/errno.h> 22 #include <linux/delay.h> 23 #include <linux/clk.h> 24 #include <linux/io.h> 25 #include <linux/bitops.h> 26 27 #include <mach/clock.h> 28 #include <mach/clockdomain.h> 29 #include <mach/sram.h> 30 #include <mach/cpu.h> 31 #include <asm/div64.h> 32 33 #include "memory.h" 34 #include "sdrc.h" 35 #include "clock.h" 36 #include "prm.h" 37 #include "prm-regbits-24xx.h" 38 #include "cm.h" 39 #include "cm-regbits-24xx.h" 40 #include "cm-regbits-34xx.h" 41 42 #define MAX_CLOCK_ENABLE_WAIT 100000 43 44 /* DPLL rate rounding: minimum DPLL multiplier, divider values */ 45 #define DPLL_MIN_MULTIPLIER 1 46 #define DPLL_MIN_DIVIDER 1 47 48 /* Possible error results from _dpll_test_mult */ 49 #define DPLL_MULT_UNDERFLOW (1 << 0) 50 51 /* 52 * Scale factor to mitigate roundoff errors in DPLL rate rounding. 53 * The higher the scale factor, the greater the risk of arithmetic overflow, 54 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR 55 * must be a power of DPLL_SCALE_BASE. 56 */ 57 #define DPLL_SCALE_FACTOR 64 58 #define DPLL_SCALE_BASE 2 59 #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \ 60 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE)) 61 62 u8 cpu_mask; 63 64 /*------------------------------------------------------------------------- 65 * OMAP2/3 specific clock functions 66 *-------------------------------------------------------------------------*/ 67 68 /** 69 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk 70 * @clk: OMAP clock struct ptr to use 71 * 72 * Convert a clockdomain name stored in a struct clk 'clk' into a 73 * clockdomain pointer, and save it into the struct clk. Intended to be 74 * called during clk_register(). No return value. 75 */ 76 void omap2_init_clk_clkdm(struct clk *clk) 77 { 78 struct clockdomain *clkdm; 79 80 if (!clk->clkdm_name) 81 return; 82 83 clkdm = clkdm_lookup(clk->clkdm_name); 84 if (clkdm) { 85 pr_debug("clock: associated clk %s to clkdm %s\n", 86 clk->name, clk->clkdm_name); 87 clk->clkdm = clkdm; 88 } else { 89 pr_debug("clock: could not associate clk %s to " 90 "clkdm %s\n", clk->name, clk->clkdm_name); 91 } 92 } 93 94 /** 95 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware 96 * @clk: OMAP clock struct ptr to use 97 * 98 * Given a pointer to a source-selectable struct clk, read the hardware 99 * register and determine what its parent is currently set to. Update the 100 * clk->parent field with the appropriate clk ptr. 101 */ 102 void omap2_init_clksel_parent(struct clk *clk) 103 { 104 const struct clksel *clks; 105 const struct clksel_rate *clkr; 106 u32 r, found = 0; 107 108 if (!clk->clksel) 109 return; 110 111 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; 112 r >>= __ffs(clk->clksel_mask); 113 114 for (clks = clk->clksel; clks->parent && !found; clks++) { 115 for (clkr = clks->rates; clkr->div && !found; clkr++) { 116 if ((clkr->flags & cpu_mask) && (clkr->val == r)) { 117 if (clk->parent != clks->parent) { 118 pr_debug("clock: inited %s parent " 119 "to %s (was %s)\n", 120 clk->name, clks->parent->name, 121 ((clk->parent) ? 122 clk->parent->name : "NULL")); 123 clk->parent = clks->parent; 124 }; 125 found = 1; 126 } 127 } 128 } 129 130 if (!found) 131 printk(KERN_ERR "clock: init parent: could not find " 132 "regval %0x for clock %s\n", r, clk->name); 133 134 return; 135 } 136 137 /* Returns the DPLL rate */ 138 u32 omap2_get_dpll_rate(struct clk *clk) 139 { 140 long long dpll_clk; 141 u32 dpll_mult, dpll_div, dpll; 142 struct dpll_data *dd; 143 144 dd = clk->dpll_data; 145 /* REVISIT: What do we return on error? */ 146 if (!dd) 147 return 0; 148 149 dpll = __raw_readl(dd->mult_div1_reg); 150 dpll_mult = dpll & dd->mult_mask; 151 dpll_mult >>= __ffs(dd->mult_mask); 152 dpll_div = dpll & dd->div1_mask; 153 dpll_div >>= __ffs(dd->div1_mask); 154 155 dpll_clk = (long long)clk->parent->rate * dpll_mult; 156 do_div(dpll_clk, dpll_div + 1); 157 158 return dpll_clk; 159 } 160 161 /* 162 * Used for clocks that have the same value as the parent clock, 163 * divided by some factor 164 */ 165 void omap2_fixed_divisor_recalc(struct clk *clk) 166 { 167 WARN_ON(!clk->fixed_div); 168 169 clk->rate = clk->parent->rate / clk->fixed_div; 170 171 if (clk->flags & RATE_PROPAGATES) 172 propagate_rate(clk); 173 } 174 175 /** 176 * omap2_wait_clock_ready - wait for clock to enable 177 * @reg: physical address of clock IDLEST register 178 * @mask: value to mask against to determine if the clock is active 179 * @name: name of the clock (for printk) 180 * 181 * Returns 1 if the clock enabled in time, or 0 if it failed to enable 182 * in roughly MAX_CLOCK_ENABLE_WAIT microseconds. 183 */ 184 int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name) 185 { 186 int i = 0; 187 int ena = 0; 188 189 /* 190 * 24xx uses 0 to indicate not ready, and 1 to indicate ready. 191 * 34xx reverses this, just to keep us on our toes 192 */ 193 if (cpu_mask & (RATE_IN_242X | RATE_IN_243X)) { 194 ena = mask; 195 } else if (cpu_mask & RATE_IN_343X) { 196 ena = 0; 197 } 198 199 /* Wait for lock */ 200 while (((__raw_readl(reg) & mask) != ena) && 201 (i++ < MAX_CLOCK_ENABLE_WAIT)) { 202 udelay(1); 203 } 204 205 if (i < MAX_CLOCK_ENABLE_WAIT) 206 pr_debug("Clock %s stable after %d loops\n", name, i); 207 else 208 printk(KERN_ERR "Clock %s didn't enable in %d tries\n", 209 name, MAX_CLOCK_ENABLE_WAIT); 210 211 212 return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0; 213 }; 214 215 216 /* 217 * Note: We don't need special code here for INVERT_ENABLE 218 * for the time being since INVERT_ENABLE only applies to clocks enabled by 219 * CM_CLKEN_PLL 220 */ 221 static void omap2_clk_wait_ready(struct clk *clk) 222 { 223 void __iomem *reg, *other_reg, *st_reg; 224 u32 bit; 225 226 /* 227 * REVISIT: This code is pretty ugly. It would be nice to generalize 228 * it and pull it into struct clk itself somehow. 229 */ 230 reg = clk->enable_reg; 231 if ((((u32)reg & 0xff) >= CM_FCLKEN1) && 232 (((u32)reg & 0xff) <= OMAP24XX_CM_FCLKEN2)) 233 other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x10); /* CM_ICLKEN* */ 234 else if ((((u32)reg & 0xff) >= CM_ICLKEN1) && 235 (((u32)reg & 0xff) <= OMAP24XX_CM_ICLKEN4)) 236 other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x00); /* CM_FCLKEN* */ 237 else 238 return; 239 240 /* Check if both functional and interface clocks 241 * are running. */ 242 bit = 1 << clk->enable_bit; 243 if (!(__raw_readl(other_reg) & bit)) 244 return; 245 st_reg = (void __iomem *)(((u32)other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */ 246 247 omap2_wait_clock_ready(st_reg, bit, clk->name); 248 } 249 250 static int omap2_dflt_clk_enable(struct clk *clk) 251 { 252 u32 regval32; 253 254 if (unlikely(clk->enable_reg == NULL)) { 255 printk(KERN_ERR "clock.c: Enable for %s without enable code\n", 256 clk->name); 257 return 0; /* REVISIT: -EINVAL */ 258 } 259 260 regval32 = __raw_readl(clk->enable_reg); 261 if (clk->flags & INVERT_ENABLE) 262 regval32 &= ~(1 << clk->enable_bit); 263 else 264 regval32 |= (1 << clk->enable_bit); 265 __raw_writel(regval32, clk->enable_reg); 266 wmb(); 267 268 return 0; 269 } 270 271 static int omap2_dflt_clk_enable_wait(struct clk *clk) 272 { 273 int ret; 274 275 if (unlikely(clk->enable_reg == NULL)) { 276 printk(KERN_ERR "clock.c: Enable for %s without enable code\n", 277 clk->name); 278 return 0; /* REVISIT: -EINVAL */ 279 } 280 281 ret = omap2_dflt_clk_enable(clk); 282 if (ret == 0) 283 omap2_clk_wait_ready(clk); 284 return ret; 285 } 286 287 static void omap2_dflt_clk_disable(struct clk *clk) 288 { 289 u32 regval32; 290 291 if (clk->enable_reg == NULL) { 292 /* 293 * 'Independent' here refers to a clock which is not 294 * controlled by its parent. 295 */ 296 printk(KERN_ERR "clock: clk_disable called on independent " 297 "clock %s which has no enable_reg\n", clk->name); 298 return; 299 } 300 301 regval32 = __raw_readl(clk->enable_reg); 302 if (clk->flags & INVERT_ENABLE) 303 regval32 |= (1 << clk->enable_bit); 304 else 305 regval32 &= ~(1 << clk->enable_bit); 306 __raw_writel(regval32, clk->enable_reg); 307 wmb(); 308 } 309 310 const struct clkops clkops_omap2_dflt_wait = { 311 .enable = omap2_dflt_clk_enable_wait, 312 .disable = omap2_dflt_clk_disable, 313 }; 314 315 const struct clkops clkops_omap2_dflt = { 316 .enable = omap2_dflt_clk_enable, 317 .disable = omap2_dflt_clk_disable, 318 }; 319 320 /* Enables clock without considering parent dependencies or use count 321 * REVISIT: Maybe change this to use clk->enable like on omap1? 322 */ 323 static int _omap2_clk_enable(struct clk *clk) 324 { 325 return clk->ops->enable(clk); 326 } 327 328 /* Disables clock without considering parent dependencies or use count */ 329 static void _omap2_clk_disable(struct clk *clk) 330 { 331 clk->ops->disable(clk); 332 } 333 334 void omap2_clk_disable(struct clk *clk) 335 { 336 if (clk->usecount > 0 && !(--clk->usecount)) { 337 _omap2_clk_disable(clk); 338 if (likely((u32)clk->parent)) 339 omap2_clk_disable(clk->parent); 340 if (clk->clkdm) 341 omap2_clkdm_clk_disable(clk->clkdm, clk); 342 343 } 344 } 345 346 int omap2_clk_enable(struct clk *clk) 347 { 348 int ret = 0; 349 350 if (clk->usecount++ == 0) { 351 if (likely((u32)clk->parent)) 352 ret = omap2_clk_enable(clk->parent); 353 354 if (unlikely(ret != 0)) { 355 clk->usecount--; 356 return ret; 357 } 358 359 if (clk->clkdm) 360 omap2_clkdm_clk_enable(clk->clkdm, clk); 361 362 ret = _omap2_clk_enable(clk); 363 364 if (unlikely(ret != 0)) { 365 if (clk->clkdm) 366 omap2_clkdm_clk_disable(clk->clkdm, clk); 367 368 if (clk->parent) { 369 omap2_clk_disable(clk->parent); 370 clk->usecount--; 371 } 372 } 373 } 374 375 return ret; 376 } 377 378 /* 379 * Used for clocks that are part of CLKSEL_xyz governed clocks. 380 * REVISIT: Maybe change to use clk->enable() functions like on omap1? 381 */ 382 void omap2_clksel_recalc(struct clk *clk) 383 { 384 u32 div = 0; 385 386 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name); 387 388 div = omap2_clksel_get_divisor(clk); 389 if (div == 0) 390 return; 391 392 if (unlikely(clk->rate == clk->parent->rate / div)) 393 return; 394 clk->rate = clk->parent->rate / div; 395 396 pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div); 397 398 if (unlikely(clk->flags & RATE_PROPAGATES)) 399 propagate_rate(clk); 400 } 401 402 /** 403 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent 404 * @clk: OMAP struct clk ptr to inspect 405 * @src_clk: OMAP struct clk ptr of the parent clk to search for 406 * 407 * Scan the struct clksel array associated with the clock to find 408 * the element associated with the supplied parent clock address. 409 * Returns a pointer to the struct clksel on success or NULL on error. 410 */ 411 const struct clksel *omap2_get_clksel_by_parent(struct clk *clk, 412 struct clk *src_clk) 413 { 414 const struct clksel *clks; 415 416 if (!clk->clksel) 417 return NULL; 418 419 for (clks = clk->clksel; clks->parent; clks++) { 420 if (clks->parent == src_clk) 421 break; /* Found the requested parent */ 422 } 423 424 if (!clks->parent) { 425 printk(KERN_ERR "clock: Could not find parent clock %s in " 426 "clksel array of clock %s\n", src_clk->name, 427 clk->name); 428 return NULL; 429 } 430 431 return clks; 432 } 433 434 /** 435 * omap2_clksel_round_rate_div - find divisor for the given clock and rate 436 * @clk: OMAP struct clk to use 437 * @target_rate: desired clock rate 438 * @new_div: ptr to where we should store the divisor 439 * 440 * Finds 'best' divider value in an array based on the source and target 441 * rates. The divider array must be sorted with smallest divider first. 442 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, 443 * they are only settable as part of virtual_prcm set. 444 * 445 * Returns the rounded clock rate or returns 0xffffffff on error. 446 */ 447 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, 448 u32 *new_div) 449 { 450 unsigned long test_rate; 451 const struct clksel *clks; 452 const struct clksel_rate *clkr; 453 u32 last_div = 0; 454 455 printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n", 456 clk->name, target_rate); 457 458 *new_div = 1; 459 460 clks = omap2_get_clksel_by_parent(clk, clk->parent); 461 if (clks == NULL) 462 return ~0; 463 464 for (clkr = clks->rates; clkr->div; clkr++) { 465 if (!(clkr->flags & cpu_mask)) 466 continue; 467 468 /* Sanity check */ 469 if (clkr->div <= last_div) 470 printk(KERN_ERR "clock: clksel_rate table not sorted " 471 "for clock %s", clk->name); 472 473 last_div = clkr->div; 474 475 test_rate = clk->parent->rate / clkr->div; 476 477 if (test_rate <= target_rate) 478 break; /* found it */ 479 } 480 481 if (!clkr->div) { 482 printk(KERN_ERR "clock: Could not find divisor for target " 483 "rate %ld for clock %s parent %s\n", target_rate, 484 clk->name, clk->parent->name); 485 return ~0; 486 } 487 488 *new_div = clkr->div; 489 490 printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div, 491 (clk->parent->rate / clkr->div)); 492 493 return (clk->parent->rate / clkr->div); 494 } 495 496 /** 497 * omap2_clksel_round_rate - find rounded rate for the given clock and rate 498 * @clk: OMAP struct clk to use 499 * @target_rate: desired clock rate 500 * 501 * Compatibility wrapper for OMAP clock framework 502 * Finds best target rate based on the source clock and possible dividers. 503 * rates. The divider array must be sorted with smallest divider first. 504 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, 505 * they are only settable as part of virtual_prcm set. 506 * 507 * Returns the rounded clock rate or returns 0xffffffff on error. 508 */ 509 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) 510 { 511 u32 new_div; 512 513 return omap2_clksel_round_rate_div(clk, target_rate, &new_div); 514 } 515 516 517 /* Given a clock and a rate apply a clock specific rounding function */ 518 long omap2_clk_round_rate(struct clk *clk, unsigned long rate) 519 { 520 if (clk->round_rate != NULL) 521 return clk->round_rate(clk, rate); 522 523 if (clk->flags & RATE_FIXED) 524 printk(KERN_ERR "clock: generic omap2_clk_round_rate called " 525 "on fixed-rate clock %s\n", clk->name); 526 527 return clk->rate; 528 } 529 530 /** 531 * omap2_clksel_to_divisor() - turn clksel field value into integer divider 532 * @clk: OMAP struct clk to use 533 * @field_val: register field value to find 534 * 535 * Given a struct clk of a rate-selectable clksel clock, and a register field 536 * value to search for, find the corresponding clock divisor. The register 537 * field value should be pre-masked and shifted down so the LSB is at bit 0 538 * before calling. Returns 0 on error 539 */ 540 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val) 541 { 542 const struct clksel *clks; 543 const struct clksel_rate *clkr; 544 545 clks = omap2_get_clksel_by_parent(clk, clk->parent); 546 if (clks == NULL) 547 return 0; 548 549 for (clkr = clks->rates; clkr->div; clkr++) { 550 if ((clkr->flags & cpu_mask) && (clkr->val == field_val)) 551 break; 552 } 553 554 if (!clkr->div) { 555 printk(KERN_ERR "clock: Could not find fieldval %d for " 556 "clock %s parent %s\n", field_val, clk->name, 557 clk->parent->name); 558 return 0; 559 } 560 561 return clkr->div; 562 } 563 564 /** 565 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value 566 * @clk: OMAP struct clk to use 567 * @div: integer divisor to search for 568 * 569 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor, 570 * find the corresponding register field value. The return register value is 571 * the value before left-shifting. Returns 0xffffffff on error 572 */ 573 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div) 574 { 575 const struct clksel *clks; 576 const struct clksel_rate *clkr; 577 578 /* should never happen */ 579 WARN_ON(div == 0); 580 581 clks = omap2_get_clksel_by_parent(clk, clk->parent); 582 if (clks == NULL) 583 return 0; 584 585 for (clkr = clks->rates; clkr->div; clkr++) { 586 if ((clkr->flags & cpu_mask) && (clkr->div == div)) 587 break; 588 } 589 590 if (!clkr->div) { 591 printk(KERN_ERR "clock: Could not find divisor %d for " 592 "clock %s parent %s\n", div, clk->name, 593 clk->parent->name); 594 return 0; 595 } 596 597 return clkr->val; 598 } 599 600 /** 601 * omap2_get_clksel - find clksel register addr & field mask for a clk 602 * @clk: struct clk to use 603 * @field_mask: ptr to u32 to store the register field mask 604 * 605 * Returns the address of the clksel register upon success or NULL on error. 606 */ 607 void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask) 608 { 609 if (unlikely((clk->clksel_reg == NULL) || (clk->clksel_mask == NULL))) 610 return NULL; 611 612 *field_mask = clk->clksel_mask; 613 614 return clk->clksel_reg; 615 } 616 617 /** 618 * omap2_clksel_get_divisor - get current divider applied to parent clock. 619 * @clk: OMAP struct clk to use. 620 * 621 * Returns the integer divisor upon success or 0 on error. 622 */ 623 u32 omap2_clksel_get_divisor(struct clk *clk) 624 { 625 u32 field_mask, field_val; 626 void __iomem *div_addr; 627 628 div_addr = omap2_get_clksel(clk, &field_mask); 629 if (div_addr == NULL) 630 return 0; 631 632 field_val = __raw_readl(div_addr) & field_mask; 633 field_val >>= __ffs(field_mask); 634 635 return omap2_clksel_to_divisor(clk, field_val); 636 } 637 638 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) 639 { 640 u32 field_mask, field_val, reg_val, validrate, new_div = 0; 641 void __iomem *div_addr; 642 643 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); 644 if (validrate != rate) 645 return -EINVAL; 646 647 div_addr = omap2_get_clksel(clk, &field_mask); 648 if (div_addr == NULL) 649 return -EINVAL; 650 651 field_val = omap2_divisor_to_clksel(clk, new_div); 652 if (field_val == ~0) 653 return -EINVAL; 654 655 reg_val = __raw_readl(div_addr); 656 reg_val &= ~field_mask; 657 reg_val |= (field_val << __ffs(field_mask)); 658 __raw_writel(reg_val, div_addr); 659 wmb(); 660 661 clk->rate = clk->parent->rate / new_div; 662 663 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) { 664 prm_write_mod_reg(OMAP24XX_VALID_CONFIG, 665 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET); 666 wmb(); 667 } 668 669 return 0; 670 } 671 672 673 /* Set the clock rate for a clock source */ 674 int omap2_clk_set_rate(struct clk *clk, unsigned long rate) 675 { 676 int ret = -EINVAL; 677 678 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate); 679 680 /* CONFIG_PARTICIPANT clocks are changed only in sets via the 681 rate table mechanism, driven by mpu_speed */ 682 if (clk->flags & CONFIG_PARTICIPANT) 683 return -EINVAL; 684 685 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ 686 if (clk->set_rate != NULL) 687 ret = clk->set_rate(clk, rate); 688 689 if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES))) 690 propagate_rate(clk); 691 692 return ret; 693 } 694 695 /* 696 * Converts encoded control register address into a full address 697 * On error, *src_addr will be returned as 0. 698 */ 699 static u32 omap2_clksel_get_src_field(void __iomem **src_addr, 700 struct clk *src_clk, u32 *field_mask, 701 struct clk *clk, u32 *parent_div) 702 { 703 const struct clksel *clks; 704 const struct clksel_rate *clkr; 705 706 *parent_div = 0; 707 *src_addr = NULL; 708 709 clks = omap2_get_clksel_by_parent(clk, src_clk); 710 if (clks == NULL) 711 return 0; 712 713 for (clkr = clks->rates; clkr->div; clkr++) { 714 if (clkr->flags & (cpu_mask | DEFAULT_RATE)) 715 break; /* Found the default rate for this platform */ 716 } 717 718 if (!clkr->div) { 719 printk(KERN_ERR "clock: Could not find default rate for " 720 "clock %s parent %s\n", clk->name, 721 src_clk->parent->name); 722 return 0; 723 } 724 725 /* Should never happen. Add a clksel mask to the struct clk. */ 726 WARN_ON(clk->clksel_mask == 0); 727 728 *field_mask = clk->clksel_mask; 729 *src_addr = clk->clksel_reg; 730 *parent_div = clkr->div; 731 732 return clkr->val; 733 } 734 735 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) 736 { 737 void __iomem *src_addr; 738 u32 field_val, field_mask, reg_val, parent_div; 739 740 if (unlikely(clk->flags & CONFIG_PARTICIPANT)) 741 return -EINVAL; 742 743 if (!clk->clksel) 744 return -EINVAL; 745 746 field_val = omap2_clksel_get_src_field(&src_addr, new_parent, 747 &field_mask, clk, &parent_div); 748 if (src_addr == NULL) 749 return -EINVAL; 750 751 if (clk->usecount > 0) 752 _omap2_clk_disable(clk); 753 754 /* Set new source value (previous dividers if any in effect) */ 755 reg_val = __raw_readl(src_addr) & ~field_mask; 756 reg_val |= (field_val << __ffs(field_mask)); 757 __raw_writel(reg_val, src_addr); 758 wmb(); 759 760 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) { 761 __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL); 762 wmb(); 763 } 764 765 if (clk->usecount > 0) 766 _omap2_clk_enable(clk); 767 768 clk->parent = new_parent; 769 770 /* CLKSEL clocks follow their parents' rates, divided by a divisor */ 771 clk->rate = new_parent->rate; 772 773 if (parent_div > 0) 774 clk->rate /= parent_div; 775 776 pr_debug("clock: set parent of %s to %s (new rate %ld)\n", 777 clk->name, clk->parent->name, clk->rate); 778 779 if (unlikely(clk->flags & RATE_PROPAGATES)) 780 propagate_rate(clk); 781 782 return 0; 783 } 784 785 /* DPLL rate rounding code */ 786 787 /** 788 * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding 789 * @clk: struct clk * of the DPLL 790 * @tolerance: maximum rate error tolerance 791 * 792 * Set the maximum DPLL rate error tolerance for the rate rounding 793 * algorithm. The rate tolerance is an attempt to balance DPLL power 794 * saving (the least divider value "n") vs. rate fidelity (the least 795 * difference between the desired DPLL target rate and the rounded 796 * rate out of the algorithm). So, increasing the tolerance is likely 797 * to decrease DPLL power consumption and increase DPLL rate error. 798 * Returns -EINVAL if provided a null clock ptr or a clk that is not a 799 * DPLL; or 0 upon success. 800 */ 801 int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance) 802 { 803 if (!clk || !clk->dpll_data) 804 return -EINVAL; 805 806 clk->dpll_data->rate_tolerance = tolerance; 807 808 return 0; 809 } 810 811 static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, unsigned int m, unsigned int n) 812 { 813 unsigned long long num; 814 815 num = (unsigned long long)parent_rate * m; 816 do_div(num, n); 817 return num; 818 } 819 820 /* 821 * _dpll_test_mult - test a DPLL multiplier value 822 * @m: pointer to the DPLL m (multiplier) value under test 823 * @n: current DPLL n (divider) value under test 824 * @new_rate: pointer to storage for the resulting rounded rate 825 * @target_rate: the desired DPLL rate 826 * @parent_rate: the DPLL's parent clock rate 827 * 828 * This code tests a DPLL multiplier value, ensuring that the 829 * resulting rate will not be higher than the target_rate, and that 830 * the multiplier value itself is valid for the DPLL. Initially, the 831 * integer pointed to by the m argument should be prescaled by 832 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with 833 * a non-scaled m upon return. This non-scaled m will result in a 834 * new_rate as close as possible to target_rate (but not greater than 835 * target_rate) given the current (parent_rate, n, prescaled m) 836 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the 837 * non-scaled m attempted to underflow, which can allow the calling 838 * function to bail out early; or 0 upon success. 839 */ 840 static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, 841 unsigned long target_rate, 842 unsigned long parent_rate) 843 { 844 int flags = 0, carry = 0; 845 846 /* Unscale m and round if necessary */ 847 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL) 848 carry = 1; 849 *m = (*m / DPLL_SCALE_FACTOR) + carry; 850 851 /* 852 * The new rate must be <= the target rate to avoid programming 853 * a rate that is impossible for the hardware to handle 854 */ 855 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); 856 if (*new_rate > target_rate) { 857 (*m)--; 858 *new_rate = 0; 859 } 860 861 /* Guard against m underflow */ 862 if (*m < DPLL_MIN_MULTIPLIER) { 863 *m = DPLL_MIN_MULTIPLIER; 864 *new_rate = 0; 865 flags = DPLL_MULT_UNDERFLOW; 866 } 867 868 if (*new_rate == 0) 869 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); 870 871 return flags; 872 } 873 874 /** 875 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL 876 * @clk: struct clk * for a DPLL 877 * @target_rate: desired DPLL clock rate 878 * 879 * Given a DPLL, a desired target rate, and a rate tolerance, round 880 * the target rate to a possible, programmable rate for this DPLL. 881 * Rate tolerance is assumed to be set by the caller before this 882 * function is called. Attempts to select the minimum possible n 883 * within the tolerance to reduce power consumption. Stores the 884 * computed (m, n) in the DPLL's dpll_data structure so set_rate() 885 * will not need to call this (expensive) function again. Returns ~0 886 * if the target rate cannot be rounded, either because the rate is 887 * too low or because the rate tolerance is set too tightly; or the 888 * rounded rate upon success. 889 */ 890 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) 891 { 892 int m, n, r, e, scaled_max_m; 893 unsigned long scaled_rt_rp, new_rate; 894 int min_e = -1, min_e_m = -1, min_e_n = -1; 895 896 if (!clk || !clk->dpll_data) 897 return ~0; 898 899 pr_debug("clock: starting DPLL round_rate for clock %s, target rate " 900 "%ld\n", clk->name, target_rate); 901 902 scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR); 903 scaled_max_m = clk->dpll_data->max_multiplier * DPLL_SCALE_FACTOR; 904 905 clk->dpll_data->last_rounded_rate = 0; 906 907 for (n = clk->dpll_data->max_divider; n >= DPLL_MIN_DIVIDER; n--) { 908 909 /* Compute the scaled DPLL multiplier, based on the divider */ 910 m = scaled_rt_rp * n; 911 912 /* 913 * Since we're counting n down, a m overflow means we can 914 * can immediately skip to the next n 915 */ 916 if (m > scaled_max_m) 917 continue; 918 919 r = _dpll_test_mult(&m, n, &new_rate, target_rate, 920 clk->parent->rate); 921 922 e = target_rate - new_rate; 923 pr_debug("clock: n = %d: m = %d: rate error is %d " 924 "(new_rate = %ld)\n", n, m, e, new_rate); 925 926 if (min_e == -1 || 927 min_e >= (int)(abs(e) - clk->dpll_data->rate_tolerance)) { 928 min_e = e; 929 min_e_m = m; 930 min_e_n = n; 931 932 pr_debug("clock: found new least error %d\n", min_e); 933 } 934 935 /* 936 * Since we're counting n down, a m underflow means we 937 * can bail out completely (since as n decreases in 938 * the next iteration, there's no way that m can 939 * increase beyond the current m) 940 */ 941 if (r & DPLL_MULT_UNDERFLOW) 942 break; 943 } 944 945 if (min_e < 0) { 946 pr_debug("clock: error: target rate or tolerance too low\n"); 947 return ~0; 948 } 949 950 clk->dpll_data->last_rounded_m = min_e_m; 951 clk->dpll_data->last_rounded_n = min_e_n; 952 clk->dpll_data->last_rounded_rate = 953 _dpll_compute_new_rate(clk->parent->rate, min_e_m, min_e_n); 954 955 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n", 956 min_e, min_e_m, min_e_n); 957 pr_debug("clock: final rate: %ld (target rate: %ld)\n", 958 clk->dpll_data->last_rounded_rate, target_rate); 959 960 return clk->dpll_data->last_rounded_rate; 961 } 962 963 /*------------------------------------------------------------------------- 964 * Omap2 clock reset and init functions 965 *-------------------------------------------------------------------------*/ 966 967 #ifdef CONFIG_OMAP_RESET_CLOCKS 968 void omap2_clk_disable_unused(struct clk *clk) 969 { 970 u32 regval32, v; 971 972 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0; 973 974 regval32 = __raw_readl(clk->enable_reg); 975 if ((regval32 & (1 << clk->enable_bit)) == v) 976 return; 977 978 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name); 979 _omap2_clk_disable(clk); 980 } 981 #endif 982