1 /* 2 * linux/arch/arm/mach-omap2/clock.c 3 * 4 * Copyright (C) 2005-2008 Texas Instruments, Inc. 5 * Copyright (C) 2004-2008 Nokia Corporation 6 * 7 * Contacts: 8 * Richard Woodruff <r-woodruff2@ti.com> 9 * Paul Walmsley 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 #undef DEBUG 16 17 #include <linux/module.h> 18 #include <linux/kernel.h> 19 #include <linux/device.h> 20 #include <linux/list.h> 21 #include <linux/errno.h> 22 #include <linux/delay.h> 23 #include <linux/clk.h> 24 #include <linux/io.h> 25 #include <linux/bitops.h> 26 27 #include <plat/clock.h> 28 #include <plat/clockdomain.h> 29 #include <plat/cpu.h> 30 #include <plat/prcm.h> 31 #include <asm/div64.h> 32 33 #include <plat/sdrc.h> 34 #include "sdrc.h" 35 #include "clock.h" 36 #include "prm.h" 37 #include "prm-regbits-24xx.h" 38 #include "cm.h" 39 #include "cm-regbits-24xx.h" 40 #include "cm-regbits-34xx.h" 41 42 /* DPLL rate rounding: minimum DPLL multiplier, divider values */ 43 #define DPLL_MIN_MULTIPLIER 1 44 #define DPLL_MIN_DIVIDER 1 45 46 /* Possible error results from _dpll_test_mult */ 47 #define DPLL_MULT_UNDERFLOW -1 48 49 /* 50 * Scale factor to mitigate roundoff errors in DPLL rate rounding. 51 * The higher the scale factor, the greater the risk of arithmetic overflow, 52 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR 53 * must be a power of DPLL_SCALE_BASE. 54 */ 55 #define DPLL_SCALE_FACTOR 64 56 #define DPLL_SCALE_BASE 2 57 #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \ 58 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE)) 59 60 /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ 61 #define DPLL_FINT_BAND1_MIN 750000 62 #define DPLL_FINT_BAND1_MAX 2100000 63 #define DPLL_FINT_BAND2_MIN 7500000 64 #define DPLL_FINT_BAND2_MAX 21000000 65 66 /* _dpll_test_fint() return codes */ 67 #define DPLL_FINT_UNDERFLOW -1 68 #define DPLL_FINT_INVALID -2 69 70 u8 cpu_mask; 71 72 /*------------------------------------------------------------------------- 73 * OMAP2/3/4 specific clock functions 74 *-------------------------------------------------------------------------*/ 75 76 void omap2_init_dpll_parent(struct clk *clk) 77 { 78 u32 v; 79 struct dpll_data *dd; 80 81 dd = clk->dpll_data; 82 if (!dd) 83 return; 84 85 /* Return bypass rate if DPLL is bypassed */ 86 v = __raw_readl(dd->control_reg); 87 v &= dd->enable_mask; 88 v >>= __ffs(dd->enable_mask); 89 90 /* Reparent in case the dpll is in bypass */ 91 if (cpu_is_omap24xx()) { 92 if (v == OMAP2XXX_EN_DPLL_LPBYPASS || 93 v == OMAP2XXX_EN_DPLL_FRBYPASS) 94 clk_reparent(clk, dd->clk_bypass); 95 } else if (cpu_is_omap34xx()) { 96 if (v == OMAP3XXX_EN_DPLL_LPBYPASS || 97 v == OMAP3XXX_EN_DPLL_FRBYPASS) 98 clk_reparent(clk, dd->clk_bypass); 99 } else if (cpu_is_omap44xx()) { 100 if (v == OMAP4XXX_EN_DPLL_LPBYPASS || 101 v == OMAP4XXX_EN_DPLL_FRBYPASS || 102 v == OMAP4XXX_EN_DPLL_MNBYPASS) 103 clk_reparent(clk, dd->clk_bypass); 104 } 105 return; 106 } 107 108 /** 109 * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware 110 * @clk: struct clk * 111 * 112 * If @clk has the DELAYED_APP flag set, meaning that parent/rate changes 113 * don't take effect until the VALID_CONFIG bit is written, write the 114 * VALID_CONFIG bit and wait for the write to complete. No return value. 115 */ 116 static void _omap2xxx_clk_commit(struct clk *clk) 117 { 118 if (!cpu_is_omap24xx()) 119 return; 120 121 if (!(clk->flags & DELAYED_APP)) 122 return; 123 124 prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD, 125 OMAP2_PRCM_CLKCFG_CTRL_OFFSET); 126 /* OCP barrier */ 127 prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP2_PRCM_CLKCFG_CTRL_OFFSET); 128 } 129 130 /* 131 * _dpll_test_fint - test whether an Fint value is valid for the DPLL 132 * @clk: DPLL struct clk to test 133 * @n: divider value (N) to test 134 * 135 * Tests whether a particular divider @n will result in a valid DPLL 136 * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter 137 * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate 138 * (assuming that it is counting N upwards), or -2 if the enclosing loop 139 * should skip to the next iteration (again assuming N is increasing). 140 */ 141 static int _dpll_test_fint(struct clk *clk, u8 n) 142 { 143 struct dpll_data *dd; 144 long fint; 145 int ret = 0; 146 147 dd = clk->dpll_data; 148 149 /* DPLL divider must result in a valid jitter correction val */ 150 fint = clk->parent->rate / (n + 1); 151 if (fint < DPLL_FINT_BAND1_MIN) { 152 153 pr_debug("rejecting n=%d due to Fint failure, " 154 "lowering max_divider\n", n); 155 dd->max_divider = n; 156 ret = DPLL_FINT_UNDERFLOW; 157 158 } else if (fint > DPLL_FINT_BAND1_MAX && 159 fint < DPLL_FINT_BAND2_MIN) { 160 161 pr_debug("rejecting n=%d due to Fint failure\n", n); 162 ret = DPLL_FINT_INVALID; 163 164 } else if (fint > DPLL_FINT_BAND2_MAX) { 165 166 pr_debug("rejecting n=%d due to Fint failure, " 167 "boosting min_divider\n", n); 168 dd->min_divider = n; 169 ret = DPLL_FINT_INVALID; 170 171 } 172 173 return ret; 174 } 175 176 /** 177 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk 178 * @clk: OMAP clock struct ptr to use 179 * 180 * Convert a clockdomain name stored in a struct clk 'clk' into a 181 * clockdomain pointer, and save it into the struct clk. Intended to be 182 * called during clk_register(). No return value. 183 */ 184 #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */ 185 void omap2_init_clk_clkdm(struct clk *clk) 186 { 187 struct clockdomain *clkdm; 188 189 if (!clk->clkdm_name) 190 return; 191 192 clkdm = clkdm_lookup(clk->clkdm_name); 193 if (clkdm) { 194 pr_debug("clock: associated clk %s to clkdm %s\n", 195 clk->name, clk->clkdm_name); 196 clk->clkdm = clkdm; 197 } else { 198 pr_debug("clock: could not associate clk %s to " 199 "clkdm %s\n", clk->name, clk->clkdm_name); 200 } 201 } 202 #endif 203 204 /** 205 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware 206 * @clk: OMAP clock struct ptr to use 207 * 208 * Given a pointer to a source-selectable struct clk, read the hardware 209 * register and determine what its parent is currently set to. Update the 210 * clk->parent field with the appropriate clk ptr. 211 */ 212 void omap2_init_clksel_parent(struct clk *clk) 213 { 214 const struct clksel *clks; 215 const struct clksel_rate *clkr; 216 u32 r, found = 0; 217 218 if (!clk->clksel) 219 return; 220 221 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; 222 r >>= __ffs(clk->clksel_mask); 223 224 for (clks = clk->clksel; clks->parent && !found; clks++) { 225 for (clkr = clks->rates; clkr->div && !found; clkr++) { 226 if ((clkr->flags & cpu_mask) && (clkr->val == r)) { 227 if (clk->parent != clks->parent) { 228 pr_debug("clock: inited %s parent " 229 "to %s (was %s)\n", 230 clk->name, clks->parent->name, 231 ((clk->parent) ? 232 clk->parent->name : "NULL")); 233 clk_reparent(clk, clks->parent); 234 }; 235 found = 1; 236 } 237 } 238 } 239 240 if (!found) 241 printk(KERN_ERR "clock: init parent: could not find " 242 "regval %0x for clock %s\n", r, clk->name); 243 244 return; 245 } 246 247 /** 248 * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate 249 * @clk: struct clk * of a DPLL 250 * 251 * DPLLs can be locked or bypassed - basically, enabled or disabled. 252 * When locked, the DPLL output depends on the M and N values. When 253 * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock 254 * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and 255 * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively 256 * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk. 257 * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is 258 * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0 259 * if the clock @clk is not a DPLL. 260 */ 261 u32 omap2_get_dpll_rate(struct clk *clk) 262 { 263 long long dpll_clk; 264 u32 dpll_mult, dpll_div, v; 265 struct dpll_data *dd; 266 267 dd = clk->dpll_data; 268 if (!dd) 269 return 0; 270 271 /* Return bypass rate if DPLL is bypassed */ 272 v = __raw_readl(dd->control_reg); 273 v &= dd->enable_mask; 274 v >>= __ffs(dd->enable_mask); 275 276 if (cpu_is_omap24xx()) { 277 if (v == OMAP2XXX_EN_DPLL_LPBYPASS || 278 v == OMAP2XXX_EN_DPLL_FRBYPASS) 279 return dd->clk_bypass->rate; 280 } else if (cpu_is_omap34xx()) { 281 if (v == OMAP3XXX_EN_DPLL_LPBYPASS || 282 v == OMAP3XXX_EN_DPLL_FRBYPASS) 283 return dd->clk_bypass->rate; 284 } else if (cpu_is_omap44xx()) { 285 if (v == OMAP4XXX_EN_DPLL_LPBYPASS || 286 v == OMAP4XXX_EN_DPLL_FRBYPASS || 287 v == OMAP4XXX_EN_DPLL_MNBYPASS) 288 return dd->clk_bypass->rate; 289 } 290 291 v = __raw_readl(dd->mult_div1_reg); 292 dpll_mult = v & dd->mult_mask; 293 dpll_mult >>= __ffs(dd->mult_mask); 294 dpll_div = v & dd->div1_mask; 295 dpll_div >>= __ffs(dd->div1_mask); 296 297 dpll_clk = (long long)dd->clk_ref->rate * dpll_mult; 298 do_div(dpll_clk, dpll_div + 1); 299 300 return dpll_clk; 301 } 302 303 /* 304 * Used for clocks that have the same value as the parent clock, 305 * divided by some factor 306 */ 307 unsigned long omap2_fixed_divisor_recalc(struct clk *clk) 308 { 309 WARN_ON(!clk->fixed_div); 310 311 return clk->parent->rate / clk->fixed_div; 312 } 313 314 /** 315 * omap2_clk_dflt_find_companion - find companion clock to @clk 316 * @clk: struct clk * to find the companion clock of 317 * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in 318 * @other_bit: u8 ** to return the companion clock bit shift in 319 * 320 * Note: We don't need special code here for INVERT_ENABLE for the 321 * time being since INVERT_ENABLE only applies to clocks enabled by 322 * CM_CLKEN_PLL 323 * 324 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's 325 * just a matter of XORing the bits. 326 * 327 * Some clocks don't have companion clocks. For example, modules with 328 * only an interface clock (such as MAILBOXES) don't have a companion 329 * clock. Right now, this code relies on the hardware exporting a bit 330 * in the correct companion register that indicates that the 331 * nonexistent 'companion clock' is active. Future patches will 332 * associate this type of code with per-module data structures to 333 * avoid this issue, and remove the casts. No return value. 334 */ 335 void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, 336 u8 *other_bit) 337 { 338 u32 r; 339 340 /* 341 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes 342 * it's just a matter of XORing the bits. 343 */ 344 r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN)); 345 346 *other_reg = (__force void __iomem *)r; 347 *other_bit = clk->enable_bit; 348 } 349 350 /** 351 * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk 352 * @clk: struct clk * to find IDLEST info for 353 * @idlest_reg: void __iomem ** to return the CM_IDLEST va in 354 * @idlest_bit: u8 ** to return the CM_IDLEST bit shift in 355 * 356 * Return the CM_IDLEST register address and bit shift corresponding 357 * to the module that "owns" this clock. This default code assumes 358 * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that 359 * the IDLEST register address ID corresponds to the CM_*CLKEN 360 * register address ID (e.g., that CM_FCLKEN2 corresponds to 361 * CM_IDLEST2). This is not true for all modules. No return value. 362 */ 363 void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, 364 u8 *idlest_bit) 365 { 366 u32 r; 367 368 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); 369 *idlest_reg = (__force void __iomem *)r; 370 *idlest_bit = clk->enable_bit; 371 } 372 373 /** 374 * omap2_module_wait_ready - wait for an OMAP module to leave IDLE 375 * @clk: struct clk * belonging to the module 376 * 377 * If the necessary clocks for the OMAP hardware IP block that 378 * corresponds to clock @clk are enabled, then wait for the module to 379 * indicate readiness (i.e., to leave IDLE). This code does not 380 * belong in the clock code and will be moved in the medium term to 381 * module-dependent code. No return value. 382 */ 383 static void omap2_module_wait_ready(struct clk *clk) 384 { 385 void __iomem *companion_reg, *idlest_reg; 386 u8 other_bit, idlest_bit; 387 388 /* Not all modules have multiple clocks that their IDLEST depends on */ 389 if (clk->ops->find_companion) { 390 clk->ops->find_companion(clk, &companion_reg, &other_bit); 391 if (!(__raw_readl(companion_reg) & (1 << other_bit))) 392 return; 393 } 394 395 clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit); 396 397 omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), clk->name); 398 } 399 400 int omap2_dflt_clk_enable(struct clk *clk) 401 { 402 u32 v; 403 404 if (unlikely(clk->enable_reg == NULL)) { 405 pr_err("clock.c: Enable for %s without enable code\n", 406 clk->name); 407 return 0; /* REVISIT: -EINVAL */ 408 } 409 410 v = __raw_readl(clk->enable_reg); 411 if (clk->flags & INVERT_ENABLE) 412 v &= ~(1 << clk->enable_bit); 413 else 414 v |= (1 << clk->enable_bit); 415 __raw_writel(v, clk->enable_reg); 416 v = __raw_readl(clk->enable_reg); /* OCP barrier */ 417 418 if (clk->ops->find_idlest) 419 omap2_module_wait_ready(clk); 420 421 return 0; 422 } 423 424 void omap2_dflt_clk_disable(struct clk *clk) 425 { 426 u32 v; 427 428 if (!clk->enable_reg) { 429 /* 430 * 'Independent' here refers to a clock which is not 431 * controlled by its parent. 432 */ 433 printk(KERN_ERR "clock: clk_disable called on independent " 434 "clock %s which has no enable_reg\n", clk->name); 435 return; 436 } 437 438 v = __raw_readl(clk->enable_reg); 439 if (clk->flags & INVERT_ENABLE) 440 v |= (1 << clk->enable_bit); 441 else 442 v &= ~(1 << clk->enable_bit); 443 __raw_writel(v, clk->enable_reg); 444 /* No OCP barrier needed here since it is a disable operation */ 445 } 446 447 const struct clkops clkops_omap2_dflt_wait = { 448 .enable = omap2_dflt_clk_enable, 449 .disable = omap2_dflt_clk_disable, 450 .find_companion = omap2_clk_dflt_find_companion, 451 .find_idlest = omap2_clk_dflt_find_idlest, 452 }; 453 454 const struct clkops clkops_omap2_dflt = { 455 .enable = omap2_dflt_clk_enable, 456 .disable = omap2_dflt_clk_disable, 457 }; 458 459 /* Enables clock without considering parent dependencies or use count 460 * REVISIT: Maybe change this to use clk->enable like on omap1? 461 */ 462 static int _omap2_clk_enable(struct clk *clk) 463 { 464 return clk->ops->enable(clk); 465 } 466 467 /* Disables clock without considering parent dependencies or use count */ 468 static void _omap2_clk_disable(struct clk *clk) 469 { 470 clk->ops->disable(clk); 471 } 472 473 void omap2_clk_disable(struct clk *clk) 474 { 475 if (clk->usecount > 0 && !(--clk->usecount)) { 476 _omap2_clk_disable(clk); 477 if (clk->parent) 478 omap2_clk_disable(clk->parent); 479 #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */ 480 if (clk->clkdm) 481 omap2_clkdm_clk_disable(clk->clkdm, clk); 482 #endif 483 484 } 485 } 486 487 int omap2_clk_enable(struct clk *clk) 488 { 489 int ret = 0; 490 491 if (clk->usecount++ == 0) { 492 #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */ 493 if (clk->clkdm) 494 omap2_clkdm_clk_enable(clk->clkdm, clk); 495 #endif 496 497 if (clk->parent) { 498 ret = omap2_clk_enable(clk->parent); 499 if (ret) 500 goto err; 501 } 502 503 ret = _omap2_clk_enable(clk); 504 if (ret) { 505 if (clk->parent) 506 omap2_clk_disable(clk->parent); 507 508 goto err; 509 } 510 } 511 return ret; 512 513 err: 514 #ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */ 515 if (clk->clkdm) 516 omap2_clkdm_clk_disable(clk->clkdm, clk); 517 #endif 518 clk->usecount--; 519 return ret; 520 } 521 522 /* 523 * Used for clocks that are part of CLKSEL_xyz governed clocks. 524 * REVISIT: Maybe change to use clk->enable() functions like on omap1? 525 */ 526 unsigned long omap2_clksel_recalc(struct clk *clk) 527 { 528 unsigned long rate; 529 u32 div = 0; 530 531 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name); 532 533 div = omap2_clksel_get_divisor(clk); 534 if (div == 0) 535 return clk->rate; 536 537 rate = clk->parent->rate / div; 538 539 pr_debug("clock: new clock rate is %ld (div %d)\n", rate, div); 540 541 return rate; 542 } 543 544 /** 545 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent 546 * @clk: OMAP struct clk ptr to inspect 547 * @src_clk: OMAP struct clk ptr of the parent clk to search for 548 * 549 * Scan the struct clksel array associated with the clock to find 550 * the element associated with the supplied parent clock address. 551 * Returns a pointer to the struct clksel on success or NULL on error. 552 */ 553 static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk, 554 struct clk *src_clk) 555 { 556 const struct clksel *clks; 557 558 if (!clk->clksel) 559 return NULL; 560 561 for (clks = clk->clksel; clks->parent; clks++) { 562 if (clks->parent == src_clk) 563 break; /* Found the requested parent */ 564 } 565 566 if (!clks->parent) { 567 printk(KERN_ERR "clock: Could not find parent clock %s in " 568 "clksel array of clock %s\n", src_clk->name, 569 clk->name); 570 return NULL; 571 } 572 573 return clks; 574 } 575 576 /** 577 * omap2_clksel_round_rate_div - find divisor for the given clock and rate 578 * @clk: OMAP struct clk to use 579 * @target_rate: desired clock rate 580 * @new_div: ptr to where we should store the divisor 581 * 582 * Finds 'best' divider value in an array based on the source and target 583 * rates. The divider array must be sorted with smallest divider first. 584 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, 585 * they are only settable as part of virtual_prcm set. 586 * 587 * Returns the rounded clock rate or returns 0xffffffff on error. 588 */ 589 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, 590 u32 *new_div) 591 { 592 unsigned long test_rate; 593 const struct clksel *clks; 594 const struct clksel_rate *clkr; 595 u32 last_div = 0; 596 597 pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n", 598 clk->name, target_rate); 599 600 *new_div = 1; 601 602 clks = omap2_get_clksel_by_parent(clk, clk->parent); 603 if (!clks) 604 return ~0; 605 606 for (clkr = clks->rates; clkr->div; clkr++) { 607 if (!(clkr->flags & cpu_mask)) 608 continue; 609 610 /* Sanity check */ 611 if (clkr->div <= last_div) 612 pr_err("clock: clksel_rate table not sorted " 613 "for clock %s", clk->name); 614 615 last_div = clkr->div; 616 617 test_rate = clk->parent->rate / clkr->div; 618 619 if (test_rate <= target_rate) 620 break; /* found it */ 621 } 622 623 if (!clkr->div) { 624 pr_err("clock: Could not find divisor for target " 625 "rate %ld for clock %s parent %s\n", target_rate, 626 clk->name, clk->parent->name); 627 return ~0; 628 } 629 630 *new_div = clkr->div; 631 632 pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div, 633 (clk->parent->rate / clkr->div)); 634 635 return (clk->parent->rate / clkr->div); 636 } 637 638 /** 639 * omap2_clksel_round_rate - find rounded rate for the given clock and rate 640 * @clk: OMAP struct clk to use 641 * @target_rate: desired clock rate 642 * 643 * Compatibility wrapper for OMAP clock framework 644 * Finds best target rate based on the source clock and possible dividers. 645 * rates. The divider array must be sorted with smallest divider first. 646 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, 647 * they are only settable as part of virtual_prcm set. 648 * 649 * Returns the rounded clock rate or returns 0xffffffff on error. 650 */ 651 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) 652 { 653 u32 new_div; 654 655 return omap2_clksel_round_rate_div(clk, target_rate, &new_div); 656 } 657 658 659 /* Given a clock and a rate apply a clock specific rounding function */ 660 long omap2_clk_round_rate(struct clk *clk, unsigned long rate) 661 { 662 if (clk->round_rate) 663 return clk->round_rate(clk, rate); 664 665 if (clk->flags & RATE_FIXED) 666 printk(KERN_ERR "clock: generic omap2_clk_round_rate called " 667 "on fixed-rate clock %s\n", clk->name); 668 669 return clk->rate; 670 } 671 672 /** 673 * omap2_clksel_to_divisor() - turn clksel field value into integer divider 674 * @clk: OMAP struct clk to use 675 * @field_val: register field value to find 676 * 677 * Given a struct clk of a rate-selectable clksel clock, and a register field 678 * value to search for, find the corresponding clock divisor. The register 679 * field value should be pre-masked and shifted down so the LSB is at bit 0 680 * before calling. Returns 0 on error 681 */ 682 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val) 683 { 684 const struct clksel *clks; 685 const struct clksel_rate *clkr; 686 687 clks = omap2_get_clksel_by_parent(clk, clk->parent); 688 if (!clks) 689 return 0; 690 691 for (clkr = clks->rates; clkr->div; clkr++) { 692 if ((clkr->flags & cpu_mask) && (clkr->val == field_val)) 693 break; 694 } 695 696 if (!clkr->div) { 697 printk(KERN_ERR "clock: Could not find fieldval %d for " 698 "clock %s parent %s\n", field_val, clk->name, 699 clk->parent->name); 700 return 0; 701 } 702 703 return clkr->div; 704 } 705 706 /** 707 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value 708 * @clk: OMAP struct clk to use 709 * @div: integer divisor to search for 710 * 711 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor, 712 * find the corresponding register field value. The return register value is 713 * the value before left-shifting. Returns ~0 on error 714 */ 715 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div) 716 { 717 const struct clksel *clks; 718 const struct clksel_rate *clkr; 719 720 /* should never happen */ 721 WARN_ON(div == 0); 722 723 clks = omap2_get_clksel_by_parent(clk, clk->parent); 724 if (!clks) 725 return ~0; 726 727 for (clkr = clks->rates; clkr->div; clkr++) { 728 if ((clkr->flags & cpu_mask) && (clkr->div == div)) 729 break; 730 } 731 732 if (!clkr->div) { 733 printk(KERN_ERR "clock: Could not find divisor %d for " 734 "clock %s parent %s\n", div, clk->name, 735 clk->parent->name); 736 return ~0; 737 } 738 739 return clkr->val; 740 } 741 742 /** 743 * omap2_clksel_get_divisor - get current divider applied to parent clock. 744 * @clk: OMAP struct clk to use. 745 * 746 * Returns the integer divisor upon success or 0 on error. 747 */ 748 u32 omap2_clksel_get_divisor(struct clk *clk) 749 { 750 u32 v; 751 752 if (!clk->clksel_mask) 753 return 0; 754 755 v = __raw_readl(clk->clksel_reg) & clk->clksel_mask; 756 v >>= __ffs(clk->clksel_mask); 757 758 return omap2_clksel_to_divisor(clk, v); 759 } 760 761 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) 762 { 763 u32 v, field_val, validrate, new_div = 0; 764 765 if (!clk->clksel_mask) 766 return -EINVAL; 767 768 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); 769 if (validrate != rate) 770 return -EINVAL; 771 772 field_val = omap2_divisor_to_clksel(clk, new_div); 773 if (field_val == ~0) 774 return -EINVAL; 775 776 v = __raw_readl(clk->clksel_reg); 777 v &= ~clk->clksel_mask; 778 v |= field_val << __ffs(clk->clksel_mask); 779 __raw_writel(v, clk->clksel_reg); 780 v = __raw_readl(clk->clksel_reg); /* OCP barrier */ 781 782 clk->rate = clk->parent->rate / new_div; 783 784 _omap2xxx_clk_commit(clk); 785 786 return 0; 787 } 788 789 790 /* Set the clock rate for a clock source */ 791 int omap2_clk_set_rate(struct clk *clk, unsigned long rate) 792 { 793 int ret = -EINVAL; 794 795 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate); 796 797 /* CONFIG_PARTICIPANT clocks are changed only in sets via the 798 rate table mechanism, driven by mpu_speed */ 799 if (clk->flags & CONFIG_PARTICIPANT) 800 return -EINVAL; 801 802 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ 803 if (clk->set_rate) 804 ret = clk->set_rate(clk, rate); 805 806 return ret; 807 } 808 809 /* 810 * Converts encoded control register address into a full address 811 * On error, the return value (parent_div) will be 0. 812 */ 813 static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk, 814 u32 *field_val) 815 { 816 const struct clksel *clks; 817 const struct clksel_rate *clkr; 818 819 clks = omap2_get_clksel_by_parent(clk, src_clk); 820 if (!clks) 821 return 0; 822 823 for (clkr = clks->rates; clkr->div; clkr++) { 824 if (clkr->flags & cpu_mask && clkr->flags & DEFAULT_RATE) 825 break; /* Found the default rate for this platform */ 826 } 827 828 if (!clkr->div) { 829 printk(KERN_ERR "clock: Could not find default rate for " 830 "clock %s parent %s\n", clk->name, 831 src_clk->parent->name); 832 return 0; 833 } 834 835 /* Should never happen. Add a clksel mask to the struct clk. */ 836 WARN_ON(clk->clksel_mask == 0); 837 838 *field_val = clkr->val; 839 840 return clkr->div; 841 } 842 843 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) 844 { 845 u32 field_val, v, parent_div; 846 847 if (clk->flags & CONFIG_PARTICIPANT) 848 return -EINVAL; 849 850 if (!clk->clksel) 851 return -EINVAL; 852 853 parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val); 854 if (!parent_div) 855 return -EINVAL; 856 857 /* Set new source value (previous dividers if any in effect) */ 858 v = __raw_readl(clk->clksel_reg); 859 v &= ~clk->clksel_mask; 860 v |= field_val << __ffs(clk->clksel_mask); 861 __raw_writel(v, clk->clksel_reg); 862 v = __raw_readl(clk->clksel_reg); /* OCP barrier */ 863 864 _omap2xxx_clk_commit(clk); 865 866 clk_reparent(clk, new_parent); 867 868 /* CLKSEL clocks follow their parents' rates, divided by a divisor */ 869 clk->rate = new_parent->rate; 870 871 if (parent_div > 0) 872 clk->rate /= parent_div; 873 874 pr_debug("clock: set parent of %s to %s (new rate %ld)\n", 875 clk->name, clk->parent->name, clk->rate); 876 877 return 0; 878 } 879 880 /* DPLL rate rounding code */ 881 882 /** 883 * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding 884 * @clk: struct clk * of the DPLL 885 * @tolerance: maximum rate error tolerance 886 * 887 * Set the maximum DPLL rate error tolerance for the rate rounding 888 * algorithm. The rate tolerance is an attempt to balance DPLL power 889 * saving (the least divider value "n") vs. rate fidelity (the least 890 * difference between the desired DPLL target rate and the rounded 891 * rate out of the algorithm). So, increasing the tolerance is likely 892 * to decrease DPLL power consumption and increase DPLL rate error. 893 * Returns -EINVAL if provided a null clock ptr or a clk that is not a 894 * DPLL; or 0 upon success. 895 */ 896 int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance) 897 { 898 if (!clk || !clk->dpll_data) 899 return -EINVAL; 900 901 clk->dpll_data->rate_tolerance = tolerance; 902 903 return 0; 904 } 905 906 static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, 907 unsigned int m, unsigned int n) 908 { 909 unsigned long long num; 910 911 num = (unsigned long long)parent_rate * m; 912 do_div(num, n); 913 return num; 914 } 915 916 /* 917 * _dpll_test_mult - test a DPLL multiplier value 918 * @m: pointer to the DPLL m (multiplier) value under test 919 * @n: current DPLL n (divider) value under test 920 * @new_rate: pointer to storage for the resulting rounded rate 921 * @target_rate: the desired DPLL rate 922 * @parent_rate: the DPLL's parent clock rate 923 * 924 * This code tests a DPLL multiplier value, ensuring that the 925 * resulting rate will not be higher than the target_rate, and that 926 * the multiplier value itself is valid for the DPLL. Initially, the 927 * integer pointed to by the m argument should be prescaled by 928 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with 929 * a non-scaled m upon return. This non-scaled m will result in a 930 * new_rate as close as possible to target_rate (but not greater than 931 * target_rate) given the current (parent_rate, n, prescaled m) 932 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the 933 * non-scaled m attempted to underflow, which can allow the calling 934 * function to bail out early; or 0 upon success. 935 */ 936 static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, 937 unsigned long target_rate, 938 unsigned long parent_rate) 939 { 940 int r = 0, carry = 0; 941 942 /* Unscale m and round if necessary */ 943 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL) 944 carry = 1; 945 *m = (*m / DPLL_SCALE_FACTOR) + carry; 946 947 /* 948 * The new rate must be <= the target rate to avoid programming 949 * a rate that is impossible for the hardware to handle 950 */ 951 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); 952 if (*new_rate > target_rate) { 953 (*m)--; 954 *new_rate = 0; 955 } 956 957 /* Guard against m underflow */ 958 if (*m < DPLL_MIN_MULTIPLIER) { 959 *m = DPLL_MIN_MULTIPLIER; 960 *new_rate = 0; 961 r = DPLL_MULT_UNDERFLOW; 962 } 963 964 if (*new_rate == 0) 965 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); 966 967 return r; 968 } 969 970 /** 971 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL 972 * @clk: struct clk * for a DPLL 973 * @target_rate: desired DPLL clock rate 974 * 975 * Given a DPLL, a desired target rate, and a rate tolerance, round 976 * the target rate to a possible, programmable rate for this DPLL. 977 * Rate tolerance is assumed to be set by the caller before this 978 * function is called. Attempts to select the minimum possible n 979 * within the tolerance to reduce power consumption. Stores the 980 * computed (m, n) in the DPLL's dpll_data structure so set_rate() 981 * will not need to call this (expensive) function again. Returns ~0 982 * if the target rate cannot be rounded, either because the rate is 983 * too low or because the rate tolerance is set too tightly; or the 984 * rounded rate upon success. 985 */ 986 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) 987 { 988 int m, n, r, e, scaled_max_m; 989 unsigned long scaled_rt_rp, new_rate; 990 int min_e = -1, min_e_m = -1, min_e_n = -1; 991 struct dpll_data *dd; 992 993 if (!clk || !clk->dpll_data) 994 return ~0; 995 996 dd = clk->dpll_data; 997 998 pr_debug("clock: starting DPLL round_rate for clock %s, target rate " 999 "%ld\n", clk->name, target_rate); 1000 1001 scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR); 1002 scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR; 1003 1004 dd->last_rounded_rate = 0; 1005 1006 for (n = dd->min_divider; n <= dd->max_divider; n++) { 1007 1008 /* Is the (input clk, divider) pair valid for the DPLL? */ 1009 r = _dpll_test_fint(clk, n); 1010 if (r == DPLL_FINT_UNDERFLOW) 1011 break; 1012 else if (r == DPLL_FINT_INVALID) 1013 continue; 1014 1015 /* Compute the scaled DPLL multiplier, based on the divider */ 1016 m = scaled_rt_rp * n; 1017 1018 /* 1019 * Since we're counting n up, a m overflow means we 1020 * can bail out completely (since as n increases in 1021 * the next iteration, there's no way that m can 1022 * increase beyond the current m) 1023 */ 1024 if (m > scaled_max_m) 1025 break; 1026 1027 r = _dpll_test_mult(&m, n, &new_rate, target_rate, 1028 dd->clk_ref->rate); 1029 1030 /* m can't be set low enough for this n - try with a larger n */ 1031 if (r == DPLL_MULT_UNDERFLOW) 1032 continue; 1033 1034 e = target_rate - new_rate; 1035 pr_debug("clock: n = %d: m = %d: rate error is %d " 1036 "(new_rate = %ld)\n", n, m, e, new_rate); 1037 1038 if (min_e == -1 || 1039 min_e >= (int)(abs(e) - dd->rate_tolerance)) { 1040 min_e = e; 1041 min_e_m = m; 1042 min_e_n = n; 1043 1044 pr_debug("clock: found new least error %d\n", min_e); 1045 1046 /* We found good settings -- bail out now */ 1047 if (min_e <= dd->rate_tolerance) 1048 break; 1049 } 1050 } 1051 1052 if (min_e < 0) { 1053 pr_debug("clock: error: target rate or tolerance too low\n"); 1054 return ~0; 1055 } 1056 1057 dd->last_rounded_m = min_e_m; 1058 dd->last_rounded_n = min_e_n; 1059 dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate, 1060 min_e_m, min_e_n); 1061 1062 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n", 1063 min_e, min_e_m, min_e_n); 1064 pr_debug("clock: final rate: %ld (target rate: %ld)\n", 1065 dd->last_rounded_rate, target_rate); 1066 1067 return dd->last_rounded_rate; 1068 } 1069 1070 /*------------------------------------------------------------------------- 1071 * Omap2 clock reset and init functions 1072 *-------------------------------------------------------------------------*/ 1073 1074 #ifdef CONFIG_OMAP_RESET_CLOCKS 1075 void omap2_clk_disable_unused(struct clk *clk) 1076 { 1077 u32 regval32, v; 1078 1079 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0; 1080 1081 regval32 = __raw_readl(clk->enable_reg); 1082 if ((regval32 & (1 << clk->enable_bit)) == v) 1083 return; 1084 1085 printk(KERN_DEBUG "Disabling unused clock \"%s\"\n", clk->name); 1086 if (cpu_is_omap34xx()) { 1087 omap2_clk_enable(clk); 1088 omap2_clk_disable(clk); 1089 } else 1090 _omap2_clk_disable(clk); 1091 if (clk->clkdm != NULL) 1092 pwrdm_clkdm_state_switch(clk->clkdm); 1093 } 1094 #endif 1095