1 /* 2 * linux/arch/arm/mach-omap2/clock.c 3 * 4 * Copyright (C) 2005-2008 Texas Instruments, Inc. 5 * Copyright (C) 2004-2008 Nokia Corporation 6 * 7 * Contacts: 8 * Richard Woodruff <r-woodruff2@ti.com> 9 * Paul Walmsley 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 #undef DEBUG 16 17 #include <linux/module.h> 18 #include <linux/kernel.h> 19 #include <linux/device.h> 20 #include <linux/list.h> 21 #include <linux/errno.h> 22 #include <linux/delay.h> 23 #include <linux/clk.h> 24 #include <linux/io.h> 25 #include <linux/bitops.h> 26 27 #include <mach/clock.h> 28 #include <mach/clockdomain.h> 29 #include <mach/cpu.h> 30 #include <asm/div64.h> 31 32 #include "memory.h" 33 #include "sdrc.h" 34 #include "clock.h" 35 #include "prm.h" 36 #include "prm-regbits-24xx.h" 37 #include "cm.h" 38 #include "cm-regbits-24xx.h" 39 #include "cm-regbits-34xx.h" 40 41 #define MAX_CLOCK_ENABLE_WAIT 100000 42 43 /* DPLL rate rounding: minimum DPLL multiplier, divider values */ 44 #define DPLL_MIN_MULTIPLIER 1 45 #define DPLL_MIN_DIVIDER 1 46 47 /* Possible error results from _dpll_test_mult */ 48 #define DPLL_MULT_UNDERFLOW (1 << 0) 49 50 /* 51 * Scale factor to mitigate roundoff errors in DPLL rate rounding. 52 * The higher the scale factor, the greater the risk of arithmetic overflow, 53 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR 54 * must be a power of DPLL_SCALE_BASE. 55 */ 56 #define DPLL_SCALE_FACTOR 64 57 #define DPLL_SCALE_BASE 2 58 #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \ 59 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE)) 60 61 u8 cpu_mask; 62 63 /*------------------------------------------------------------------------- 64 * OMAP2/3 specific clock functions 65 *-------------------------------------------------------------------------*/ 66 67 /** 68 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk 69 * @clk: OMAP clock struct ptr to use 70 * 71 * Convert a clockdomain name stored in a struct clk 'clk' into a 72 * clockdomain pointer, and save it into the struct clk. Intended to be 73 * called during clk_register(). No return value. 74 */ 75 void omap2_init_clk_clkdm(struct clk *clk) 76 { 77 struct clockdomain *clkdm; 78 79 if (!clk->clkdm_name) 80 return; 81 82 clkdm = clkdm_lookup(clk->clkdm_name); 83 if (clkdm) { 84 pr_debug("clock: associated clk %s to clkdm %s\n", 85 clk->name, clk->clkdm_name); 86 clk->clkdm = clkdm; 87 } else { 88 pr_debug("clock: could not associate clk %s to " 89 "clkdm %s\n", clk->name, clk->clkdm_name); 90 } 91 } 92 93 /** 94 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware 95 * @clk: OMAP clock struct ptr to use 96 * 97 * Given a pointer to a source-selectable struct clk, read the hardware 98 * register and determine what its parent is currently set to. Update the 99 * clk->parent field with the appropriate clk ptr. 100 */ 101 void omap2_init_clksel_parent(struct clk *clk) 102 { 103 const struct clksel *clks; 104 const struct clksel_rate *clkr; 105 u32 r, found = 0; 106 107 if (!clk->clksel) 108 return; 109 110 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask; 111 r >>= __ffs(clk->clksel_mask); 112 113 for (clks = clk->clksel; clks->parent && !found; clks++) { 114 for (clkr = clks->rates; clkr->div && !found; clkr++) { 115 if ((clkr->flags & cpu_mask) && (clkr->val == r)) { 116 if (clk->parent != clks->parent) { 117 pr_debug("clock: inited %s parent " 118 "to %s (was %s)\n", 119 clk->name, clks->parent->name, 120 ((clk->parent) ? 121 clk->parent->name : "NULL")); 122 clk->parent = clks->parent; 123 }; 124 found = 1; 125 } 126 } 127 } 128 129 if (!found) 130 printk(KERN_ERR "clock: init parent: could not find " 131 "regval %0x for clock %s\n", r, clk->name); 132 133 return; 134 } 135 136 /* Returns the DPLL rate */ 137 u32 omap2_get_dpll_rate(struct clk *clk) 138 { 139 long long dpll_clk; 140 u32 dpll_mult, dpll_div, dpll; 141 struct dpll_data *dd; 142 143 dd = clk->dpll_data; 144 /* REVISIT: What do we return on error? */ 145 if (!dd) 146 return 0; 147 148 dpll = __raw_readl(dd->mult_div1_reg); 149 dpll_mult = dpll & dd->mult_mask; 150 dpll_mult >>= __ffs(dd->mult_mask); 151 dpll_div = dpll & dd->div1_mask; 152 dpll_div >>= __ffs(dd->div1_mask); 153 154 dpll_clk = (long long)clk->parent->rate * dpll_mult; 155 do_div(dpll_clk, dpll_div + 1); 156 157 return dpll_clk; 158 } 159 160 /* 161 * Used for clocks that have the same value as the parent clock, 162 * divided by some factor 163 */ 164 void omap2_fixed_divisor_recalc(struct clk *clk) 165 { 166 WARN_ON(!clk->fixed_div); 167 168 clk->rate = clk->parent->rate / clk->fixed_div; 169 } 170 171 /** 172 * omap2_wait_clock_ready - wait for clock to enable 173 * @reg: physical address of clock IDLEST register 174 * @mask: value to mask against to determine if the clock is active 175 * @name: name of the clock (for printk) 176 * 177 * Returns 1 if the clock enabled in time, or 0 if it failed to enable 178 * in roughly MAX_CLOCK_ENABLE_WAIT microseconds. 179 */ 180 int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name) 181 { 182 int i = 0; 183 int ena = 0; 184 185 /* 186 * 24xx uses 0 to indicate not ready, and 1 to indicate ready. 187 * 34xx reverses this, just to keep us on our toes 188 */ 189 if (cpu_mask & (RATE_IN_242X | RATE_IN_243X)) 190 ena = mask; 191 else if (cpu_mask & RATE_IN_343X) 192 ena = 0; 193 194 /* Wait for lock */ 195 while (((__raw_readl(reg) & mask) != ena) && 196 (i++ < MAX_CLOCK_ENABLE_WAIT)) { 197 udelay(1); 198 } 199 200 if (i < MAX_CLOCK_ENABLE_WAIT) 201 pr_debug("Clock %s stable after %d loops\n", name, i); 202 else 203 printk(KERN_ERR "Clock %s didn't enable in %d tries\n", 204 name, MAX_CLOCK_ENABLE_WAIT); 205 206 207 return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0; 208 }; 209 210 211 /* 212 * Note: We don't need special code here for INVERT_ENABLE 213 * for the time being since INVERT_ENABLE only applies to clocks enabled by 214 * CM_CLKEN_PLL 215 */ 216 static void omap2_clk_wait_ready(struct clk *clk) 217 { 218 void __iomem *reg, *other_reg, *st_reg; 219 u32 bit; 220 221 /* 222 * REVISIT: This code is pretty ugly. It would be nice to generalize 223 * it and pull it into struct clk itself somehow. 224 */ 225 reg = clk->enable_reg; 226 227 /* 228 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes 229 * it's just a matter of XORing the bits. 230 */ 231 other_reg = (void __iomem *)((u32)reg ^ (CM_FCLKEN ^ CM_ICLKEN)); 232 233 /* Check if both functional and interface clocks 234 * are running. */ 235 bit = 1 << clk->enable_bit; 236 if (!(__raw_readl(other_reg) & bit)) 237 return; 238 st_reg = (void __iomem *)(((u32)other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */ 239 240 omap2_wait_clock_ready(st_reg, bit, clk->name); 241 } 242 243 static int omap2_dflt_clk_enable(struct clk *clk) 244 { 245 u32 regval32; 246 247 if (unlikely(clk->enable_reg == NULL)) { 248 printk(KERN_ERR "clock.c: Enable for %s without enable code\n", 249 clk->name); 250 return 0; /* REVISIT: -EINVAL */ 251 } 252 253 regval32 = __raw_readl(clk->enable_reg); 254 if (clk->flags & INVERT_ENABLE) 255 regval32 &= ~(1 << clk->enable_bit); 256 else 257 regval32 |= (1 << clk->enable_bit); 258 __raw_writel(regval32, clk->enable_reg); 259 wmb(); 260 261 return 0; 262 } 263 264 static int omap2_dflt_clk_enable_wait(struct clk *clk) 265 { 266 int ret; 267 268 if (!clk->enable_reg) { 269 printk(KERN_ERR "clock.c: Enable for %s without enable code\n", 270 clk->name); 271 return 0; /* REVISIT: -EINVAL */ 272 } 273 274 ret = omap2_dflt_clk_enable(clk); 275 if (ret == 0) 276 omap2_clk_wait_ready(clk); 277 return ret; 278 } 279 280 static void omap2_dflt_clk_disable(struct clk *clk) 281 { 282 u32 regval32; 283 284 if (!clk->enable_reg) { 285 /* 286 * 'Independent' here refers to a clock which is not 287 * controlled by its parent. 288 */ 289 printk(KERN_ERR "clock: clk_disable called on independent " 290 "clock %s which has no enable_reg\n", clk->name); 291 return; 292 } 293 294 regval32 = __raw_readl(clk->enable_reg); 295 if (clk->flags & INVERT_ENABLE) 296 regval32 |= (1 << clk->enable_bit); 297 else 298 regval32 &= ~(1 << clk->enable_bit); 299 __raw_writel(regval32, clk->enable_reg); 300 wmb(); 301 } 302 303 const struct clkops clkops_omap2_dflt_wait = { 304 .enable = omap2_dflt_clk_enable_wait, 305 .disable = omap2_dflt_clk_disable, 306 }; 307 308 const struct clkops clkops_omap2_dflt = { 309 .enable = omap2_dflt_clk_enable, 310 .disable = omap2_dflt_clk_disable, 311 }; 312 313 /* Enables clock without considering parent dependencies or use count 314 * REVISIT: Maybe change this to use clk->enable like on omap1? 315 */ 316 static int _omap2_clk_enable(struct clk *clk) 317 { 318 return clk->ops->enable(clk); 319 } 320 321 /* Disables clock without considering parent dependencies or use count */ 322 static void _omap2_clk_disable(struct clk *clk) 323 { 324 clk->ops->disable(clk); 325 } 326 327 void omap2_clk_disable(struct clk *clk) 328 { 329 if (clk->usecount > 0 && !(--clk->usecount)) { 330 _omap2_clk_disable(clk); 331 if (clk->parent) 332 omap2_clk_disable(clk->parent); 333 if (clk->clkdm) 334 omap2_clkdm_clk_disable(clk->clkdm, clk); 335 336 } 337 } 338 339 int omap2_clk_enable(struct clk *clk) 340 { 341 int ret = 0; 342 343 if (clk->usecount++ == 0) { 344 if (clk->parent) 345 ret = omap2_clk_enable(clk->parent); 346 347 if (ret != 0) { 348 clk->usecount--; 349 return ret; 350 } 351 352 if (clk->clkdm) 353 omap2_clkdm_clk_enable(clk->clkdm, clk); 354 355 ret = _omap2_clk_enable(clk); 356 357 if (ret != 0) { 358 if (clk->clkdm) 359 omap2_clkdm_clk_disable(clk->clkdm, clk); 360 361 if (clk->parent) { 362 omap2_clk_disable(clk->parent); 363 clk->usecount--; 364 } 365 } 366 } 367 368 return ret; 369 } 370 371 /* 372 * Used for clocks that are part of CLKSEL_xyz governed clocks. 373 * REVISIT: Maybe change to use clk->enable() functions like on omap1? 374 */ 375 void omap2_clksel_recalc(struct clk *clk) 376 { 377 u32 div = 0; 378 379 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name); 380 381 div = omap2_clksel_get_divisor(clk); 382 if (div == 0) 383 return; 384 385 if (clk->rate == (clk->parent->rate / div)) 386 return; 387 clk->rate = clk->parent->rate / div; 388 389 pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div); 390 } 391 392 /** 393 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent 394 * @clk: OMAP struct clk ptr to inspect 395 * @src_clk: OMAP struct clk ptr of the parent clk to search for 396 * 397 * Scan the struct clksel array associated with the clock to find 398 * the element associated with the supplied parent clock address. 399 * Returns a pointer to the struct clksel on success or NULL on error. 400 */ 401 static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk, 402 struct clk *src_clk) 403 { 404 const struct clksel *clks; 405 406 if (!clk->clksel) 407 return NULL; 408 409 for (clks = clk->clksel; clks->parent; clks++) { 410 if (clks->parent == src_clk) 411 break; /* Found the requested parent */ 412 } 413 414 if (!clks->parent) { 415 printk(KERN_ERR "clock: Could not find parent clock %s in " 416 "clksel array of clock %s\n", src_clk->name, 417 clk->name); 418 return NULL; 419 } 420 421 return clks; 422 } 423 424 /** 425 * omap2_clksel_round_rate_div - find divisor for the given clock and rate 426 * @clk: OMAP struct clk to use 427 * @target_rate: desired clock rate 428 * @new_div: ptr to where we should store the divisor 429 * 430 * Finds 'best' divider value in an array based on the source and target 431 * rates. The divider array must be sorted with smallest divider first. 432 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, 433 * they are only settable as part of virtual_prcm set. 434 * 435 * Returns the rounded clock rate or returns 0xffffffff on error. 436 */ 437 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, 438 u32 *new_div) 439 { 440 unsigned long test_rate; 441 const struct clksel *clks; 442 const struct clksel_rate *clkr; 443 u32 last_div = 0; 444 445 printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n", 446 clk->name, target_rate); 447 448 *new_div = 1; 449 450 clks = omap2_get_clksel_by_parent(clk, clk->parent); 451 if (!clks) 452 return ~0; 453 454 for (clkr = clks->rates; clkr->div; clkr++) { 455 if (!(clkr->flags & cpu_mask)) 456 continue; 457 458 /* Sanity check */ 459 if (clkr->div <= last_div) 460 printk(KERN_ERR "clock: clksel_rate table not sorted " 461 "for clock %s", clk->name); 462 463 last_div = clkr->div; 464 465 test_rate = clk->parent->rate / clkr->div; 466 467 if (test_rate <= target_rate) 468 break; /* found it */ 469 } 470 471 if (!clkr->div) { 472 printk(KERN_ERR "clock: Could not find divisor for target " 473 "rate %ld for clock %s parent %s\n", target_rate, 474 clk->name, clk->parent->name); 475 return ~0; 476 } 477 478 *new_div = clkr->div; 479 480 printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div, 481 (clk->parent->rate / clkr->div)); 482 483 return (clk->parent->rate / clkr->div); 484 } 485 486 /** 487 * omap2_clksel_round_rate - find rounded rate for the given clock and rate 488 * @clk: OMAP struct clk to use 489 * @target_rate: desired clock rate 490 * 491 * Compatibility wrapper for OMAP clock framework 492 * Finds best target rate based on the source clock and possible dividers. 493 * rates. The divider array must be sorted with smallest divider first. 494 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, 495 * they are only settable as part of virtual_prcm set. 496 * 497 * Returns the rounded clock rate or returns 0xffffffff on error. 498 */ 499 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) 500 { 501 u32 new_div; 502 503 return omap2_clksel_round_rate_div(clk, target_rate, &new_div); 504 } 505 506 507 /* Given a clock and a rate apply a clock specific rounding function */ 508 long omap2_clk_round_rate(struct clk *clk, unsigned long rate) 509 { 510 if (clk->round_rate) 511 return clk->round_rate(clk, rate); 512 513 if (clk->flags & RATE_FIXED) 514 printk(KERN_ERR "clock: generic omap2_clk_round_rate called " 515 "on fixed-rate clock %s\n", clk->name); 516 517 return clk->rate; 518 } 519 520 /** 521 * omap2_clksel_to_divisor() - turn clksel field value into integer divider 522 * @clk: OMAP struct clk to use 523 * @field_val: register field value to find 524 * 525 * Given a struct clk of a rate-selectable clksel clock, and a register field 526 * value to search for, find the corresponding clock divisor. The register 527 * field value should be pre-masked and shifted down so the LSB is at bit 0 528 * before calling. Returns 0 on error 529 */ 530 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val) 531 { 532 const struct clksel *clks; 533 const struct clksel_rate *clkr; 534 535 clks = omap2_get_clksel_by_parent(clk, clk->parent); 536 if (!clks) 537 return 0; 538 539 for (clkr = clks->rates; clkr->div; clkr++) { 540 if ((clkr->flags & cpu_mask) && (clkr->val == field_val)) 541 break; 542 } 543 544 if (!clkr->div) { 545 printk(KERN_ERR "clock: Could not find fieldval %d for " 546 "clock %s parent %s\n", field_val, clk->name, 547 clk->parent->name); 548 return 0; 549 } 550 551 return clkr->div; 552 } 553 554 /** 555 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value 556 * @clk: OMAP struct clk to use 557 * @div: integer divisor to search for 558 * 559 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor, 560 * find the corresponding register field value. The return register value is 561 * the value before left-shifting. Returns 0xffffffff on error 562 */ 563 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div) 564 { 565 const struct clksel *clks; 566 const struct clksel_rate *clkr; 567 568 /* should never happen */ 569 WARN_ON(div == 0); 570 571 clks = omap2_get_clksel_by_parent(clk, clk->parent); 572 if (!clks) 573 return 0; 574 575 for (clkr = clks->rates; clkr->div; clkr++) { 576 if ((clkr->flags & cpu_mask) && (clkr->div == div)) 577 break; 578 } 579 580 if (!clkr->div) { 581 printk(KERN_ERR "clock: Could not find divisor %d for " 582 "clock %s parent %s\n", div, clk->name, 583 clk->parent->name); 584 return 0; 585 } 586 587 return clkr->val; 588 } 589 590 /** 591 * omap2_get_clksel - find clksel register addr & field mask for a clk 592 * @clk: struct clk to use 593 * @field_mask: ptr to u32 to store the register field mask 594 * 595 * Returns the address of the clksel register upon success or NULL on error. 596 */ 597 static void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask) 598 { 599 if (!clk->clksel_reg || (clk->clksel_mask == 0)) 600 return NULL; 601 602 *field_mask = clk->clksel_mask; 603 604 return clk->clksel_reg; 605 } 606 607 /** 608 * omap2_clksel_get_divisor - get current divider applied to parent clock. 609 * @clk: OMAP struct clk to use. 610 * 611 * Returns the integer divisor upon success or 0 on error. 612 */ 613 u32 omap2_clksel_get_divisor(struct clk *clk) 614 { 615 u32 field_mask, field_val; 616 void __iomem *div_addr; 617 618 div_addr = omap2_get_clksel(clk, &field_mask); 619 if (!div_addr) 620 return 0; 621 622 field_val = __raw_readl(div_addr) & field_mask; 623 field_val >>= __ffs(field_mask); 624 625 return omap2_clksel_to_divisor(clk, field_val); 626 } 627 628 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) 629 { 630 u32 field_mask, field_val, reg_val, validrate, new_div = 0; 631 void __iomem *div_addr; 632 633 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); 634 if (validrate != rate) 635 return -EINVAL; 636 637 div_addr = omap2_get_clksel(clk, &field_mask); 638 if (!div_addr) 639 return -EINVAL; 640 641 field_val = omap2_divisor_to_clksel(clk, new_div); 642 if (field_val == ~0) 643 return -EINVAL; 644 645 reg_val = __raw_readl(div_addr); 646 reg_val &= ~field_mask; 647 reg_val |= (field_val << __ffs(field_mask)); 648 __raw_writel(reg_val, div_addr); 649 wmb(); 650 651 clk->rate = clk->parent->rate / new_div; 652 653 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) { 654 prm_write_mod_reg(OMAP24XX_VALID_CONFIG, 655 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET); 656 wmb(); 657 } 658 659 return 0; 660 } 661 662 663 /* Set the clock rate for a clock source */ 664 int omap2_clk_set_rate(struct clk *clk, unsigned long rate) 665 { 666 int ret = -EINVAL; 667 668 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate); 669 670 /* CONFIG_PARTICIPANT clocks are changed only in sets via the 671 rate table mechanism, driven by mpu_speed */ 672 if (clk->flags & CONFIG_PARTICIPANT) 673 return -EINVAL; 674 675 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ 676 if (clk->set_rate) 677 ret = clk->set_rate(clk, rate); 678 679 return ret; 680 } 681 682 /* 683 * Converts encoded control register address into a full address 684 * On error, *src_addr will be returned as 0. 685 */ 686 static u32 omap2_clksel_get_src_field(void __iomem **src_addr, 687 struct clk *src_clk, u32 *field_mask, 688 struct clk *clk, u32 *parent_div) 689 { 690 const struct clksel *clks; 691 const struct clksel_rate *clkr; 692 693 *parent_div = 0; 694 *src_addr = NULL; 695 696 clks = omap2_get_clksel_by_parent(clk, src_clk); 697 if (!clks) 698 return 0; 699 700 for (clkr = clks->rates; clkr->div; clkr++) { 701 if (clkr->flags & (cpu_mask | DEFAULT_RATE)) 702 break; /* Found the default rate for this platform */ 703 } 704 705 if (!clkr->div) { 706 printk(KERN_ERR "clock: Could not find default rate for " 707 "clock %s parent %s\n", clk->name, 708 src_clk->parent->name); 709 return 0; 710 } 711 712 /* Should never happen. Add a clksel mask to the struct clk. */ 713 WARN_ON(clk->clksel_mask == 0); 714 715 *field_mask = clk->clksel_mask; 716 *src_addr = clk->clksel_reg; 717 *parent_div = clkr->div; 718 719 return clkr->val; 720 } 721 722 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) 723 { 724 void __iomem *src_addr; 725 u32 field_val, field_mask, reg_val, parent_div; 726 727 if (clk->flags & CONFIG_PARTICIPANT) 728 return -EINVAL; 729 730 if (!clk->clksel) 731 return -EINVAL; 732 733 field_val = omap2_clksel_get_src_field(&src_addr, new_parent, 734 &field_mask, clk, &parent_div); 735 if (!src_addr) 736 return -EINVAL; 737 738 if (clk->usecount > 0) 739 _omap2_clk_disable(clk); 740 741 /* Set new source value (previous dividers if any in effect) */ 742 reg_val = __raw_readl(src_addr) & ~field_mask; 743 reg_val |= (field_val << __ffs(field_mask)); 744 __raw_writel(reg_val, src_addr); 745 wmb(); 746 747 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) { 748 __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL); 749 wmb(); 750 } 751 752 if (clk->usecount > 0) 753 _omap2_clk_enable(clk); 754 755 clk->parent = new_parent; 756 757 /* CLKSEL clocks follow their parents' rates, divided by a divisor */ 758 clk->rate = new_parent->rate; 759 760 if (parent_div > 0) 761 clk->rate /= parent_div; 762 763 pr_debug("clock: set parent of %s to %s (new rate %ld)\n", 764 clk->name, clk->parent->name, clk->rate); 765 766 return 0; 767 } 768 769 /* DPLL rate rounding code */ 770 771 /** 772 * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding 773 * @clk: struct clk * of the DPLL 774 * @tolerance: maximum rate error tolerance 775 * 776 * Set the maximum DPLL rate error tolerance for the rate rounding 777 * algorithm. The rate tolerance is an attempt to balance DPLL power 778 * saving (the least divider value "n") vs. rate fidelity (the least 779 * difference between the desired DPLL target rate and the rounded 780 * rate out of the algorithm). So, increasing the tolerance is likely 781 * to decrease DPLL power consumption and increase DPLL rate error. 782 * Returns -EINVAL if provided a null clock ptr or a clk that is not a 783 * DPLL; or 0 upon success. 784 */ 785 int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance) 786 { 787 if (!clk || !clk->dpll_data) 788 return -EINVAL; 789 790 clk->dpll_data->rate_tolerance = tolerance; 791 792 return 0; 793 } 794 795 static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, 796 unsigned int m, unsigned int n) 797 { 798 unsigned long long num; 799 800 num = (unsigned long long)parent_rate * m; 801 do_div(num, n); 802 return num; 803 } 804 805 /* 806 * _dpll_test_mult - test a DPLL multiplier value 807 * @m: pointer to the DPLL m (multiplier) value under test 808 * @n: current DPLL n (divider) value under test 809 * @new_rate: pointer to storage for the resulting rounded rate 810 * @target_rate: the desired DPLL rate 811 * @parent_rate: the DPLL's parent clock rate 812 * 813 * This code tests a DPLL multiplier value, ensuring that the 814 * resulting rate will not be higher than the target_rate, and that 815 * the multiplier value itself is valid for the DPLL. Initially, the 816 * integer pointed to by the m argument should be prescaled by 817 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with 818 * a non-scaled m upon return. This non-scaled m will result in a 819 * new_rate as close as possible to target_rate (but not greater than 820 * target_rate) given the current (parent_rate, n, prescaled m) 821 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the 822 * non-scaled m attempted to underflow, which can allow the calling 823 * function to bail out early; or 0 upon success. 824 */ 825 static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, 826 unsigned long target_rate, 827 unsigned long parent_rate) 828 { 829 int flags = 0, carry = 0; 830 831 /* Unscale m and round if necessary */ 832 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL) 833 carry = 1; 834 *m = (*m / DPLL_SCALE_FACTOR) + carry; 835 836 /* 837 * The new rate must be <= the target rate to avoid programming 838 * a rate that is impossible for the hardware to handle 839 */ 840 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); 841 if (*new_rate > target_rate) { 842 (*m)--; 843 *new_rate = 0; 844 } 845 846 /* Guard against m underflow */ 847 if (*m < DPLL_MIN_MULTIPLIER) { 848 *m = DPLL_MIN_MULTIPLIER; 849 *new_rate = 0; 850 flags = DPLL_MULT_UNDERFLOW; 851 } 852 853 if (*new_rate == 0) 854 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); 855 856 return flags; 857 } 858 859 /** 860 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL 861 * @clk: struct clk * for a DPLL 862 * @target_rate: desired DPLL clock rate 863 * 864 * Given a DPLL, a desired target rate, and a rate tolerance, round 865 * the target rate to a possible, programmable rate for this DPLL. 866 * Rate tolerance is assumed to be set by the caller before this 867 * function is called. Attempts to select the minimum possible n 868 * within the tolerance to reduce power consumption. Stores the 869 * computed (m, n) in the DPLL's dpll_data structure so set_rate() 870 * will not need to call this (expensive) function again. Returns ~0 871 * if the target rate cannot be rounded, either because the rate is 872 * too low or because the rate tolerance is set too tightly; or the 873 * rounded rate upon success. 874 */ 875 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) 876 { 877 int m, n, r, e, scaled_max_m; 878 unsigned long scaled_rt_rp, new_rate; 879 int min_e = -1, min_e_m = -1, min_e_n = -1; 880 struct dpll_data *dd; 881 882 if (!clk || !clk->dpll_data) 883 return ~0; 884 885 dd = clk->dpll_data; 886 887 pr_debug("clock: starting DPLL round_rate for clock %s, target rate " 888 "%ld\n", clk->name, target_rate); 889 890 scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR); 891 scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR; 892 893 dd->last_rounded_rate = 0; 894 895 for (n = dd->max_divider; n >= DPLL_MIN_DIVIDER; n--) { 896 897 /* Compute the scaled DPLL multiplier, based on the divider */ 898 m = scaled_rt_rp * n; 899 900 /* 901 * Since we're counting n down, a m overflow means we can 902 * can immediately skip to the next n 903 */ 904 if (m > scaled_max_m) 905 continue; 906 907 r = _dpll_test_mult(&m, n, &new_rate, target_rate, 908 clk->parent->rate); 909 910 e = target_rate - new_rate; 911 pr_debug("clock: n = %d: m = %d: rate error is %d " 912 "(new_rate = %ld)\n", n, m, e, new_rate); 913 914 if (min_e == -1 || 915 min_e >= (int)(abs(e) - dd->rate_tolerance)) { 916 min_e = e; 917 min_e_m = m; 918 min_e_n = n; 919 920 pr_debug("clock: found new least error %d\n", min_e); 921 } 922 923 /* 924 * Since we're counting n down, a m underflow means we 925 * can bail out completely (since as n decreases in 926 * the next iteration, there's no way that m can 927 * increase beyond the current m) 928 */ 929 if (r & DPLL_MULT_UNDERFLOW) 930 break; 931 } 932 933 if (min_e < 0) { 934 pr_debug("clock: error: target rate or tolerance too low\n"); 935 return ~0; 936 } 937 938 dd->last_rounded_m = min_e_m; 939 dd->last_rounded_n = min_e_n; 940 dd->last_rounded_rate = _dpll_compute_new_rate(clk->parent->rate, 941 min_e_m, min_e_n); 942 943 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n", 944 min_e, min_e_m, min_e_n); 945 pr_debug("clock: final rate: %ld (target rate: %ld)\n", 946 dd->last_rounded_rate, target_rate); 947 948 return dd->last_rounded_rate; 949 } 950 951 /*------------------------------------------------------------------------- 952 * Omap2 clock reset and init functions 953 *-------------------------------------------------------------------------*/ 954 955 #ifdef CONFIG_OMAP_RESET_CLOCKS 956 void omap2_clk_disable_unused(struct clk *clk) 957 { 958 u32 regval32, v; 959 960 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0; 961 962 regval32 = __raw_readl(clk->enable_reg); 963 if ((regval32 & (1 << clk->enable_bit)) == v) 964 return; 965 966 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name); 967 _omap2_clk_disable(clk); 968 } 969 #endif 970