1 /* 2 * linux/arch/arm/mach-omap2/clock.c 3 * 4 * Copyright (C) 2005-2008 Texas Instruments, Inc. 5 * Copyright (C) 2004-2010 Nokia Corporation 6 * 7 * Contacts: 8 * Richard Woodruff <r-woodruff2@ti.com> 9 * Paul Walmsley 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 #undef DEBUG 16 17 #include <linux/kernel.h> 18 #include <linux/export.h> 19 #include <linux/list.h> 20 #include <linux/errno.h> 21 #include <linux/err.h> 22 #include <linux/delay.h> 23 #include <linux/clk-provider.h> 24 #include <linux/io.h> 25 #include <linux/bitops.h> 26 #include <linux/clk-private.h> 27 #include <asm/cpu.h> 28 29 #include <trace/events/power.h> 30 31 #include "soc.h" 32 #include "clockdomain.h" 33 #include "clock.h" 34 #include "cm.h" 35 #include "cm2xxx.h" 36 #include "cm3xxx.h" 37 #include "cm-regbits-24xx.h" 38 #include "cm-regbits-34xx.h" 39 #include "common.h" 40 41 /* 42 * MAX_MODULE_ENABLE_WAIT: maximum of number of microseconds to wait 43 * for a module to indicate that it is no longer in idle 44 */ 45 #define MAX_MODULE_ENABLE_WAIT 100000 46 47 u16 cpu_mask; 48 49 /* 50 * clkdm_control: if true, then when a clock is enabled in the 51 * hardware, its clockdomain will first be enabled; and when a clock 52 * is disabled in the hardware, its clockdomain will be disabled 53 * afterwards. 54 */ 55 static bool clkdm_control = true; 56 57 static LIST_HEAD(clk_hw_omap_clocks); 58 void __iomem *clk_memmaps[CLK_MAX_MEMMAPS]; 59 60 void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg) 61 { 62 if (clk->flags & MEMMAP_ADDRESSING) { 63 struct clk_omap_reg *r = (struct clk_omap_reg *)® 64 writel_relaxed(val, clk_memmaps[r->index] + r->offset); 65 } else { 66 writel_relaxed(val, reg); 67 } 68 } 69 70 u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg) 71 { 72 u32 val; 73 74 if (clk->flags & MEMMAP_ADDRESSING) { 75 struct clk_omap_reg *r = (struct clk_omap_reg *)® 76 val = readl_relaxed(clk_memmaps[r->index] + r->offset); 77 } else { 78 val = readl_relaxed(reg); 79 } 80 81 return val; 82 } 83 84 /* 85 * OMAP2+ specific clock functions 86 */ 87 88 /* Private functions */ 89 90 91 /** 92 * _wait_idlest_generic - wait for a module to leave the idle state 93 * @clk: module clock to wait for (needed for register offsets) 94 * @reg: virtual address of module IDLEST register 95 * @mask: value to mask against to determine if the module is active 96 * @idlest: idle state indicator (0 or 1) for the clock 97 * @name: name of the clock (for printk) 98 * 99 * Wait for a module to leave idle, where its idle-status register is 100 * not inside the CM module. Returns 1 if the module left idle 101 * promptly, or 0 if the module did not leave idle before the timeout 102 * elapsed. XXX Deprecated - should be moved into drivers for the 103 * individual IP block that the IDLEST register exists in. 104 */ 105 static int _wait_idlest_generic(struct clk_hw_omap *clk, void __iomem *reg, 106 u32 mask, u8 idlest, const char *name) 107 { 108 int i = 0, ena = 0; 109 110 ena = (idlest) ? 0 : mask; 111 112 omap_test_timeout(((omap2_clk_readl(clk, reg) & mask) == ena), 113 MAX_MODULE_ENABLE_WAIT, i); 114 115 if (i < MAX_MODULE_ENABLE_WAIT) 116 pr_debug("omap clock: module associated with clock %s ready after %d loops\n", 117 name, i); 118 else 119 pr_err("omap clock: module associated with clock %s didn't enable in %d tries\n", 120 name, MAX_MODULE_ENABLE_WAIT); 121 122 return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0; 123 }; 124 125 /** 126 * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE 127 * @clk: struct clk * belonging to the module 128 * 129 * If the necessary clocks for the OMAP hardware IP block that 130 * corresponds to clock @clk are enabled, then wait for the module to 131 * indicate readiness (i.e., to leave IDLE). This code does not 132 * belong in the clock code and will be moved in the medium term to 133 * module-dependent code. No return value. 134 */ 135 static void _omap2_module_wait_ready(struct clk_hw_omap *clk) 136 { 137 void __iomem *companion_reg, *idlest_reg; 138 u8 other_bit, idlest_bit, idlest_val, idlest_reg_id; 139 s16 prcm_mod; 140 int r; 141 142 /* Not all modules have multiple clocks that their IDLEST depends on */ 143 if (clk->ops->find_companion) { 144 clk->ops->find_companion(clk, &companion_reg, &other_bit); 145 if (!(omap2_clk_readl(clk, companion_reg) & (1 << other_bit))) 146 return; 147 } 148 149 clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); 150 r = cm_split_idlest_reg(idlest_reg, &prcm_mod, &idlest_reg_id); 151 if (r) { 152 /* IDLEST register not in the CM module */ 153 _wait_idlest_generic(clk, idlest_reg, (1 << idlest_bit), 154 idlest_val, __clk_get_name(clk->hw.clk)); 155 } else { 156 cm_wait_module_ready(prcm_mod, idlest_reg_id, idlest_bit); 157 }; 158 } 159 160 /* Public functions */ 161 162 /** 163 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk 164 * @clk: OMAP clock struct ptr to use 165 * 166 * Convert a clockdomain name stored in a struct clk 'clk' into a 167 * clockdomain pointer, and save it into the struct clk. Intended to be 168 * called during clk_register(). No return value. 169 */ 170 void omap2_init_clk_clkdm(struct clk_hw *hw) 171 { 172 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 173 struct clockdomain *clkdm; 174 const char *clk_name; 175 176 if (!clk->clkdm_name) 177 return; 178 179 clk_name = __clk_get_name(hw->clk); 180 181 clkdm = clkdm_lookup(clk->clkdm_name); 182 if (clkdm) { 183 pr_debug("clock: associated clk %s to clkdm %s\n", 184 clk_name, clk->clkdm_name); 185 clk->clkdm = clkdm; 186 } else { 187 pr_debug("clock: could not associate clk %s to clkdm %s\n", 188 clk_name, clk->clkdm_name); 189 } 190 } 191 192 /** 193 * omap2_clk_disable_clkdm_control - disable clkdm control on clk enable/disable 194 * 195 * Prevent the OMAP clock code from calling into the clockdomain code 196 * when a hardware clock in that clockdomain is enabled or disabled. 197 * Intended to be called at init time from omap*_clk_init(). No 198 * return value. 199 */ 200 void __init omap2_clk_disable_clkdm_control(void) 201 { 202 clkdm_control = false; 203 } 204 205 /** 206 * omap2_clk_dflt_find_companion - find companion clock to @clk 207 * @clk: struct clk * to find the companion clock of 208 * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in 209 * @other_bit: u8 ** to return the companion clock bit shift in 210 * 211 * Note: We don't need special code here for INVERT_ENABLE for the 212 * time being since INVERT_ENABLE only applies to clocks enabled by 213 * CM_CLKEN_PLL 214 * 215 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's 216 * just a matter of XORing the bits. 217 * 218 * Some clocks don't have companion clocks. For example, modules with 219 * only an interface clock (such as MAILBOXES) don't have a companion 220 * clock. Right now, this code relies on the hardware exporting a bit 221 * in the correct companion register that indicates that the 222 * nonexistent 'companion clock' is active. Future patches will 223 * associate this type of code with per-module data structures to 224 * avoid this issue, and remove the casts. No return value. 225 */ 226 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, 227 void __iomem **other_reg, u8 *other_bit) 228 { 229 u32 r; 230 231 /* 232 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes 233 * it's just a matter of XORing the bits. 234 */ 235 r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN)); 236 237 *other_reg = (__force void __iomem *)r; 238 *other_bit = clk->enable_bit; 239 } 240 241 /** 242 * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk 243 * @clk: struct clk * to find IDLEST info for 244 * @idlest_reg: void __iomem ** to return the CM_IDLEST va in 245 * @idlest_bit: u8 * to return the CM_IDLEST bit shift in 246 * @idlest_val: u8 * to return the idle status indicator 247 * 248 * Return the CM_IDLEST register address and bit shift corresponding 249 * to the module that "owns" this clock. This default code assumes 250 * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that 251 * the IDLEST register address ID corresponds to the CM_*CLKEN 252 * register address ID (e.g., that CM_FCLKEN2 corresponds to 253 * CM_IDLEST2). This is not true for all modules. No return value. 254 */ 255 void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, 256 void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) 257 { 258 u32 r; 259 260 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); 261 *idlest_reg = (__force void __iomem *)r; 262 *idlest_bit = clk->enable_bit; 263 264 /* 265 * 24xx uses 0 to indicate not ready, and 1 to indicate ready. 266 * 34xx reverses this, just to keep us on our toes 267 * AM35xx uses both, depending on the module. 268 */ 269 if (cpu_is_omap24xx()) 270 *idlest_val = OMAP24XX_CM_IDLEST_VAL; 271 else if (cpu_is_omap34xx()) 272 *idlest_val = OMAP34XX_CM_IDLEST_VAL; 273 else 274 BUG(); 275 276 } 277 278 /** 279 * omap2_dflt_clk_enable - enable a clock in the hardware 280 * @hw: struct clk_hw * of the clock to enable 281 * 282 * Enable the clock @hw in the hardware. We first call into the OMAP 283 * clockdomain code to "enable" the corresponding clockdomain if this 284 * is the first enabled user of the clockdomain. Then program the 285 * hardware to enable the clock. Then wait for the IP block that uses 286 * this clock to leave idle (if applicable). Returns the error value 287 * from clkdm_clk_enable() if it terminated with an error, or -EINVAL 288 * if @hw has a null clock enable_reg, or zero upon success. 289 */ 290 int omap2_dflt_clk_enable(struct clk_hw *hw) 291 { 292 struct clk_hw_omap *clk; 293 u32 v; 294 int ret = 0; 295 296 clk = to_clk_hw_omap(hw); 297 298 if (clkdm_control && clk->clkdm) { 299 ret = clkdm_clk_enable(clk->clkdm, hw->clk); 300 if (ret) { 301 WARN(1, "%s: could not enable %s's clockdomain %s: %d\n", 302 __func__, __clk_get_name(hw->clk), 303 clk->clkdm->name, ret); 304 return ret; 305 } 306 } 307 308 if (unlikely(clk->enable_reg == NULL)) { 309 pr_err("%s: %s missing enable_reg\n", __func__, 310 __clk_get_name(hw->clk)); 311 ret = -EINVAL; 312 goto err; 313 } 314 315 /* FIXME should not have INVERT_ENABLE bit here */ 316 v = omap2_clk_readl(clk, clk->enable_reg); 317 if (clk->flags & INVERT_ENABLE) 318 v &= ~(1 << clk->enable_bit); 319 else 320 v |= (1 << clk->enable_bit); 321 omap2_clk_writel(v, clk, clk->enable_reg); 322 v = omap2_clk_readl(clk, clk->enable_reg); /* OCP barrier */ 323 324 if (clk->ops && clk->ops->find_idlest) 325 _omap2_module_wait_ready(clk); 326 327 return 0; 328 329 err: 330 if (clkdm_control && clk->clkdm) 331 clkdm_clk_disable(clk->clkdm, hw->clk); 332 return ret; 333 } 334 335 /** 336 * omap2_dflt_clk_disable - disable a clock in the hardware 337 * @hw: struct clk_hw * of the clock to disable 338 * 339 * Disable the clock @hw in the hardware, and call into the OMAP 340 * clockdomain code to "disable" the corresponding clockdomain if all 341 * clocks/hwmods in that clockdomain are now disabled. No return 342 * value. 343 */ 344 void omap2_dflt_clk_disable(struct clk_hw *hw) 345 { 346 struct clk_hw_omap *clk; 347 u32 v; 348 349 clk = to_clk_hw_omap(hw); 350 if (!clk->enable_reg) { 351 /* 352 * 'independent' here refers to a clock which is not 353 * controlled by its parent. 354 */ 355 pr_err("%s: independent clock %s has no enable_reg\n", 356 __func__, __clk_get_name(hw->clk)); 357 return; 358 } 359 360 v = omap2_clk_readl(clk, clk->enable_reg); 361 if (clk->flags & INVERT_ENABLE) 362 v |= (1 << clk->enable_bit); 363 else 364 v &= ~(1 << clk->enable_bit); 365 omap2_clk_writel(v, clk, clk->enable_reg); 366 /* No OCP barrier needed here since it is a disable operation */ 367 368 if (clkdm_control && clk->clkdm) 369 clkdm_clk_disable(clk->clkdm, hw->clk); 370 } 371 372 /** 373 * omap2_clkops_enable_clkdm - increment usecount on clkdm of @hw 374 * @hw: struct clk_hw * of the clock being enabled 375 * 376 * Increment the usecount of the clockdomain of the clock pointed to 377 * by @hw; if the usecount is 1, the clockdomain will be "enabled." 378 * Only needed for clocks that don't use omap2_dflt_clk_enable() as 379 * their enable function pointer. Passes along the return value of 380 * clkdm_clk_enable(), -EINVAL if @hw is not associated with a 381 * clockdomain, or 0 if clock framework-based clockdomain control is 382 * not implemented. 383 */ 384 int omap2_clkops_enable_clkdm(struct clk_hw *hw) 385 { 386 struct clk_hw_omap *clk; 387 int ret = 0; 388 389 clk = to_clk_hw_omap(hw); 390 391 if (unlikely(!clk->clkdm)) { 392 pr_err("%s: %s: no clkdm set ?!\n", __func__, 393 __clk_get_name(hw->clk)); 394 return -EINVAL; 395 } 396 397 if (unlikely(clk->enable_reg)) 398 pr_err("%s: %s: should use dflt_clk_enable ?!\n", __func__, 399 __clk_get_name(hw->clk)); 400 401 if (!clkdm_control) { 402 pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", 403 __func__, __clk_get_name(hw->clk)); 404 return 0; 405 } 406 407 ret = clkdm_clk_enable(clk->clkdm, hw->clk); 408 WARN(ret, "%s: could not enable %s's clockdomain %s: %d\n", 409 __func__, __clk_get_name(hw->clk), clk->clkdm->name, ret); 410 411 return ret; 412 } 413 414 /** 415 * omap2_clkops_disable_clkdm - decrement usecount on clkdm of @hw 416 * @hw: struct clk_hw * of the clock being disabled 417 * 418 * Decrement the usecount of the clockdomain of the clock pointed to 419 * by @hw; if the usecount is 0, the clockdomain will be "disabled." 420 * Only needed for clocks that don't use omap2_dflt_clk_disable() as their 421 * disable function pointer. No return value. 422 */ 423 void omap2_clkops_disable_clkdm(struct clk_hw *hw) 424 { 425 struct clk_hw_omap *clk; 426 427 clk = to_clk_hw_omap(hw); 428 429 if (unlikely(!clk->clkdm)) { 430 pr_err("%s: %s: no clkdm set ?!\n", __func__, 431 __clk_get_name(hw->clk)); 432 return; 433 } 434 435 if (unlikely(clk->enable_reg)) 436 pr_err("%s: %s: should use dflt_clk_disable ?!\n", __func__, 437 __clk_get_name(hw->clk)); 438 439 if (!clkdm_control) { 440 pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", 441 __func__, __clk_get_name(hw->clk)); 442 return; 443 } 444 445 clkdm_clk_disable(clk->clkdm, hw->clk); 446 } 447 448 /** 449 * omap2_dflt_clk_is_enabled - is clock enabled in the hardware? 450 * @hw: struct clk_hw * to check 451 * 452 * Return 1 if the clock represented by @hw is enabled in the 453 * hardware, or 0 otherwise. Intended for use in the struct 454 * clk_ops.is_enabled function pointer. 455 */ 456 int omap2_dflt_clk_is_enabled(struct clk_hw *hw) 457 { 458 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 459 u32 v; 460 461 v = omap2_clk_readl(clk, clk->enable_reg); 462 463 if (clk->flags & INVERT_ENABLE) 464 v ^= BIT(clk->enable_bit); 465 466 v &= BIT(clk->enable_bit); 467 468 return v ? 1 : 0; 469 } 470 471 static int __initdata mpurate; 472 473 /* 474 * By default we use the rate set by the bootloader. 475 * You can override this with mpurate= cmdline option. 476 */ 477 static int __init omap_clk_setup(char *str) 478 { 479 get_option(&str, &mpurate); 480 481 if (!mpurate) 482 return 1; 483 484 if (mpurate < 1000) 485 mpurate *= 1000000; 486 487 return 1; 488 } 489 __setup("mpurate=", omap_clk_setup); 490 491 /** 492 * omap2_init_clk_hw_omap_clocks - initialize an OMAP clock 493 * @clk: struct clk * to initialize 494 * 495 * Add an OMAP clock @clk to the internal list of OMAP clocks. Used 496 * temporarily for autoidle handling, until this support can be 497 * integrated into the common clock framework code in some way. No 498 * return value. 499 */ 500 void omap2_init_clk_hw_omap_clocks(struct clk *clk) 501 { 502 struct clk_hw_omap *c; 503 504 if (__clk_get_flags(clk) & CLK_IS_BASIC) 505 return; 506 507 c = to_clk_hw_omap(__clk_get_hw(clk)); 508 list_add(&c->node, &clk_hw_omap_clocks); 509 } 510 511 /** 512 * omap2_clk_enable_autoidle_all - enable autoidle on all OMAP clocks that 513 * support it 514 * 515 * Enable clock autoidle on all OMAP clocks that have allow_idle 516 * function pointers associated with them. This function is intended 517 * to be temporary until support for this is added to the common clock 518 * code. Returns 0. 519 */ 520 int omap2_clk_enable_autoidle_all(void) 521 { 522 struct clk_hw_omap *c; 523 524 list_for_each_entry(c, &clk_hw_omap_clocks, node) 525 if (c->ops && c->ops->allow_idle) 526 c->ops->allow_idle(c); 527 528 of_ti_clk_allow_autoidle_all(); 529 530 return 0; 531 } 532 533 /** 534 * omap2_clk_disable_autoidle_all - disable autoidle on all OMAP clocks that 535 * support it 536 * 537 * Disable clock autoidle on all OMAP clocks that have allow_idle 538 * function pointers associated with them. This function is intended 539 * to be temporary until support for this is added to the common clock 540 * code. Returns 0. 541 */ 542 int omap2_clk_disable_autoidle_all(void) 543 { 544 struct clk_hw_omap *c; 545 546 list_for_each_entry(c, &clk_hw_omap_clocks, node) 547 if (c->ops && c->ops->deny_idle) 548 c->ops->deny_idle(c); 549 550 of_ti_clk_deny_autoidle_all(); 551 552 return 0; 553 } 554 555 /** 556 * omap2_clk_deny_idle - disable autoidle on an OMAP clock 557 * @clk: struct clk * to disable autoidle for 558 * 559 * Disable autoidle on an OMAP clock. 560 */ 561 int omap2_clk_deny_idle(struct clk *clk) 562 { 563 struct clk_hw_omap *c; 564 565 if (__clk_get_flags(clk) & CLK_IS_BASIC) 566 return -EINVAL; 567 568 c = to_clk_hw_omap(__clk_get_hw(clk)); 569 if (c->ops && c->ops->deny_idle) 570 c->ops->deny_idle(c); 571 return 0; 572 } 573 574 /** 575 * omap2_clk_allow_idle - enable autoidle on an OMAP clock 576 * @clk: struct clk * to enable autoidle for 577 * 578 * Enable autoidle on an OMAP clock. 579 */ 580 int omap2_clk_allow_idle(struct clk *clk) 581 { 582 struct clk_hw_omap *c; 583 584 if (__clk_get_flags(clk) & CLK_IS_BASIC) 585 return -EINVAL; 586 587 c = to_clk_hw_omap(__clk_get_hw(clk)); 588 if (c->ops && c->ops->allow_idle) 589 c->ops->allow_idle(c); 590 return 0; 591 } 592 593 /** 594 * omap2_clk_enable_init_clocks - prepare & enable a list of clocks 595 * @clk_names: ptr to an array of strings of clock names to enable 596 * @num_clocks: number of clock names in @clk_names 597 * 598 * Prepare and enable a list of clocks, named by @clk_names. No 599 * return value. XXX Deprecated; only needed until these clocks are 600 * properly claimed and enabled by the drivers or core code that uses 601 * them. XXX What code disables & calls clk_put on these clocks? 602 */ 603 void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks) 604 { 605 struct clk *init_clk; 606 int i; 607 608 for (i = 0; i < num_clocks; i++) { 609 init_clk = clk_get(NULL, clk_names[i]); 610 clk_prepare_enable(init_clk); 611 } 612 } 613 614 const struct clk_hw_omap_ops clkhwops_wait = { 615 .find_idlest = omap2_clk_dflt_find_idlest, 616 .find_companion = omap2_clk_dflt_find_companion, 617 }; 618 619 /** 620 * omap_clocks_register - register an array of omap_clk 621 * @ocs: pointer to an array of omap_clk to register 622 */ 623 void __init omap_clocks_register(struct omap_clk oclks[], int cnt) 624 { 625 struct omap_clk *c; 626 627 for (c = oclks; c < oclks + cnt; c++) { 628 clkdev_add(&c->lk); 629 if (!__clk_init(NULL, c->lk.clk)) 630 omap2_init_clk_hw_omap_clocks(c->lk.clk); 631 } 632 } 633 634 /** 635 * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument 636 * @mpurate_ck_name: clk name of the clock to change rate 637 * 638 * Change the ARM MPU clock rate to the rate specified on the command 639 * line, if one was specified. @mpurate_ck_name should be 640 * "virt_prcm_set" on OMAP2xxx and "dpll1_ck" on OMAP34xx/OMAP36xx. 641 * XXX Does not handle voltage scaling - on OMAP2xxx this is currently 642 * handled by the virt_prcm_set clock, but this should be handled by 643 * the OPP layer. XXX This is intended to be handled by the OPP layer 644 * code in the near future and should be removed from the clock code. 645 * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects 646 * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name 647 * cannot be found, or 0 upon success. 648 */ 649 int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name) 650 { 651 struct clk *mpurate_ck; 652 int r; 653 654 if (!mpurate) 655 return -EINVAL; 656 657 mpurate_ck = clk_get(NULL, mpurate_ck_name); 658 if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name)) 659 return -ENOENT; 660 661 r = clk_set_rate(mpurate_ck, mpurate); 662 if (r < 0) { 663 WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n", 664 mpurate_ck_name, mpurate, r); 665 clk_put(mpurate_ck); 666 return -EINVAL; 667 } 668 669 calibrate_delay(); 670 clk_put(mpurate_ck); 671 672 return 0; 673 } 674 675 /** 676 * omap2_clk_print_new_rates - print summary of current clock tree rates 677 * @hfclkin_ck_name: clk name for the off-chip HF oscillator 678 * @core_ck_name: clk name for the on-chip CORE_CLK 679 * @mpu_ck_name: clk name for the ARM MPU clock 680 * 681 * Prints a short message to the console with the HFCLKIN oscillator 682 * rate, the rate of the CORE clock, and the rate of the ARM MPU clock. 683 * Called by the boot-time MPU rate switching code. XXX This is intended 684 * to be handled by the OPP layer code in the near future and should be 685 * removed from the clock code. No return value. 686 */ 687 void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, 688 const char *core_ck_name, 689 const char *mpu_ck_name) 690 { 691 struct clk *hfclkin_ck, *core_ck, *mpu_ck; 692 unsigned long hfclkin_rate; 693 694 mpu_ck = clk_get(NULL, mpu_ck_name); 695 if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name)) 696 return; 697 698 core_ck = clk_get(NULL, core_ck_name); 699 if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name)) 700 return; 701 702 hfclkin_ck = clk_get(NULL, hfclkin_ck_name); 703 if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name)) 704 return; 705 706 hfclkin_rate = clk_get_rate(hfclkin_ck); 707 708 pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", 709 (hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10), 710 (clk_get_rate(core_ck) / 1000000), 711 (clk_get_rate(mpu_ck) / 1000000)); 712 } 713