1 /* 2 * linux/arch/arm/mach-omap2/clock.c 3 * 4 * Copyright (C) 2005-2008 Texas Instruments, Inc. 5 * Copyright (C) 2004-2010 Nokia Corporation 6 * 7 * Contacts: 8 * Richard Woodruff <r-woodruff2@ti.com> 9 * Paul Walmsley 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 #undef DEBUG 16 17 #include <linux/kernel.h> 18 #include <linux/export.h> 19 #include <linux/list.h> 20 #include <linux/errno.h> 21 #include <linux/err.h> 22 #include <linux/delay.h> 23 #include <linux/clk-provider.h> 24 #include <linux/io.h> 25 #include <linux/bitops.h> 26 #include <linux/clk-private.h> 27 #include <asm/cpu.h> 28 29 #include <trace/events/power.h> 30 31 #include "soc.h" 32 #include "clockdomain.h" 33 #include "clock.h" 34 #include "cm.h" 35 #include "cm2xxx.h" 36 #include "cm3xxx.h" 37 #include "cm-regbits-24xx.h" 38 #include "cm-regbits-34xx.h" 39 #include "common.h" 40 41 /* 42 * MAX_MODULE_ENABLE_WAIT: maximum of number of microseconds to wait 43 * for a module to indicate that it is no longer in idle 44 */ 45 #define MAX_MODULE_ENABLE_WAIT 100000 46 47 u16 cpu_mask; 48 49 /* 50 * Clock features setup. Used instead of CPU type checks. 51 */ 52 struct ti_clk_features ti_clk_features; 53 54 /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ 55 #define OMAP3430_DPLL_FINT_BAND1_MIN 750000 56 #define OMAP3430_DPLL_FINT_BAND1_MAX 2100000 57 #define OMAP3430_DPLL_FINT_BAND2_MIN 7500000 58 #define OMAP3430_DPLL_FINT_BAND2_MAX 21000000 59 60 /* 61 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx. 62 * From device data manual section 4.3 "DPLL and DLL Specifications". 63 */ 64 #define OMAP3PLUS_DPLL_FINT_MIN 32000 65 #define OMAP3PLUS_DPLL_FINT_MAX 52000000 66 67 /* 68 * clkdm_control: if true, then when a clock is enabled in the 69 * hardware, its clockdomain will first be enabled; and when a clock 70 * is disabled in the hardware, its clockdomain will be disabled 71 * afterwards. 72 */ 73 static bool clkdm_control = true; 74 75 static LIST_HEAD(clk_hw_omap_clocks); 76 void __iomem *clk_memmaps[CLK_MAX_MEMMAPS]; 77 78 void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg) 79 { 80 if (clk->flags & MEMMAP_ADDRESSING) { 81 struct clk_omap_reg *r = (struct clk_omap_reg *)® 82 writel_relaxed(val, clk_memmaps[r->index] + r->offset); 83 } else { 84 writel_relaxed(val, reg); 85 } 86 } 87 88 u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg) 89 { 90 u32 val; 91 92 if (clk->flags & MEMMAP_ADDRESSING) { 93 struct clk_omap_reg *r = (struct clk_omap_reg *)® 94 val = readl_relaxed(clk_memmaps[r->index] + r->offset); 95 } else { 96 val = readl_relaxed(reg); 97 } 98 99 return val; 100 } 101 102 /* 103 * Used for clocks that have the same value as the parent clock, 104 * divided by some factor 105 */ 106 unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, 107 unsigned long parent_rate) 108 { 109 struct clk_hw_omap *oclk; 110 111 if (!hw) { 112 pr_warn("%s: hw is NULL\n", __func__); 113 return -EINVAL; 114 } 115 116 oclk = to_clk_hw_omap(hw); 117 118 WARN_ON(!oclk->fixed_div); 119 120 return parent_rate / oclk->fixed_div; 121 } 122 123 /* 124 * OMAP2+ specific clock functions 125 */ 126 127 /* Private functions */ 128 129 130 /** 131 * _wait_idlest_generic - wait for a module to leave the idle state 132 * @clk: module clock to wait for (needed for register offsets) 133 * @reg: virtual address of module IDLEST register 134 * @mask: value to mask against to determine if the module is active 135 * @idlest: idle state indicator (0 or 1) for the clock 136 * @name: name of the clock (for printk) 137 * 138 * Wait for a module to leave idle, where its idle-status register is 139 * not inside the CM module. Returns 1 if the module left idle 140 * promptly, or 0 if the module did not leave idle before the timeout 141 * elapsed. XXX Deprecated - should be moved into drivers for the 142 * individual IP block that the IDLEST register exists in. 143 */ 144 static int _wait_idlest_generic(struct clk_hw_omap *clk, void __iomem *reg, 145 u32 mask, u8 idlest, const char *name) 146 { 147 int i = 0, ena = 0; 148 149 ena = (idlest) ? 0 : mask; 150 151 omap_test_timeout(((omap2_clk_readl(clk, reg) & mask) == ena), 152 MAX_MODULE_ENABLE_WAIT, i); 153 154 if (i < MAX_MODULE_ENABLE_WAIT) 155 pr_debug("omap clock: module associated with clock %s ready after %d loops\n", 156 name, i); 157 else 158 pr_err("omap clock: module associated with clock %s didn't enable in %d tries\n", 159 name, MAX_MODULE_ENABLE_WAIT); 160 161 return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0; 162 }; 163 164 /** 165 * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE 166 * @clk: struct clk * belonging to the module 167 * 168 * If the necessary clocks for the OMAP hardware IP block that 169 * corresponds to clock @clk are enabled, then wait for the module to 170 * indicate readiness (i.e., to leave IDLE). This code does not 171 * belong in the clock code and will be moved in the medium term to 172 * module-dependent code. No return value. 173 */ 174 static void _omap2_module_wait_ready(struct clk_hw_omap *clk) 175 { 176 void __iomem *companion_reg, *idlest_reg; 177 u8 other_bit, idlest_bit, idlest_val, idlest_reg_id; 178 s16 prcm_mod; 179 int r; 180 181 /* Not all modules have multiple clocks that their IDLEST depends on */ 182 if (clk->ops->find_companion) { 183 clk->ops->find_companion(clk, &companion_reg, &other_bit); 184 if (!(omap2_clk_readl(clk, companion_reg) & (1 << other_bit))) 185 return; 186 } 187 188 clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); 189 r = cm_split_idlest_reg(idlest_reg, &prcm_mod, &idlest_reg_id); 190 if (r) { 191 /* IDLEST register not in the CM module */ 192 _wait_idlest_generic(clk, idlest_reg, (1 << idlest_bit), 193 idlest_val, __clk_get_name(clk->hw.clk)); 194 } else { 195 cm_wait_module_ready(prcm_mod, idlest_reg_id, idlest_bit); 196 }; 197 } 198 199 /* Public functions */ 200 201 /** 202 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk 203 * @clk: OMAP clock struct ptr to use 204 * 205 * Convert a clockdomain name stored in a struct clk 'clk' into a 206 * clockdomain pointer, and save it into the struct clk. Intended to be 207 * called during clk_register(). No return value. 208 */ 209 void omap2_init_clk_clkdm(struct clk_hw *hw) 210 { 211 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 212 struct clockdomain *clkdm; 213 const char *clk_name; 214 215 if (!clk->clkdm_name) 216 return; 217 218 clk_name = __clk_get_name(hw->clk); 219 220 clkdm = clkdm_lookup(clk->clkdm_name); 221 if (clkdm) { 222 pr_debug("clock: associated clk %s to clkdm %s\n", 223 clk_name, clk->clkdm_name); 224 clk->clkdm = clkdm; 225 } else { 226 pr_debug("clock: could not associate clk %s to clkdm %s\n", 227 clk_name, clk->clkdm_name); 228 } 229 } 230 231 /** 232 * omap2_clk_disable_clkdm_control - disable clkdm control on clk enable/disable 233 * 234 * Prevent the OMAP clock code from calling into the clockdomain code 235 * when a hardware clock in that clockdomain is enabled or disabled. 236 * Intended to be called at init time from omap*_clk_init(). No 237 * return value. 238 */ 239 void __init omap2_clk_disable_clkdm_control(void) 240 { 241 clkdm_control = false; 242 } 243 244 /** 245 * omap2_clk_dflt_find_companion - find companion clock to @clk 246 * @clk: struct clk * to find the companion clock of 247 * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in 248 * @other_bit: u8 ** to return the companion clock bit shift in 249 * 250 * Note: We don't need special code here for INVERT_ENABLE for the 251 * time being since INVERT_ENABLE only applies to clocks enabled by 252 * CM_CLKEN_PLL 253 * 254 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's 255 * just a matter of XORing the bits. 256 * 257 * Some clocks don't have companion clocks. For example, modules with 258 * only an interface clock (such as MAILBOXES) don't have a companion 259 * clock. Right now, this code relies on the hardware exporting a bit 260 * in the correct companion register that indicates that the 261 * nonexistent 'companion clock' is active. Future patches will 262 * associate this type of code with per-module data structures to 263 * avoid this issue, and remove the casts. No return value. 264 */ 265 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, 266 void __iomem **other_reg, u8 *other_bit) 267 { 268 u32 r; 269 270 /* 271 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes 272 * it's just a matter of XORing the bits. 273 */ 274 r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN)); 275 276 *other_reg = (__force void __iomem *)r; 277 *other_bit = clk->enable_bit; 278 } 279 280 /** 281 * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk 282 * @clk: struct clk * to find IDLEST info for 283 * @idlest_reg: void __iomem ** to return the CM_IDLEST va in 284 * @idlest_bit: u8 * to return the CM_IDLEST bit shift in 285 * @idlest_val: u8 * to return the idle status indicator 286 * 287 * Return the CM_IDLEST register address and bit shift corresponding 288 * to the module that "owns" this clock. This default code assumes 289 * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that 290 * the IDLEST register address ID corresponds to the CM_*CLKEN 291 * register address ID (e.g., that CM_FCLKEN2 corresponds to 292 * CM_IDLEST2). This is not true for all modules. No return value. 293 */ 294 void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, 295 void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) 296 { 297 u32 r; 298 299 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); 300 *idlest_reg = (__force void __iomem *)r; 301 *idlest_bit = clk->enable_bit; 302 303 /* 304 * 24xx uses 0 to indicate not ready, and 1 to indicate ready. 305 * 34xx reverses this, just to keep us on our toes 306 * AM35xx uses both, depending on the module. 307 */ 308 if (cpu_is_omap24xx()) 309 *idlest_val = OMAP24XX_CM_IDLEST_VAL; 310 else if (cpu_is_omap34xx()) 311 *idlest_val = OMAP34XX_CM_IDLEST_VAL; 312 else 313 BUG(); 314 315 } 316 317 /** 318 * omap2_dflt_clk_enable - enable a clock in the hardware 319 * @hw: struct clk_hw * of the clock to enable 320 * 321 * Enable the clock @hw in the hardware. We first call into the OMAP 322 * clockdomain code to "enable" the corresponding clockdomain if this 323 * is the first enabled user of the clockdomain. Then program the 324 * hardware to enable the clock. Then wait for the IP block that uses 325 * this clock to leave idle (if applicable). Returns the error value 326 * from clkdm_clk_enable() if it terminated with an error, or -EINVAL 327 * if @hw has a null clock enable_reg, or zero upon success. 328 */ 329 int omap2_dflt_clk_enable(struct clk_hw *hw) 330 { 331 struct clk_hw_omap *clk; 332 u32 v; 333 int ret = 0; 334 335 clk = to_clk_hw_omap(hw); 336 337 if (clkdm_control && clk->clkdm) { 338 ret = clkdm_clk_enable(clk->clkdm, hw->clk); 339 if (ret) { 340 WARN(1, "%s: could not enable %s's clockdomain %s: %d\n", 341 __func__, __clk_get_name(hw->clk), 342 clk->clkdm->name, ret); 343 return ret; 344 } 345 } 346 347 if (unlikely(clk->enable_reg == NULL)) { 348 pr_err("%s: %s missing enable_reg\n", __func__, 349 __clk_get_name(hw->clk)); 350 ret = -EINVAL; 351 goto err; 352 } 353 354 /* FIXME should not have INVERT_ENABLE bit here */ 355 v = omap2_clk_readl(clk, clk->enable_reg); 356 if (clk->flags & INVERT_ENABLE) 357 v &= ~(1 << clk->enable_bit); 358 else 359 v |= (1 << clk->enable_bit); 360 omap2_clk_writel(v, clk, clk->enable_reg); 361 v = omap2_clk_readl(clk, clk->enable_reg); /* OCP barrier */ 362 363 if (clk->ops && clk->ops->find_idlest) 364 _omap2_module_wait_ready(clk); 365 366 return 0; 367 368 err: 369 if (clkdm_control && clk->clkdm) 370 clkdm_clk_disable(clk->clkdm, hw->clk); 371 return ret; 372 } 373 374 /** 375 * omap2_dflt_clk_disable - disable a clock in the hardware 376 * @hw: struct clk_hw * of the clock to disable 377 * 378 * Disable the clock @hw in the hardware, and call into the OMAP 379 * clockdomain code to "disable" the corresponding clockdomain if all 380 * clocks/hwmods in that clockdomain are now disabled. No return 381 * value. 382 */ 383 void omap2_dflt_clk_disable(struct clk_hw *hw) 384 { 385 struct clk_hw_omap *clk; 386 u32 v; 387 388 clk = to_clk_hw_omap(hw); 389 if (!clk->enable_reg) { 390 /* 391 * 'independent' here refers to a clock which is not 392 * controlled by its parent. 393 */ 394 pr_err("%s: independent clock %s has no enable_reg\n", 395 __func__, __clk_get_name(hw->clk)); 396 return; 397 } 398 399 v = omap2_clk_readl(clk, clk->enable_reg); 400 if (clk->flags & INVERT_ENABLE) 401 v |= (1 << clk->enable_bit); 402 else 403 v &= ~(1 << clk->enable_bit); 404 omap2_clk_writel(v, clk, clk->enable_reg); 405 /* No OCP barrier needed here since it is a disable operation */ 406 407 if (clkdm_control && clk->clkdm) 408 clkdm_clk_disable(clk->clkdm, hw->clk); 409 } 410 411 /** 412 * omap2_clkops_enable_clkdm - increment usecount on clkdm of @hw 413 * @hw: struct clk_hw * of the clock being enabled 414 * 415 * Increment the usecount of the clockdomain of the clock pointed to 416 * by @hw; if the usecount is 1, the clockdomain will be "enabled." 417 * Only needed for clocks that don't use omap2_dflt_clk_enable() as 418 * their enable function pointer. Passes along the return value of 419 * clkdm_clk_enable(), -EINVAL if @hw is not associated with a 420 * clockdomain, or 0 if clock framework-based clockdomain control is 421 * not implemented. 422 */ 423 int omap2_clkops_enable_clkdm(struct clk_hw *hw) 424 { 425 struct clk_hw_omap *clk; 426 int ret = 0; 427 428 clk = to_clk_hw_omap(hw); 429 430 if (unlikely(!clk->clkdm)) { 431 pr_err("%s: %s: no clkdm set ?!\n", __func__, 432 __clk_get_name(hw->clk)); 433 return -EINVAL; 434 } 435 436 if (unlikely(clk->enable_reg)) 437 pr_err("%s: %s: should use dflt_clk_enable ?!\n", __func__, 438 __clk_get_name(hw->clk)); 439 440 if (!clkdm_control) { 441 pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", 442 __func__, __clk_get_name(hw->clk)); 443 return 0; 444 } 445 446 ret = clkdm_clk_enable(clk->clkdm, hw->clk); 447 WARN(ret, "%s: could not enable %s's clockdomain %s: %d\n", 448 __func__, __clk_get_name(hw->clk), clk->clkdm->name, ret); 449 450 return ret; 451 } 452 453 /** 454 * omap2_clkops_disable_clkdm - decrement usecount on clkdm of @hw 455 * @hw: struct clk_hw * of the clock being disabled 456 * 457 * Decrement the usecount of the clockdomain of the clock pointed to 458 * by @hw; if the usecount is 0, the clockdomain will be "disabled." 459 * Only needed for clocks that don't use omap2_dflt_clk_disable() as their 460 * disable function pointer. No return value. 461 */ 462 void omap2_clkops_disable_clkdm(struct clk_hw *hw) 463 { 464 struct clk_hw_omap *clk; 465 466 clk = to_clk_hw_omap(hw); 467 468 if (unlikely(!clk->clkdm)) { 469 pr_err("%s: %s: no clkdm set ?!\n", __func__, 470 __clk_get_name(hw->clk)); 471 return; 472 } 473 474 if (unlikely(clk->enable_reg)) 475 pr_err("%s: %s: should use dflt_clk_disable ?!\n", __func__, 476 __clk_get_name(hw->clk)); 477 478 if (!clkdm_control) { 479 pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", 480 __func__, __clk_get_name(hw->clk)); 481 return; 482 } 483 484 clkdm_clk_disable(clk->clkdm, hw->clk); 485 } 486 487 /** 488 * omap2_dflt_clk_is_enabled - is clock enabled in the hardware? 489 * @hw: struct clk_hw * to check 490 * 491 * Return 1 if the clock represented by @hw is enabled in the 492 * hardware, or 0 otherwise. Intended for use in the struct 493 * clk_ops.is_enabled function pointer. 494 */ 495 int omap2_dflt_clk_is_enabled(struct clk_hw *hw) 496 { 497 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 498 u32 v; 499 500 v = omap2_clk_readl(clk, clk->enable_reg); 501 502 if (clk->flags & INVERT_ENABLE) 503 v ^= BIT(clk->enable_bit); 504 505 v &= BIT(clk->enable_bit); 506 507 return v ? 1 : 0; 508 } 509 510 static int __initdata mpurate; 511 512 /* 513 * By default we use the rate set by the bootloader. 514 * You can override this with mpurate= cmdline option. 515 */ 516 static int __init omap_clk_setup(char *str) 517 { 518 get_option(&str, &mpurate); 519 520 if (!mpurate) 521 return 1; 522 523 if (mpurate < 1000) 524 mpurate *= 1000000; 525 526 return 1; 527 } 528 __setup("mpurate=", omap_clk_setup); 529 530 /** 531 * omap2_init_clk_hw_omap_clocks - initialize an OMAP clock 532 * @clk: struct clk * to initialize 533 * 534 * Add an OMAP clock @clk to the internal list of OMAP clocks. Used 535 * temporarily for autoidle handling, until this support can be 536 * integrated into the common clock framework code in some way. No 537 * return value. 538 */ 539 void omap2_init_clk_hw_omap_clocks(struct clk *clk) 540 { 541 struct clk_hw_omap *c; 542 543 if (__clk_get_flags(clk) & CLK_IS_BASIC) 544 return; 545 546 c = to_clk_hw_omap(__clk_get_hw(clk)); 547 list_add(&c->node, &clk_hw_omap_clocks); 548 } 549 550 /** 551 * omap2_clk_enable_autoidle_all - enable autoidle on all OMAP clocks that 552 * support it 553 * 554 * Enable clock autoidle on all OMAP clocks that have allow_idle 555 * function pointers associated with them. This function is intended 556 * to be temporary until support for this is added to the common clock 557 * code. Returns 0. 558 */ 559 int omap2_clk_enable_autoidle_all(void) 560 { 561 struct clk_hw_omap *c; 562 563 list_for_each_entry(c, &clk_hw_omap_clocks, node) 564 if (c->ops && c->ops->allow_idle) 565 c->ops->allow_idle(c); 566 567 of_ti_clk_allow_autoidle_all(); 568 569 return 0; 570 } 571 572 /** 573 * omap2_clk_disable_autoidle_all - disable autoidle on all OMAP clocks that 574 * support it 575 * 576 * Disable clock autoidle on all OMAP clocks that have allow_idle 577 * function pointers associated with them. This function is intended 578 * to be temporary until support for this is added to the common clock 579 * code. Returns 0. 580 */ 581 int omap2_clk_disable_autoidle_all(void) 582 { 583 struct clk_hw_omap *c; 584 585 list_for_each_entry(c, &clk_hw_omap_clocks, node) 586 if (c->ops && c->ops->deny_idle) 587 c->ops->deny_idle(c); 588 589 of_ti_clk_deny_autoidle_all(); 590 591 return 0; 592 } 593 594 /** 595 * omap2_clk_deny_idle - disable autoidle on an OMAP clock 596 * @clk: struct clk * to disable autoidle for 597 * 598 * Disable autoidle on an OMAP clock. 599 */ 600 int omap2_clk_deny_idle(struct clk *clk) 601 { 602 struct clk_hw_omap *c; 603 604 if (__clk_get_flags(clk) & CLK_IS_BASIC) 605 return -EINVAL; 606 607 c = to_clk_hw_omap(__clk_get_hw(clk)); 608 if (c->ops && c->ops->deny_idle) 609 c->ops->deny_idle(c); 610 return 0; 611 } 612 613 /** 614 * omap2_clk_allow_idle - enable autoidle on an OMAP clock 615 * @clk: struct clk * to enable autoidle for 616 * 617 * Enable autoidle on an OMAP clock. 618 */ 619 int omap2_clk_allow_idle(struct clk *clk) 620 { 621 struct clk_hw_omap *c; 622 623 if (__clk_get_flags(clk) & CLK_IS_BASIC) 624 return -EINVAL; 625 626 c = to_clk_hw_omap(__clk_get_hw(clk)); 627 if (c->ops && c->ops->allow_idle) 628 c->ops->allow_idle(c); 629 return 0; 630 } 631 632 /** 633 * omap2_clk_enable_init_clocks - prepare & enable a list of clocks 634 * @clk_names: ptr to an array of strings of clock names to enable 635 * @num_clocks: number of clock names in @clk_names 636 * 637 * Prepare and enable a list of clocks, named by @clk_names. No 638 * return value. XXX Deprecated; only needed until these clocks are 639 * properly claimed and enabled by the drivers or core code that uses 640 * them. XXX What code disables & calls clk_put on these clocks? 641 */ 642 void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks) 643 { 644 struct clk *init_clk; 645 int i; 646 647 for (i = 0; i < num_clocks; i++) { 648 init_clk = clk_get(NULL, clk_names[i]); 649 clk_prepare_enable(init_clk); 650 } 651 } 652 653 const struct clk_hw_omap_ops clkhwops_wait = { 654 .find_idlest = omap2_clk_dflt_find_idlest, 655 .find_companion = omap2_clk_dflt_find_companion, 656 }; 657 658 /** 659 * omap_clocks_register - register an array of omap_clk 660 * @ocs: pointer to an array of omap_clk to register 661 */ 662 void __init omap_clocks_register(struct omap_clk oclks[], int cnt) 663 { 664 struct omap_clk *c; 665 666 for (c = oclks; c < oclks + cnt; c++) { 667 clkdev_add(&c->lk); 668 if (!__clk_init(NULL, c->lk.clk)) 669 omap2_init_clk_hw_omap_clocks(c->lk.clk); 670 } 671 } 672 673 /** 674 * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument 675 * @mpurate_ck_name: clk name of the clock to change rate 676 * 677 * Change the ARM MPU clock rate to the rate specified on the command 678 * line, if one was specified. @mpurate_ck_name should be 679 * "virt_prcm_set" on OMAP2xxx and "dpll1_ck" on OMAP34xx/OMAP36xx. 680 * XXX Does not handle voltage scaling - on OMAP2xxx this is currently 681 * handled by the virt_prcm_set clock, but this should be handled by 682 * the OPP layer. XXX This is intended to be handled by the OPP layer 683 * code in the near future and should be removed from the clock code. 684 * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects 685 * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name 686 * cannot be found, or 0 upon success. 687 */ 688 int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name) 689 { 690 struct clk *mpurate_ck; 691 int r; 692 693 if (!mpurate) 694 return -EINVAL; 695 696 mpurate_ck = clk_get(NULL, mpurate_ck_name); 697 if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name)) 698 return -ENOENT; 699 700 r = clk_set_rate(mpurate_ck, mpurate); 701 if (r < 0) { 702 WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n", 703 mpurate_ck_name, mpurate, r); 704 clk_put(mpurate_ck); 705 return -EINVAL; 706 } 707 708 calibrate_delay(); 709 clk_put(mpurate_ck); 710 711 return 0; 712 } 713 714 /** 715 * omap2_clk_print_new_rates - print summary of current clock tree rates 716 * @hfclkin_ck_name: clk name for the off-chip HF oscillator 717 * @core_ck_name: clk name for the on-chip CORE_CLK 718 * @mpu_ck_name: clk name for the ARM MPU clock 719 * 720 * Prints a short message to the console with the HFCLKIN oscillator 721 * rate, the rate of the CORE clock, and the rate of the ARM MPU clock. 722 * Called by the boot-time MPU rate switching code. XXX This is intended 723 * to be handled by the OPP layer code in the near future and should be 724 * removed from the clock code. No return value. 725 */ 726 void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, 727 const char *core_ck_name, 728 const char *mpu_ck_name) 729 { 730 struct clk *hfclkin_ck, *core_ck, *mpu_ck; 731 unsigned long hfclkin_rate; 732 733 mpu_ck = clk_get(NULL, mpu_ck_name); 734 if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name)) 735 return; 736 737 core_ck = clk_get(NULL, core_ck_name); 738 if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name)) 739 return; 740 741 hfclkin_ck = clk_get(NULL, hfclkin_ck_name); 742 if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name)) 743 return; 744 745 hfclkin_rate = clk_get_rate(hfclkin_ck); 746 747 pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", 748 (hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10), 749 (clk_get_rate(core_ck) / 1000000), 750 (clk_get_rate(mpu_ck) / 1000000)); 751 } 752 753 /** 754 * ti_clk_init_features - init clock features struct for the SoC 755 * 756 * Initializes the clock features struct based on the SoC type. 757 */ 758 void __init ti_clk_init_features(void) 759 { 760 /* Fint setup for DPLLs */ 761 if (cpu_is_omap3430()) { 762 ti_clk_features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN; 763 ti_clk_features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX; 764 ti_clk_features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX; 765 ti_clk_features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN; 766 } else { 767 ti_clk_features.fint_min = OMAP3PLUS_DPLL_FINT_MIN; 768 ti_clk_features.fint_max = OMAP3PLUS_DPLL_FINT_MAX; 769 } 770 } 771