1 /* 2 * linux/arch/arm/mach-omap2/clock.c 3 * 4 * Copyright (C) 2005-2008 Texas Instruments, Inc. 5 * Copyright (C) 2004-2010 Nokia Corporation 6 * 7 * Contacts: 8 * Richard Woodruff <r-woodruff2@ti.com> 9 * Paul Walmsley 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 #undef DEBUG 16 17 #include <linux/kernel.h> 18 #include <linux/export.h> 19 #include <linux/list.h> 20 #include <linux/errno.h> 21 #include <linux/err.h> 22 #include <linux/delay.h> 23 #include <linux/clk-provider.h> 24 #include <linux/io.h> 25 #include <linux/bitops.h> 26 #include <linux/of_address.h> 27 #include <asm/cpu.h> 28 29 #include <trace/events/power.h> 30 31 #include "soc.h" 32 #include "clockdomain.h" 33 #include "clock.h" 34 #include "cm.h" 35 #include "cm2xxx.h" 36 #include "cm3xxx.h" 37 #include "cm-regbits-24xx.h" 38 #include "cm-regbits-34xx.h" 39 #include "common.h" 40 41 u16 cpu_mask; 42 43 /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ 44 #define OMAP3430_DPLL_FINT_BAND1_MIN 750000 45 #define OMAP3430_DPLL_FINT_BAND1_MAX 2100000 46 #define OMAP3430_DPLL_FINT_BAND2_MIN 7500000 47 #define OMAP3430_DPLL_FINT_BAND2_MAX 21000000 48 49 /* 50 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx. 51 * From device data manual section 4.3 "DPLL and DLL Specifications". 52 */ 53 #define OMAP3PLUS_DPLL_FINT_MIN 32000 54 #define OMAP3PLUS_DPLL_FINT_MAX 52000000 55 56 static struct ti_clk_ll_ops omap_clk_ll_ops = { 57 .clkdm_clk_enable = clkdm_clk_enable, 58 .clkdm_clk_disable = clkdm_clk_disable, 59 .cm_wait_module_ready = omap_cm_wait_module_ready, 60 .cm_split_idlest_reg = cm_split_idlest_reg, 61 }; 62 63 /** 64 * omap2_clk_setup_ll_ops - setup clock driver low-level ops 65 * 66 * Sets up clock driver low-level platform ops. These are needed 67 * for register accesses and various other misc platform operations. 68 * Returns 0 on success, -EBUSY if low level ops have been registered 69 * already. 70 */ 71 int __init omap2_clk_setup_ll_ops(void) 72 { 73 return ti_clk_setup_ll_ops(&omap_clk_ll_ops); 74 } 75 76 /* 77 * OMAP2+ specific clock functions 78 */ 79 80 /* Private functions */ 81 82 /* Public functions */ 83 84 /** 85 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk 86 * @clk: OMAP clock struct ptr to use 87 * 88 * Convert a clockdomain name stored in a struct clk 'clk' into a 89 * clockdomain pointer, and save it into the struct clk. Intended to be 90 * called during clk_register(). No return value. 91 */ 92 void omap2_init_clk_clkdm(struct clk_hw *hw) 93 { 94 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 95 struct clockdomain *clkdm; 96 const char *clk_name; 97 98 if (!clk->clkdm_name) 99 return; 100 101 clk_name = __clk_get_name(hw->clk); 102 103 clkdm = clkdm_lookup(clk->clkdm_name); 104 if (clkdm) { 105 pr_debug("clock: associated clk %s to clkdm %s\n", 106 clk_name, clk->clkdm_name); 107 clk->clkdm = clkdm; 108 } else { 109 pr_debug("clock: could not associate clk %s to clkdm %s\n", 110 clk_name, clk->clkdm_name); 111 } 112 } 113 114 static int __initdata mpurate; 115 116 /* 117 * By default we use the rate set by the bootloader. 118 * You can override this with mpurate= cmdline option. 119 */ 120 static int __init omap_clk_setup(char *str) 121 { 122 get_option(&str, &mpurate); 123 124 if (!mpurate) 125 return 1; 126 127 if (mpurate < 1000) 128 mpurate *= 1000000; 129 130 return 1; 131 } 132 __setup("mpurate=", omap_clk_setup); 133 134 /** 135 * omap2_clk_print_new_rates - print summary of current clock tree rates 136 * @hfclkin_ck_name: clk name for the off-chip HF oscillator 137 * @core_ck_name: clk name for the on-chip CORE_CLK 138 * @mpu_ck_name: clk name for the ARM MPU clock 139 * 140 * Prints a short message to the console with the HFCLKIN oscillator 141 * rate, the rate of the CORE clock, and the rate of the ARM MPU clock. 142 * Called by the boot-time MPU rate switching code. XXX This is intended 143 * to be handled by the OPP layer code in the near future and should be 144 * removed from the clock code. No return value. 145 */ 146 void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, 147 const char *core_ck_name, 148 const char *mpu_ck_name) 149 { 150 struct clk *hfclkin_ck, *core_ck, *mpu_ck; 151 unsigned long hfclkin_rate; 152 153 mpu_ck = clk_get(NULL, mpu_ck_name); 154 if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name)) 155 return; 156 157 core_ck = clk_get(NULL, core_ck_name); 158 if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name)) 159 return; 160 161 hfclkin_ck = clk_get(NULL, hfclkin_ck_name); 162 if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name)) 163 return; 164 165 hfclkin_rate = clk_get_rate(hfclkin_ck); 166 167 pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", 168 (hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10), 169 (clk_get_rate(core_ck) / 1000000), 170 (clk_get_rate(mpu_ck) / 1000000)); 171 } 172 173 /** 174 * ti_clk_init_features - init clock features struct for the SoC 175 * 176 * Initializes the clock features struct based on the SoC type. 177 */ 178 void __init ti_clk_init_features(void) 179 { 180 struct ti_clk_features features = { 0 }; 181 /* Fint setup for DPLLs */ 182 if (cpu_is_omap3430()) { 183 features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN; 184 features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX; 185 features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX; 186 features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN; 187 } else { 188 features.fint_min = OMAP3PLUS_DPLL_FINT_MIN; 189 features.fint_max = OMAP3PLUS_DPLL_FINT_MAX; 190 } 191 192 /* Bypass value setup for DPLLs */ 193 if (cpu_is_omap24xx()) { 194 features.dpll_bypass_vals |= 195 (1 << OMAP2XXX_EN_DPLL_LPBYPASS) | 196 (1 << OMAP2XXX_EN_DPLL_FRBYPASS); 197 } else if (cpu_is_omap34xx()) { 198 features.dpll_bypass_vals |= 199 (1 << OMAP3XXX_EN_DPLL_LPBYPASS) | 200 (1 << OMAP3XXX_EN_DPLL_FRBYPASS); 201 } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() || 202 soc_is_omap54xx() || soc_is_dra7xx()) { 203 features.dpll_bypass_vals |= 204 (1 << OMAP4XXX_EN_DPLL_LPBYPASS) | 205 (1 << OMAP4XXX_EN_DPLL_FRBYPASS) | 206 (1 << OMAP4XXX_EN_DPLL_MNBYPASS); 207 } 208 209 /* Jitter correction only available on OMAP343X */ 210 if (cpu_is_omap343x()) 211 features.flags |= TI_CLK_DPLL_HAS_FREQSEL; 212 213 /* Idlest value for interface clocks. 214 * 24xx uses 0 to indicate not ready, and 1 to indicate ready. 215 * 34xx reverses this, just to keep us on our toes 216 * AM35xx uses both, depending on the module. 217 */ 218 if (cpu_is_omap24xx()) 219 features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL; 220 else if (cpu_is_omap34xx()) 221 features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL; 222 223 /* On OMAP3430 ES1.0, DPLL4 can't be re-programmed */ 224 if (omap_rev() == OMAP3430_REV_ES1_0) 225 features.flags |= TI_CLK_DPLL4_DENY_REPROGRAM; 226 227 ti_clk_setup_features(&features); 228 } 229