1 /* 2 * linux/arch/arm/mach-omap2/clock.c 3 * 4 * Copyright (C) 2005 Texas Instruments Inc. 5 * Richard Woodruff <r-woodruff2@ti.com> 6 * Created for OMAP2. 7 * 8 * Cleaned up and modified to use omap shared clock framework by 9 * Tony Lindgren <tony@atomide.com> 10 * 11 * Based on omap1 clock.c, Copyright (C) 2004 - 2005 Nokia corporation 12 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License version 2 as 16 * published by the Free Software Foundation. 17 */ 18 #include <linux/module.h> 19 #include <linux/kernel.h> 20 #include <linux/device.h> 21 #include <linux/list.h> 22 #include <linux/errno.h> 23 #include <linux/delay.h> 24 #include <linux/clk.h> 25 26 #include <asm/io.h> 27 28 #include <asm/arch/clock.h> 29 #include <asm/arch/sram.h> 30 31 #include "prcm-regs.h" 32 #include "memory.h" 33 #include "clock.h" 34 35 #undef DEBUG 36 37 //#define DOWN_VARIABLE_DPLL 1 /* Experimental */ 38 39 static struct prcm_config *curr_prcm_set; 40 static u32 curr_perf_level = PRCM_FULL_SPEED; 41 static struct clk *vclk; 42 static struct clk *sclk; 43 44 /*------------------------------------------------------------------------- 45 * Omap2 specific clock functions 46 *-------------------------------------------------------------------------*/ 47 48 /* Recalculate SYST_CLK */ 49 static void omap2_sys_clk_recalc(struct clk * clk) 50 { 51 u32 div = PRCM_CLKSRC_CTRL; 52 div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */ 53 div >>= clk->rate_offset; 54 clk->rate = (clk->parent->rate / div); 55 propagate_rate(clk); 56 } 57 58 static u32 omap2_get_dpll_rate(struct clk * tclk) 59 { 60 long long dpll_clk; 61 int dpll_mult, dpll_div, amult; 62 63 dpll_mult = (CM_CLKSEL1_PLL >> 12) & 0x03ff; /* 10 bits */ 64 dpll_div = (CM_CLKSEL1_PLL >> 8) & 0x0f; /* 4 bits */ 65 dpll_clk = (long long)tclk->parent->rate * dpll_mult; 66 do_div(dpll_clk, dpll_div + 1); 67 amult = CM_CLKSEL2_PLL & 0x3; 68 dpll_clk *= amult; 69 70 return dpll_clk; 71 } 72 73 static void omap2_followparent_recalc(struct clk *clk) 74 { 75 followparent_recalc(clk); 76 } 77 78 static void omap2_propagate_rate(struct clk * clk) 79 { 80 if (!(clk->flags & RATE_FIXED)) 81 clk->rate = clk->parent->rate; 82 83 propagate_rate(clk); 84 } 85 86 static void omap2_set_osc_ck(int enable) 87 { 88 if (enable) 89 PRCM_CLKSRC_CTRL &= ~(0x3 << 3); 90 else 91 PRCM_CLKSRC_CTRL |= 0x3 << 3; 92 } 93 94 /* Enable an APLL if off */ 95 static void omap2_clk_fixed_enable(struct clk *clk) 96 { 97 u32 cval, i=0; 98 99 if (clk->enable_bit == 0xff) /* Parent will do it */ 100 return; 101 102 cval = CM_CLKEN_PLL; 103 104 if ((cval & (0x3 << clk->enable_bit)) == (0x3 << clk->enable_bit)) 105 return; 106 107 cval &= ~(0x3 << clk->enable_bit); 108 cval |= (0x3 << clk->enable_bit); 109 CM_CLKEN_PLL = cval; 110 111 if (clk == &apll96_ck) 112 cval = (1 << 8); 113 else if (clk == &apll54_ck) 114 cval = (1 << 6); 115 116 while (!(CM_IDLEST_CKGEN & cval)) { /* Wait for lock */ 117 ++i; 118 udelay(1); 119 if (i == 100000) { 120 printk(KERN_ERR "Clock %s didn't lock\n", clk->name); 121 break; 122 } 123 } 124 } 125 126 static void omap2_clk_wait_ready(struct clk *clk) 127 { 128 unsigned long reg, other_reg, st_reg; 129 u32 bit; 130 int i; 131 132 reg = (unsigned long) clk->enable_reg; 133 if (reg == (unsigned long) &CM_FCLKEN1_CORE || 134 reg == (unsigned long) &CM_FCLKEN2_CORE) 135 other_reg = (reg & ~0xf0) | 0x10; 136 else if (reg == (unsigned long) &CM_ICLKEN1_CORE || 137 reg == (unsigned long) &CM_ICLKEN2_CORE) 138 other_reg = (reg & ~0xf0) | 0x00; 139 else 140 return; 141 142 /* No check for DSS or cam clocks */ 143 if ((reg & 0x0f) == 0) { 144 if (clk->enable_bit <= 1 || clk->enable_bit == 31) 145 return; 146 } 147 148 /* Check if both functional and interface clocks 149 * are running. */ 150 bit = 1 << clk->enable_bit; 151 if (!(__raw_readl(other_reg) & bit)) 152 return; 153 st_reg = (other_reg & ~0xf0) | 0x20; 154 i = 0; 155 while (!(__raw_readl(st_reg) & bit)) { 156 i++; 157 if (i == 100000) { 158 printk(KERN_ERR "Timeout enabling clock %s\n", clk->name); 159 break; 160 } 161 } 162 if (i) 163 pr_debug("Clock %s stable after %d loops\n", clk->name, i); 164 } 165 166 /* Enables clock without considering parent dependencies or use count 167 * REVISIT: Maybe change this to use clk->enable like on omap1? 168 */ 169 static int _omap2_clk_enable(struct clk * clk) 170 { 171 u32 regval32; 172 173 if (clk->flags & ALWAYS_ENABLED) 174 return 0; 175 176 if (unlikely(clk == &osc_ck)) { 177 omap2_set_osc_ck(1); 178 return 0; 179 } 180 181 if (unlikely(clk->enable_reg == 0)) { 182 printk(KERN_ERR "clock.c: Enable for %s without enable code\n", 183 clk->name); 184 return 0; 185 } 186 187 if (clk->enable_reg == (void __iomem *)&CM_CLKEN_PLL) { 188 omap2_clk_fixed_enable(clk); 189 return 0; 190 } 191 192 regval32 = __raw_readl(clk->enable_reg); 193 regval32 |= (1 << clk->enable_bit); 194 __raw_writel(regval32, clk->enable_reg); 195 wmb(); 196 197 omap2_clk_wait_ready(clk); 198 199 return 0; 200 } 201 202 /* Stop APLL */ 203 static void omap2_clk_fixed_disable(struct clk *clk) 204 { 205 u32 cval; 206 207 if(clk->enable_bit == 0xff) /* let parent off do it */ 208 return; 209 210 cval = CM_CLKEN_PLL; 211 cval &= ~(0x3 << clk->enable_bit); 212 CM_CLKEN_PLL = cval; 213 } 214 215 /* Disables clock without considering parent dependencies or use count */ 216 static void _omap2_clk_disable(struct clk *clk) 217 { 218 u32 regval32; 219 220 if (unlikely(clk == &osc_ck)) { 221 omap2_set_osc_ck(0); 222 return; 223 } 224 225 if (clk->enable_reg == 0) 226 return; 227 228 if (clk->enable_reg == (void __iomem *)&CM_CLKEN_PLL) { 229 omap2_clk_fixed_disable(clk); 230 return; 231 } 232 233 regval32 = __raw_readl(clk->enable_reg); 234 regval32 &= ~(1 << clk->enable_bit); 235 __raw_writel(regval32, clk->enable_reg); 236 wmb(); 237 } 238 239 static int omap2_clk_enable(struct clk *clk) 240 { 241 int ret = 0; 242 243 if (clk->usecount++ == 0) { 244 if (likely((u32)clk->parent)) 245 ret = omap2_clk_enable(clk->parent); 246 247 if (unlikely(ret != 0)) { 248 clk->usecount--; 249 return ret; 250 } 251 252 ret = _omap2_clk_enable(clk); 253 254 if (unlikely(ret != 0) && clk->parent) { 255 omap2_clk_disable(clk->parent); 256 clk->usecount--; 257 } 258 } 259 260 return ret; 261 } 262 263 static void omap2_clk_disable(struct clk *clk) 264 { 265 if (clk->usecount > 0 && !(--clk->usecount)) { 266 _omap2_clk_disable(clk); 267 if (likely((u32)clk->parent)) 268 omap2_clk_disable(clk->parent); 269 } 270 } 271 272 /* 273 * Uses the current prcm set to tell if a rate is valid. 274 * You can go slower, but not faster within a given rate set. 275 */ 276 static u32 omap2_dpll_round_rate(unsigned long target_rate) 277 { 278 u32 high, low; 279 280 if ((CM_CLKSEL2_PLL & 0x3) == 1) { /* DPLL clockout */ 281 high = curr_prcm_set->dpll_speed * 2; 282 low = curr_prcm_set->dpll_speed; 283 } else { /* DPLL clockout x 2 */ 284 high = curr_prcm_set->dpll_speed; 285 low = curr_prcm_set->dpll_speed / 2; 286 } 287 288 #ifdef DOWN_VARIABLE_DPLL 289 if (target_rate > high) 290 return high; 291 else 292 return target_rate; 293 #else 294 if (target_rate > low) 295 return high; 296 else 297 return low; 298 #endif 299 300 } 301 302 /* 303 * Used for clocks that are part of CLKSEL_xyz governed clocks. 304 * REVISIT: Maybe change to use clk->enable() functions like on omap1? 305 */ 306 static void omap2_clksel_recalc(struct clk * clk) 307 { 308 u32 fixed = 0, div = 0; 309 310 if (clk == &dpll_ck) { 311 clk->rate = omap2_get_dpll_rate(clk); 312 fixed = 1; 313 div = 0; 314 } 315 316 if (clk == &iva1_mpu_int_ifck) { 317 div = 2; 318 fixed = 1; 319 } 320 321 if ((clk == &dss1_fck) && ((CM_CLKSEL1_CORE & (0x1f << 8)) == 0)) { 322 clk->rate = sys_ck.rate; 323 return; 324 } 325 326 if (!fixed) { 327 div = omap2_clksel_get_divisor(clk); 328 if (div == 0) 329 return; 330 } 331 332 if (div != 0) { 333 if (unlikely(clk->rate == clk->parent->rate / div)) 334 return; 335 clk->rate = clk->parent->rate / div; 336 } 337 338 if (unlikely(clk->flags & RATE_PROPAGATES)) 339 propagate_rate(clk); 340 } 341 342 /* 343 * Finds best divider value in an array based on the source and target 344 * rates. The divider array must be sorted with smallest divider first. 345 */ 346 static inline u32 omap2_divider_from_table(u32 size, u32 *div_array, 347 u32 src_rate, u32 tgt_rate) 348 { 349 int i, test_rate; 350 351 if (div_array == NULL) 352 return ~1; 353 354 for (i=0; i < size; i++) { 355 test_rate = src_rate / *div_array; 356 if (test_rate <= tgt_rate) 357 return *div_array; 358 ++div_array; 359 } 360 361 return ~0; /* No acceptable divider */ 362 } 363 364 /* 365 * Find divisor for the given clock and target rate. 366 * 367 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT, 368 * they are only settable as part of virtual_prcm set. 369 */ 370 static u32 omap2_clksel_round_rate(struct clk *tclk, u32 target_rate, 371 u32 *new_div) 372 { 373 u32 gfx_div[] = {2, 3, 4}; 374 u32 sysclkout_div[] = {1, 2, 4, 8, 16}; 375 u32 dss1_div[] = {1, 2, 3, 4, 5, 6, 8, 9, 12, 16}; 376 u32 vylnq_div[] = {1, 2, 3, 4, 6, 8, 9, 12, 16, 18}; 377 u32 best_div = ~0, asize = 0; 378 u32 *div_array = NULL; 379 380 switch (tclk->flags & SRC_RATE_SEL_MASK) { 381 case CM_GFX_SEL1: 382 asize = 3; 383 div_array = gfx_div; 384 break; 385 case CM_PLL_SEL1: 386 return omap2_dpll_round_rate(target_rate); 387 case CM_SYSCLKOUT_SEL1: 388 asize = 5; 389 div_array = sysclkout_div; 390 break; 391 case CM_CORE_SEL1: 392 if(tclk == &dss1_fck){ 393 if(tclk->parent == &core_ck){ 394 asize = 10; 395 div_array = dss1_div; 396 } else { 397 *new_div = 0; /* fixed clk */ 398 return(tclk->parent->rate); 399 } 400 } else if((tclk == &vlynq_fck) && cpu_is_omap2420()){ 401 if(tclk->parent == &core_ck){ 402 asize = 10; 403 div_array = vylnq_div; 404 } else { 405 *new_div = 0; /* fixed clk */ 406 return(tclk->parent->rate); 407 } 408 } 409 break; 410 } 411 412 best_div = omap2_divider_from_table(asize, div_array, 413 tclk->parent->rate, target_rate); 414 if (best_div == ~0){ 415 *new_div = 1; 416 return best_div; /* signal error */ 417 } 418 419 *new_div = best_div; 420 return (tclk->parent->rate / best_div); 421 } 422 423 /* Given a clock and a rate apply a clock specific rounding function */ 424 static long omap2_clk_round_rate(struct clk *clk, unsigned long rate) 425 { 426 u32 new_div = 0; 427 int valid_rate; 428 429 if (clk->flags & RATE_FIXED) 430 return clk->rate; 431 432 if (clk->flags & RATE_CKCTL) { 433 valid_rate = omap2_clksel_round_rate(clk, rate, &new_div); 434 return valid_rate; 435 } 436 437 if (clk->round_rate != 0) 438 return clk->round_rate(clk, rate); 439 440 return clk->rate; 441 } 442 443 /* 444 * Check the DLL lock state, and return tue if running in unlock mode. 445 * This is needed to compenste for the shifted DLL value in unlock mode. 446 */ 447 static u32 omap2_dll_force_needed(void) 448 { 449 u32 dll_state = SDRC_DLLA_CTRL; /* dlla and dllb are a set */ 450 451 if ((dll_state & (1 << 2)) == (1 << 2)) 452 return 1; 453 else 454 return 0; 455 } 456 457 static u32 omap2_reprogram_sdrc(u32 level, u32 force) 458 { 459 u32 slow_dll_ctrl, fast_dll_ctrl, m_type; 460 u32 prev = curr_perf_level, flags; 461 462 if ((curr_perf_level == level) && !force) 463 return prev; 464 465 m_type = omap2_memory_get_type(); 466 slow_dll_ctrl = omap2_memory_get_slow_dll_ctrl(); 467 fast_dll_ctrl = omap2_memory_get_fast_dll_ctrl(); 468 469 if (level == PRCM_HALF_SPEED) { 470 local_irq_save(flags); 471 PRCM_VOLTSETUP = 0xffff; 472 omap2_sram_reprogram_sdrc(PRCM_HALF_SPEED, 473 slow_dll_ctrl, m_type); 474 curr_perf_level = PRCM_HALF_SPEED; 475 local_irq_restore(flags); 476 } 477 if (level == PRCM_FULL_SPEED) { 478 local_irq_save(flags); 479 PRCM_VOLTSETUP = 0xffff; 480 omap2_sram_reprogram_sdrc(PRCM_FULL_SPEED, 481 fast_dll_ctrl, m_type); 482 curr_perf_level = PRCM_FULL_SPEED; 483 local_irq_restore(flags); 484 } 485 486 return prev; 487 } 488 489 static int omap2_reprogram_dpll(struct clk * clk, unsigned long rate) 490 { 491 u32 flags, cur_rate, low, mult, div, valid_rate, done_rate; 492 u32 bypass = 0; 493 struct prcm_config tmpset; 494 int ret = -EINVAL; 495 496 local_irq_save(flags); 497 cur_rate = omap2_get_dpll_rate(&dpll_ck); 498 mult = CM_CLKSEL2_PLL & 0x3; 499 500 if ((rate == (cur_rate / 2)) && (mult == 2)) { 501 omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1); 502 } else if ((rate == (cur_rate * 2)) && (mult == 1)) { 503 omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1); 504 } else if (rate != cur_rate) { 505 valid_rate = omap2_dpll_round_rate(rate); 506 if (valid_rate != rate) 507 goto dpll_exit; 508 509 if ((CM_CLKSEL2_PLL & 0x3) == 1) 510 low = curr_prcm_set->dpll_speed; 511 else 512 low = curr_prcm_set->dpll_speed / 2; 513 514 tmpset.cm_clksel1_pll = CM_CLKSEL1_PLL; 515 tmpset.cm_clksel1_pll &= ~(0x3FFF << 8); 516 div = ((curr_prcm_set->xtal_speed / 1000000) - 1); 517 tmpset.cm_clksel2_pll = CM_CLKSEL2_PLL; 518 tmpset.cm_clksel2_pll &= ~0x3; 519 if (rate > low) { 520 tmpset.cm_clksel2_pll |= 0x2; 521 mult = ((rate / 2) / 1000000); 522 done_rate = PRCM_FULL_SPEED; 523 } else { 524 tmpset.cm_clksel2_pll |= 0x1; 525 mult = (rate / 1000000); 526 done_rate = PRCM_HALF_SPEED; 527 } 528 tmpset.cm_clksel1_pll |= ((div << 8) | (mult << 12)); 529 530 /* Worst case */ 531 tmpset.base_sdrc_rfr = V24XX_SDRC_RFR_CTRL_BYPASS; 532 533 if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */ 534 bypass = 1; 535 536 omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1); /* For init_mem */ 537 538 /* Force dll lock mode */ 539 omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr, 540 bypass); 541 542 /* Errata: ret dll entry state */ 543 omap2_init_memory_params(omap2_dll_force_needed()); 544 omap2_reprogram_sdrc(done_rate, 0); 545 } 546 omap2_clksel_recalc(&dpll_ck); 547 ret = 0; 548 549 dpll_exit: 550 local_irq_restore(flags); 551 return(ret); 552 } 553 554 /* Just return the MPU speed */ 555 static void omap2_mpu_recalc(struct clk * clk) 556 { 557 clk->rate = curr_prcm_set->mpu_speed; 558 } 559 560 /* 561 * Look for a rate equal or less than the target rate given a configuration set. 562 * 563 * What's not entirely clear is "which" field represents the key field. 564 * Some might argue L3-DDR, others ARM, others IVA. This code is simple and 565 * just uses the ARM rates. 566 */ 567 static long omap2_round_to_table_rate(struct clk * clk, unsigned long rate) 568 { 569 struct prcm_config * ptr; 570 long highest_rate; 571 572 if (clk != &virt_prcm_set) 573 return -EINVAL; 574 575 highest_rate = -EINVAL; 576 577 for (ptr = rate_table; ptr->mpu_speed; ptr++) { 578 if (ptr->xtal_speed != sys_ck.rate) 579 continue; 580 581 highest_rate = ptr->mpu_speed; 582 583 /* Can check only after xtal frequency check */ 584 if (ptr->mpu_speed <= rate) 585 break; 586 } 587 return highest_rate; 588 } 589 590 /* 591 * omap2_convert_field_to_div() - turn field value into integer divider 592 */ 593 static u32 omap2_clksel_to_divisor(u32 div_sel, u32 field_val) 594 { 595 u32 i; 596 u32 clkout_array[] = {1, 2, 4, 8, 16}; 597 598 if ((div_sel & SRC_RATE_SEL_MASK) == CM_SYSCLKOUT_SEL1) { 599 for (i = 0; i < 5; i++) { 600 if (field_val == i) 601 return clkout_array[i]; 602 } 603 return ~0; 604 } else 605 return field_val; 606 } 607 608 /* 609 * Returns the CLKSEL divider register value 610 * REVISIT: This should be cleaned up to work nicely with void __iomem * 611 */ 612 static u32 omap2_get_clksel(u32 *div_sel, u32 *field_mask, 613 struct clk *clk) 614 { 615 int ret = ~0; 616 u32 reg_val, div_off; 617 u32 div_addr = 0; 618 u32 mask = ~0; 619 620 div_off = clk->rate_offset; 621 622 switch ((*div_sel & SRC_RATE_SEL_MASK)) { 623 case CM_MPU_SEL1: 624 div_addr = (u32)&CM_CLKSEL_MPU; 625 mask = 0x1f; 626 break; 627 case CM_DSP_SEL1: 628 div_addr = (u32)&CM_CLKSEL_DSP; 629 if (cpu_is_omap2420()) { 630 if ((div_off == 0) || (div_off == 8)) 631 mask = 0x1f; 632 else if (div_off == 5) 633 mask = 0x3; 634 } else if (cpu_is_omap2430()) { 635 if (div_off == 0) 636 mask = 0x1f; 637 else if (div_off == 5) 638 mask = 0x3; 639 } 640 break; 641 case CM_GFX_SEL1: 642 div_addr = (u32)&CM_CLKSEL_GFX; 643 if (div_off == 0) 644 mask = 0x7; 645 break; 646 case CM_MODEM_SEL1: 647 div_addr = (u32)&CM_CLKSEL_MDM; 648 if (div_off == 0) 649 mask = 0xf; 650 break; 651 case CM_SYSCLKOUT_SEL1: 652 div_addr = (u32)&PRCM_CLKOUT_CTRL; 653 if ((div_off == 3) || (div_off = 11)) 654 mask= 0x3; 655 break; 656 case CM_CORE_SEL1: 657 div_addr = (u32)&CM_CLKSEL1_CORE; 658 switch (div_off) { 659 case 0: /* l3 */ 660 case 8: /* dss1 */ 661 case 15: /* vylnc-2420 */ 662 case 20: /* ssi */ 663 mask = 0x1f; break; 664 case 5: /* l4 */ 665 mask = 0x3; break; 666 case 13: /* dss2 */ 667 mask = 0x1; break; 668 case 25: /* usb */ 669 mask = 0x7; break; 670 } 671 } 672 673 *field_mask = mask; 674 675 if (unlikely(mask == ~0)) 676 div_addr = 0; 677 678 *div_sel = div_addr; 679 680 if (unlikely(div_addr == 0)) 681 return ret; 682 683 /* Isolate field */ 684 reg_val = __raw_readl((void __iomem *)div_addr) & (mask << div_off); 685 686 /* Normalize back to divider value */ 687 reg_val >>= div_off; 688 689 return reg_val; 690 } 691 692 /* 693 * Return divider to be applied to parent clock. 694 * Return 0 on error. 695 */ 696 static u32 omap2_clksel_get_divisor(struct clk *clk) 697 { 698 int ret = 0; 699 u32 div, div_sel, div_off, field_mask, field_val; 700 701 /* isolate control register */ 702 div_sel = (SRC_RATE_SEL_MASK & clk->flags); 703 704 div_off = clk->rate_offset; 705 field_val = omap2_get_clksel(&div_sel, &field_mask, clk); 706 if (div_sel == 0) 707 return ret; 708 709 div_sel = (SRC_RATE_SEL_MASK & clk->flags); 710 div = omap2_clksel_to_divisor(div_sel, field_val); 711 712 return div; 713 } 714 715 /* Set the clock rate for a clock source */ 716 static int omap2_clk_set_rate(struct clk *clk, unsigned long rate) 717 718 { 719 int ret = -EINVAL; 720 void __iomem * reg; 721 u32 div_sel, div_off, field_mask, field_val, reg_val, validrate; 722 u32 new_div = 0; 723 724 if (!(clk->flags & CONFIG_PARTICIPANT) && (clk->flags & RATE_CKCTL)) { 725 if (clk == &dpll_ck) 726 return omap2_reprogram_dpll(clk, rate); 727 728 /* Isolate control register */ 729 div_sel = (SRC_RATE_SEL_MASK & clk->flags); 730 div_off = clk->rate_offset; 731 732 validrate = omap2_clksel_round_rate(clk, rate, &new_div); 733 if (validrate != rate) 734 return(ret); 735 736 field_val = omap2_get_clksel(&div_sel, &field_mask, clk); 737 if (div_sel == 0) 738 return ret; 739 740 if (clk->flags & CM_SYSCLKOUT_SEL1) { 741 switch (new_div) { 742 case 16: 743 field_val = 4; 744 break; 745 case 8: 746 field_val = 3; 747 break; 748 case 4: 749 field_val = 2; 750 break; 751 case 2: 752 field_val = 1; 753 break; 754 case 1: 755 field_val = 0; 756 break; 757 } 758 } else 759 field_val = new_div; 760 761 reg = (void __iomem *)div_sel; 762 763 reg_val = __raw_readl(reg); 764 reg_val &= ~(field_mask << div_off); 765 reg_val |= (field_val << div_off); 766 __raw_writel(reg_val, reg); 767 wmb(); 768 clk->rate = clk->parent->rate / field_val; 769 770 if (clk->flags & DELAYED_APP) { 771 __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL); 772 wmb(); 773 } 774 ret = 0; 775 } else if (clk->set_rate != 0) 776 ret = clk->set_rate(clk, rate); 777 778 if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES))) 779 propagate_rate(clk); 780 781 return ret; 782 } 783 784 /* Converts encoded control register address into a full address */ 785 static u32 omap2_get_src_field(u32 *type_to_addr, u32 reg_offset, 786 struct clk *src_clk, u32 *field_mask) 787 { 788 u32 val = ~0, src_reg_addr = 0, mask = 0; 789 790 /* Find target control register.*/ 791 switch ((*type_to_addr & SRC_RATE_SEL_MASK)) { 792 case CM_CORE_SEL1: 793 src_reg_addr = (u32)&CM_CLKSEL1_CORE; 794 if (reg_offset == 13) { /* DSS2_fclk */ 795 mask = 0x1; 796 if (src_clk == &sys_ck) 797 val = 0; 798 if (src_clk == &func_48m_ck) 799 val = 1; 800 } else if (reg_offset == 8) { /* DSS1_fclk */ 801 mask = 0x1f; 802 if (src_clk == &sys_ck) 803 val = 0; 804 else if (src_clk == &core_ck) /* divided clock */ 805 val = 0x10; /* rate needs fixing */ 806 } else if ((reg_offset == 15) && cpu_is_omap2420()){ /*vlnyq*/ 807 mask = 0x1F; 808 if(src_clk == &func_96m_ck) 809 val = 0; 810 else if (src_clk == &core_ck) 811 val = 0x10; 812 } 813 break; 814 case CM_CORE_SEL2: 815 src_reg_addr = (u32)&CM_CLKSEL2_CORE; 816 mask = 0x3; 817 if (src_clk == &func_32k_ck) 818 val = 0x0; 819 if (src_clk == &sys_ck) 820 val = 0x1; 821 if (src_clk == &alt_ck) 822 val = 0x2; 823 break; 824 case CM_WKUP_SEL1: 825 src_reg_addr = (u32)&CM_CLKSEL_WKUP; 826 mask = 0x3; 827 if (src_clk == &func_32k_ck) 828 val = 0x0; 829 if (src_clk == &sys_ck) 830 val = 0x1; 831 if (src_clk == &alt_ck) 832 val = 0x2; 833 break; 834 case CM_PLL_SEL1: 835 src_reg_addr = (u32)&CM_CLKSEL1_PLL; 836 mask = 0x1; 837 if (reg_offset == 0x3) { 838 if (src_clk == &apll96_ck) 839 val = 0; 840 if (src_clk == &alt_ck) 841 val = 1; 842 } 843 else if (reg_offset == 0x5) { 844 if (src_clk == &apll54_ck) 845 val = 0; 846 if (src_clk == &alt_ck) 847 val = 1; 848 } 849 break; 850 case CM_PLL_SEL2: 851 src_reg_addr = (u32)&CM_CLKSEL2_PLL; 852 mask = 0x3; 853 if (src_clk == &func_32k_ck) 854 val = 0x0; 855 if (src_clk == &dpll_ck) 856 val = 0x2; 857 break; 858 case CM_SYSCLKOUT_SEL1: 859 src_reg_addr = (u32)&PRCM_CLKOUT_CTRL; 860 mask = 0x3; 861 if (src_clk == &dpll_ck) 862 val = 0; 863 if (src_clk == &sys_ck) 864 val = 1; 865 if (src_clk == &func_96m_ck) 866 val = 2; 867 if (src_clk == &func_54m_ck) 868 val = 3; 869 break; 870 } 871 872 if (val == ~0) /* Catch errors in offset */ 873 *type_to_addr = 0; 874 else 875 *type_to_addr = src_reg_addr; 876 *field_mask = mask; 877 878 return val; 879 } 880 881 static int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) 882 { 883 void __iomem * reg; 884 u32 src_sel, src_off, field_val, field_mask, reg_val, rate; 885 int ret = -EINVAL; 886 887 if (unlikely(clk->flags & CONFIG_PARTICIPANT)) 888 return ret; 889 890 if (clk->flags & SRC_SEL_MASK) { /* On-chip SEL collection */ 891 src_sel = (SRC_RATE_SEL_MASK & clk->flags); 892 src_off = clk->src_offset; 893 894 if (src_sel == 0) 895 goto set_parent_error; 896 897 field_val = omap2_get_src_field(&src_sel, src_off, new_parent, 898 &field_mask); 899 900 reg = (void __iomem *)src_sel; 901 902 if (clk->usecount > 0) 903 _omap2_clk_disable(clk); 904 905 /* Set new source value (previous dividers if any in effect) */ 906 reg_val = __raw_readl(reg) & ~(field_mask << src_off); 907 reg_val |= (field_val << src_off); 908 __raw_writel(reg_val, reg); 909 wmb(); 910 911 if (clk->flags & DELAYED_APP) { 912 __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL); 913 wmb(); 914 } 915 if (clk->usecount > 0) 916 _omap2_clk_enable(clk); 917 918 clk->parent = new_parent; 919 920 /* SRC_RATE_SEL_MASK clocks follow their parents rates.*/ 921 if ((new_parent == &core_ck) && (clk == &dss1_fck)) 922 clk->rate = new_parent->rate / 0x10; 923 else 924 clk->rate = new_parent->rate; 925 926 if (unlikely(clk->flags & RATE_PROPAGATES)) 927 propagate_rate(clk); 928 929 return 0; 930 } else { 931 clk->parent = new_parent; 932 rate = new_parent->rate; 933 omap2_clk_set_rate(clk, rate); 934 ret = 0; 935 } 936 937 set_parent_error: 938 return ret; 939 } 940 941 /* Sets basic clocks based on the specified rate */ 942 static int omap2_select_table_rate(struct clk * clk, unsigned long rate) 943 { 944 u32 flags, cur_rate, done_rate, bypass = 0; 945 u8 cpu_mask = 0; 946 struct prcm_config *prcm; 947 unsigned long found_speed = 0; 948 949 if (clk != &virt_prcm_set) 950 return -EINVAL; 951 952 /* FIXME: Change cpu_is_omap2420() to cpu_is_omap242x() */ 953 if (cpu_is_omap2420()) 954 cpu_mask = RATE_IN_242X; 955 else if (cpu_is_omap2430()) 956 cpu_mask = RATE_IN_243X; 957 958 for (prcm = rate_table; prcm->mpu_speed; prcm++) { 959 if (!(prcm->flags & cpu_mask)) 960 continue; 961 962 if (prcm->xtal_speed != sys_ck.rate) 963 continue; 964 965 if (prcm->mpu_speed <= rate) { 966 found_speed = prcm->mpu_speed; 967 break; 968 } 969 } 970 971 if (!found_speed) { 972 printk(KERN_INFO "Could not set MPU rate to %luMHz\n", 973 rate / 1000000); 974 return -EINVAL; 975 } 976 977 curr_prcm_set = prcm; 978 cur_rate = omap2_get_dpll_rate(&dpll_ck); 979 980 if (prcm->dpll_speed == cur_rate / 2) { 981 omap2_reprogram_sdrc(PRCM_HALF_SPEED, 1); 982 } else if (prcm->dpll_speed == cur_rate * 2) { 983 omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1); 984 } else if (prcm->dpll_speed != cur_rate) { 985 local_irq_save(flags); 986 987 if (prcm->dpll_speed == prcm->xtal_speed) 988 bypass = 1; 989 990 if ((prcm->cm_clksel2_pll & 0x3) == 2) 991 done_rate = PRCM_FULL_SPEED; 992 else 993 done_rate = PRCM_HALF_SPEED; 994 995 /* MPU divider */ 996 CM_CLKSEL_MPU = prcm->cm_clksel_mpu; 997 998 /* dsp + iva1 div(2420), iva2.1(2430) */ 999 CM_CLKSEL_DSP = prcm->cm_clksel_dsp; 1000 1001 CM_CLKSEL_GFX = prcm->cm_clksel_gfx; 1002 1003 /* Major subsystem dividers */ 1004 CM_CLKSEL1_CORE = prcm->cm_clksel1_core; 1005 if (cpu_is_omap2430()) 1006 CM_CLKSEL_MDM = prcm->cm_clksel_mdm; 1007 1008 /* x2 to enter init_mem */ 1009 omap2_reprogram_sdrc(PRCM_FULL_SPEED, 1); 1010 1011 omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr, 1012 bypass); 1013 1014 omap2_init_memory_params(omap2_dll_force_needed()); 1015 omap2_reprogram_sdrc(done_rate, 0); 1016 1017 local_irq_restore(flags); 1018 } 1019 omap2_clksel_recalc(&dpll_ck); 1020 1021 return 0; 1022 } 1023 1024 /*------------------------------------------------------------------------- 1025 * Omap2 clock reset and init functions 1026 *-------------------------------------------------------------------------*/ 1027 1028 #ifdef CONFIG_OMAP_RESET_CLOCKS 1029 static void __init omap2_clk_disable_unused(struct clk *clk) 1030 { 1031 u32 regval32; 1032 1033 regval32 = __raw_readl(clk->enable_reg); 1034 if ((regval32 & (1 << clk->enable_bit)) == 0) 1035 return; 1036 1037 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name); 1038 _omap2_clk_disable(clk); 1039 } 1040 #else 1041 #define omap2_clk_disable_unused NULL 1042 #endif 1043 1044 static struct clk_functions omap2_clk_functions = { 1045 .clk_enable = omap2_clk_enable, 1046 .clk_disable = omap2_clk_disable, 1047 .clk_round_rate = omap2_clk_round_rate, 1048 .clk_set_rate = omap2_clk_set_rate, 1049 .clk_set_parent = omap2_clk_set_parent, 1050 .clk_disable_unused = omap2_clk_disable_unused, 1051 }; 1052 1053 static void __init omap2_get_crystal_rate(struct clk *osc, struct clk *sys) 1054 { 1055 u32 div, aplls, sclk = 13000000; 1056 1057 aplls = CM_CLKSEL1_PLL; 1058 aplls &= ((1 << 23) | (1 << 24) | (1 << 25)); 1059 aplls >>= 23; /* Isolate field, 0,2,3 */ 1060 1061 if (aplls == 0) 1062 sclk = 19200000; 1063 else if (aplls == 2) 1064 sclk = 13000000; 1065 else if (aplls == 3) 1066 sclk = 12000000; 1067 1068 div = PRCM_CLKSRC_CTRL; 1069 div &= ((1 << 7) | (1 << 6)); 1070 div >>= sys->rate_offset; 1071 1072 osc->rate = sclk * div; 1073 sys->rate = sclk; 1074 } 1075 1076 /* 1077 * Set clocks for bypass mode for reboot to work. 1078 */ 1079 void omap2_clk_prepare_for_reboot(void) 1080 { 1081 u32 rate; 1082 1083 if (vclk == NULL || sclk == NULL) 1084 return; 1085 1086 rate = clk_get_rate(sclk); 1087 clk_set_rate(vclk, rate); 1088 } 1089 1090 /* 1091 * Switch the MPU rate if specified on cmdline. 1092 * We cannot do this early until cmdline is parsed. 1093 */ 1094 static int __init omap2_clk_arch_init(void) 1095 { 1096 if (!mpurate) 1097 return -EINVAL; 1098 1099 if (omap2_select_table_rate(&virt_prcm_set, mpurate)) 1100 printk(KERN_ERR "Could not find matching MPU rate\n"); 1101 1102 propagate_rate(&osc_ck); /* update main root fast */ 1103 propagate_rate(&func_32k_ck); /* update main root slow */ 1104 1105 printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): " 1106 "%ld.%01ld/%ld/%ld MHz\n", 1107 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, 1108 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; 1109 1110 return 0; 1111 } 1112 arch_initcall(omap2_clk_arch_init); 1113 1114 int __init omap2_clk_init(void) 1115 { 1116 struct prcm_config *prcm; 1117 struct clk ** clkp; 1118 u32 clkrate; 1119 1120 clk_init(&omap2_clk_functions); 1121 omap2_get_crystal_rate(&osc_ck, &sys_ck); 1122 1123 for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks); 1124 clkp++) { 1125 1126 if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) { 1127 clk_register(*clkp); 1128 continue; 1129 } 1130 1131 if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) { 1132 clk_register(*clkp); 1133 continue; 1134 } 1135 } 1136 1137 /* Check the MPU rate set by bootloader */ 1138 clkrate = omap2_get_dpll_rate(&dpll_ck); 1139 for (prcm = rate_table; prcm->mpu_speed; prcm++) { 1140 if (prcm->xtal_speed != sys_ck.rate) 1141 continue; 1142 if (prcm->dpll_speed <= clkrate) 1143 break; 1144 } 1145 curr_prcm_set = prcm; 1146 1147 propagate_rate(&osc_ck); /* update main root fast */ 1148 propagate_rate(&func_32k_ck); /* update main root slow */ 1149 1150 printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): " 1151 "%ld.%01ld/%ld/%ld MHz\n", 1152 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, 1153 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; 1154 1155 /* 1156 * Only enable those clocks we will need, let the drivers 1157 * enable other clocks as necessary 1158 */ 1159 clk_enable(&sync_32k_ick); 1160 clk_enable(&omapctrl_ick); 1161 1162 /* Force the APLLs active during bootup to avoid disabling and 1163 * enabling them unnecessarily. */ 1164 clk_enable(&apll96_ck); 1165 clk_enable(&apll54_ck); 1166 1167 if (cpu_is_omap2430()) 1168 clk_enable(&sdrc_ick); 1169 1170 /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */ 1171 vclk = clk_get(NULL, "virt_prcm_set"); 1172 sclk = clk_get(NULL, "sys_ck"); 1173 1174 return 0; 1175 } 1176 1177 static int __init omap2_disable_aplls(void) 1178 { 1179 clk_disable(&apll96_ck); 1180 clk_disable(&apll54_ck); 1181 1182 return 0; 1183 } 1184 late_initcall(omap2_disable_aplls); 1185