1 /* 2 * linux/arch/arm/mach-omap2/clock.c 3 * 4 * Copyright (C) 2005-2008 Texas Instruments, Inc. 5 * Copyright (C) 2004-2010 Nokia Corporation 6 * 7 * Contacts: 8 * Richard Woodruff <r-woodruff2@ti.com> 9 * Paul Walmsley 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 #undef DEBUG 16 17 #include <linux/kernel.h> 18 #include <linux/export.h> 19 #include <linux/list.h> 20 #include <linux/errno.h> 21 #include <linux/err.h> 22 #include <linux/delay.h> 23 #include <linux/clk-provider.h> 24 #include <linux/io.h> 25 #include <linux/bitops.h> 26 #include <linux/clk-private.h> 27 #include <asm/cpu.h> 28 29 #include <trace/events/power.h> 30 31 #include "soc.h" 32 #include "clockdomain.h" 33 #include "clock.h" 34 #include "cm.h" 35 #include "cm2xxx.h" 36 #include "cm3xxx.h" 37 #include "cm-regbits-24xx.h" 38 #include "cm-regbits-34xx.h" 39 #include "common.h" 40 41 /* 42 * MAX_MODULE_ENABLE_WAIT: maximum of number of microseconds to wait 43 * for a module to indicate that it is no longer in idle 44 */ 45 #define MAX_MODULE_ENABLE_WAIT 100000 46 47 u16 cpu_mask; 48 49 /* 50 * Clock features setup. Used instead of CPU type checks. 51 */ 52 struct ti_clk_features ti_clk_features; 53 54 /* 55 * clkdm_control: if true, then when a clock is enabled in the 56 * hardware, its clockdomain will first be enabled; and when a clock 57 * is disabled in the hardware, its clockdomain will be disabled 58 * afterwards. 59 */ 60 static bool clkdm_control = true; 61 62 static LIST_HEAD(clk_hw_omap_clocks); 63 void __iomem *clk_memmaps[CLK_MAX_MEMMAPS]; 64 65 void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg) 66 { 67 if (clk->flags & MEMMAP_ADDRESSING) { 68 struct clk_omap_reg *r = (struct clk_omap_reg *)® 69 writel_relaxed(val, clk_memmaps[r->index] + r->offset); 70 } else { 71 writel_relaxed(val, reg); 72 } 73 } 74 75 u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg) 76 { 77 u32 val; 78 79 if (clk->flags & MEMMAP_ADDRESSING) { 80 struct clk_omap_reg *r = (struct clk_omap_reg *)® 81 val = readl_relaxed(clk_memmaps[r->index] + r->offset); 82 } else { 83 val = readl_relaxed(reg); 84 } 85 86 return val; 87 } 88 89 /* 90 * Used for clocks that have the same value as the parent clock, 91 * divided by some factor 92 */ 93 unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw, 94 unsigned long parent_rate) 95 { 96 struct clk_hw_omap *oclk; 97 98 if (!hw) { 99 pr_warn("%s: hw is NULL\n", __func__); 100 return -EINVAL; 101 } 102 103 oclk = to_clk_hw_omap(hw); 104 105 WARN_ON(!oclk->fixed_div); 106 107 return parent_rate / oclk->fixed_div; 108 } 109 110 /* 111 * OMAP2+ specific clock functions 112 */ 113 114 /* Private functions */ 115 116 117 /** 118 * _wait_idlest_generic - wait for a module to leave the idle state 119 * @clk: module clock to wait for (needed for register offsets) 120 * @reg: virtual address of module IDLEST register 121 * @mask: value to mask against to determine if the module is active 122 * @idlest: idle state indicator (0 or 1) for the clock 123 * @name: name of the clock (for printk) 124 * 125 * Wait for a module to leave idle, where its idle-status register is 126 * not inside the CM module. Returns 1 if the module left idle 127 * promptly, or 0 if the module did not leave idle before the timeout 128 * elapsed. XXX Deprecated - should be moved into drivers for the 129 * individual IP block that the IDLEST register exists in. 130 */ 131 static int _wait_idlest_generic(struct clk_hw_omap *clk, void __iomem *reg, 132 u32 mask, u8 idlest, const char *name) 133 { 134 int i = 0, ena = 0; 135 136 ena = (idlest) ? 0 : mask; 137 138 omap_test_timeout(((omap2_clk_readl(clk, reg) & mask) == ena), 139 MAX_MODULE_ENABLE_WAIT, i); 140 141 if (i < MAX_MODULE_ENABLE_WAIT) 142 pr_debug("omap clock: module associated with clock %s ready after %d loops\n", 143 name, i); 144 else 145 pr_err("omap clock: module associated with clock %s didn't enable in %d tries\n", 146 name, MAX_MODULE_ENABLE_WAIT); 147 148 return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0; 149 }; 150 151 /** 152 * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE 153 * @clk: struct clk * belonging to the module 154 * 155 * If the necessary clocks for the OMAP hardware IP block that 156 * corresponds to clock @clk are enabled, then wait for the module to 157 * indicate readiness (i.e., to leave IDLE). This code does not 158 * belong in the clock code and will be moved in the medium term to 159 * module-dependent code. No return value. 160 */ 161 static void _omap2_module_wait_ready(struct clk_hw_omap *clk) 162 { 163 void __iomem *companion_reg, *idlest_reg; 164 u8 other_bit, idlest_bit, idlest_val, idlest_reg_id; 165 s16 prcm_mod; 166 int r; 167 168 /* Not all modules have multiple clocks that their IDLEST depends on */ 169 if (clk->ops->find_companion) { 170 clk->ops->find_companion(clk, &companion_reg, &other_bit); 171 if (!(omap2_clk_readl(clk, companion_reg) & (1 << other_bit))) 172 return; 173 } 174 175 clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); 176 r = cm_split_idlest_reg(idlest_reg, &prcm_mod, &idlest_reg_id); 177 if (r) { 178 /* IDLEST register not in the CM module */ 179 _wait_idlest_generic(clk, idlest_reg, (1 << idlest_bit), 180 idlest_val, __clk_get_name(clk->hw.clk)); 181 } else { 182 cm_wait_module_ready(prcm_mod, idlest_reg_id, idlest_bit); 183 }; 184 } 185 186 /* Public functions */ 187 188 /** 189 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk 190 * @clk: OMAP clock struct ptr to use 191 * 192 * Convert a clockdomain name stored in a struct clk 'clk' into a 193 * clockdomain pointer, and save it into the struct clk. Intended to be 194 * called during clk_register(). No return value. 195 */ 196 void omap2_init_clk_clkdm(struct clk_hw *hw) 197 { 198 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 199 struct clockdomain *clkdm; 200 const char *clk_name; 201 202 if (!clk->clkdm_name) 203 return; 204 205 clk_name = __clk_get_name(hw->clk); 206 207 clkdm = clkdm_lookup(clk->clkdm_name); 208 if (clkdm) { 209 pr_debug("clock: associated clk %s to clkdm %s\n", 210 clk_name, clk->clkdm_name); 211 clk->clkdm = clkdm; 212 } else { 213 pr_debug("clock: could not associate clk %s to clkdm %s\n", 214 clk_name, clk->clkdm_name); 215 } 216 } 217 218 /** 219 * omap2_clk_disable_clkdm_control - disable clkdm control on clk enable/disable 220 * 221 * Prevent the OMAP clock code from calling into the clockdomain code 222 * when a hardware clock in that clockdomain is enabled or disabled. 223 * Intended to be called at init time from omap*_clk_init(). No 224 * return value. 225 */ 226 void __init omap2_clk_disable_clkdm_control(void) 227 { 228 clkdm_control = false; 229 } 230 231 /** 232 * omap2_clk_dflt_find_companion - find companion clock to @clk 233 * @clk: struct clk * to find the companion clock of 234 * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in 235 * @other_bit: u8 ** to return the companion clock bit shift in 236 * 237 * Note: We don't need special code here for INVERT_ENABLE for the 238 * time being since INVERT_ENABLE only applies to clocks enabled by 239 * CM_CLKEN_PLL 240 * 241 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's 242 * just a matter of XORing the bits. 243 * 244 * Some clocks don't have companion clocks. For example, modules with 245 * only an interface clock (such as MAILBOXES) don't have a companion 246 * clock. Right now, this code relies on the hardware exporting a bit 247 * in the correct companion register that indicates that the 248 * nonexistent 'companion clock' is active. Future patches will 249 * associate this type of code with per-module data structures to 250 * avoid this issue, and remove the casts. No return value. 251 */ 252 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, 253 void __iomem **other_reg, u8 *other_bit) 254 { 255 u32 r; 256 257 /* 258 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes 259 * it's just a matter of XORing the bits. 260 */ 261 r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN)); 262 263 *other_reg = (__force void __iomem *)r; 264 *other_bit = clk->enable_bit; 265 } 266 267 /** 268 * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk 269 * @clk: struct clk * to find IDLEST info for 270 * @idlest_reg: void __iomem ** to return the CM_IDLEST va in 271 * @idlest_bit: u8 * to return the CM_IDLEST bit shift in 272 * @idlest_val: u8 * to return the idle status indicator 273 * 274 * Return the CM_IDLEST register address and bit shift corresponding 275 * to the module that "owns" this clock. This default code assumes 276 * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that 277 * the IDLEST register address ID corresponds to the CM_*CLKEN 278 * register address ID (e.g., that CM_FCLKEN2 corresponds to 279 * CM_IDLEST2). This is not true for all modules. No return value. 280 */ 281 void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, 282 void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val) 283 { 284 u32 r; 285 286 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); 287 *idlest_reg = (__force void __iomem *)r; 288 *idlest_bit = clk->enable_bit; 289 290 /* 291 * 24xx uses 0 to indicate not ready, and 1 to indicate ready. 292 * 34xx reverses this, just to keep us on our toes 293 * AM35xx uses both, depending on the module. 294 */ 295 if (cpu_is_omap24xx()) 296 *idlest_val = OMAP24XX_CM_IDLEST_VAL; 297 else if (cpu_is_omap34xx()) 298 *idlest_val = OMAP34XX_CM_IDLEST_VAL; 299 else 300 BUG(); 301 302 } 303 304 /** 305 * omap2_dflt_clk_enable - enable a clock in the hardware 306 * @hw: struct clk_hw * of the clock to enable 307 * 308 * Enable the clock @hw in the hardware. We first call into the OMAP 309 * clockdomain code to "enable" the corresponding clockdomain if this 310 * is the first enabled user of the clockdomain. Then program the 311 * hardware to enable the clock. Then wait for the IP block that uses 312 * this clock to leave idle (if applicable). Returns the error value 313 * from clkdm_clk_enable() if it terminated with an error, or -EINVAL 314 * if @hw has a null clock enable_reg, or zero upon success. 315 */ 316 int omap2_dflt_clk_enable(struct clk_hw *hw) 317 { 318 struct clk_hw_omap *clk; 319 u32 v; 320 int ret = 0; 321 322 clk = to_clk_hw_omap(hw); 323 324 if (clkdm_control && clk->clkdm) { 325 ret = clkdm_clk_enable(clk->clkdm, hw->clk); 326 if (ret) { 327 WARN(1, "%s: could not enable %s's clockdomain %s: %d\n", 328 __func__, __clk_get_name(hw->clk), 329 clk->clkdm->name, ret); 330 return ret; 331 } 332 } 333 334 if (unlikely(clk->enable_reg == NULL)) { 335 pr_err("%s: %s missing enable_reg\n", __func__, 336 __clk_get_name(hw->clk)); 337 ret = -EINVAL; 338 goto err; 339 } 340 341 /* FIXME should not have INVERT_ENABLE bit here */ 342 v = omap2_clk_readl(clk, clk->enable_reg); 343 if (clk->flags & INVERT_ENABLE) 344 v &= ~(1 << clk->enable_bit); 345 else 346 v |= (1 << clk->enable_bit); 347 omap2_clk_writel(v, clk, clk->enable_reg); 348 v = omap2_clk_readl(clk, clk->enable_reg); /* OCP barrier */ 349 350 if (clk->ops && clk->ops->find_idlest) 351 _omap2_module_wait_ready(clk); 352 353 return 0; 354 355 err: 356 if (clkdm_control && clk->clkdm) 357 clkdm_clk_disable(clk->clkdm, hw->clk); 358 return ret; 359 } 360 361 /** 362 * omap2_dflt_clk_disable - disable a clock in the hardware 363 * @hw: struct clk_hw * of the clock to disable 364 * 365 * Disable the clock @hw in the hardware, and call into the OMAP 366 * clockdomain code to "disable" the corresponding clockdomain if all 367 * clocks/hwmods in that clockdomain are now disabled. No return 368 * value. 369 */ 370 void omap2_dflt_clk_disable(struct clk_hw *hw) 371 { 372 struct clk_hw_omap *clk; 373 u32 v; 374 375 clk = to_clk_hw_omap(hw); 376 if (!clk->enable_reg) { 377 /* 378 * 'independent' here refers to a clock which is not 379 * controlled by its parent. 380 */ 381 pr_err("%s: independent clock %s has no enable_reg\n", 382 __func__, __clk_get_name(hw->clk)); 383 return; 384 } 385 386 v = omap2_clk_readl(clk, clk->enable_reg); 387 if (clk->flags & INVERT_ENABLE) 388 v |= (1 << clk->enable_bit); 389 else 390 v &= ~(1 << clk->enable_bit); 391 omap2_clk_writel(v, clk, clk->enable_reg); 392 /* No OCP barrier needed here since it is a disable operation */ 393 394 if (clkdm_control && clk->clkdm) 395 clkdm_clk_disable(clk->clkdm, hw->clk); 396 } 397 398 /** 399 * omap2_clkops_enable_clkdm - increment usecount on clkdm of @hw 400 * @hw: struct clk_hw * of the clock being enabled 401 * 402 * Increment the usecount of the clockdomain of the clock pointed to 403 * by @hw; if the usecount is 1, the clockdomain will be "enabled." 404 * Only needed for clocks that don't use omap2_dflt_clk_enable() as 405 * their enable function pointer. Passes along the return value of 406 * clkdm_clk_enable(), -EINVAL if @hw is not associated with a 407 * clockdomain, or 0 if clock framework-based clockdomain control is 408 * not implemented. 409 */ 410 int omap2_clkops_enable_clkdm(struct clk_hw *hw) 411 { 412 struct clk_hw_omap *clk; 413 int ret = 0; 414 415 clk = to_clk_hw_omap(hw); 416 417 if (unlikely(!clk->clkdm)) { 418 pr_err("%s: %s: no clkdm set ?!\n", __func__, 419 __clk_get_name(hw->clk)); 420 return -EINVAL; 421 } 422 423 if (unlikely(clk->enable_reg)) 424 pr_err("%s: %s: should use dflt_clk_enable ?!\n", __func__, 425 __clk_get_name(hw->clk)); 426 427 if (!clkdm_control) { 428 pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", 429 __func__, __clk_get_name(hw->clk)); 430 return 0; 431 } 432 433 ret = clkdm_clk_enable(clk->clkdm, hw->clk); 434 WARN(ret, "%s: could not enable %s's clockdomain %s: %d\n", 435 __func__, __clk_get_name(hw->clk), clk->clkdm->name, ret); 436 437 return ret; 438 } 439 440 /** 441 * omap2_clkops_disable_clkdm - decrement usecount on clkdm of @hw 442 * @hw: struct clk_hw * of the clock being disabled 443 * 444 * Decrement the usecount of the clockdomain of the clock pointed to 445 * by @hw; if the usecount is 0, the clockdomain will be "disabled." 446 * Only needed for clocks that don't use omap2_dflt_clk_disable() as their 447 * disable function pointer. No return value. 448 */ 449 void omap2_clkops_disable_clkdm(struct clk_hw *hw) 450 { 451 struct clk_hw_omap *clk; 452 453 clk = to_clk_hw_omap(hw); 454 455 if (unlikely(!clk->clkdm)) { 456 pr_err("%s: %s: no clkdm set ?!\n", __func__, 457 __clk_get_name(hw->clk)); 458 return; 459 } 460 461 if (unlikely(clk->enable_reg)) 462 pr_err("%s: %s: should use dflt_clk_disable ?!\n", __func__, 463 __clk_get_name(hw->clk)); 464 465 if (!clkdm_control) { 466 pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", 467 __func__, __clk_get_name(hw->clk)); 468 return; 469 } 470 471 clkdm_clk_disable(clk->clkdm, hw->clk); 472 } 473 474 /** 475 * omap2_dflt_clk_is_enabled - is clock enabled in the hardware? 476 * @hw: struct clk_hw * to check 477 * 478 * Return 1 if the clock represented by @hw is enabled in the 479 * hardware, or 0 otherwise. Intended for use in the struct 480 * clk_ops.is_enabled function pointer. 481 */ 482 int omap2_dflt_clk_is_enabled(struct clk_hw *hw) 483 { 484 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 485 u32 v; 486 487 v = omap2_clk_readl(clk, clk->enable_reg); 488 489 if (clk->flags & INVERT_ENABLE) 490 v ^= BIT(clk->enable_bit); 491 492 v &= BIT(clk->enable_bit); 493 494 return v ? 1 : 0; 495 } 496 497 static int __initdata mpurate; 498 499 /* 500 * By default we use the rate set by the bootloader. 501 * You can override this with mpurate= cmdline option. 502 */ 503 static int __init omap_clk_setup(char *str) 504 { 505 get_option(&str, &mpurate); 506 507 if (!mpurate) 508 return 1; 509 510 if (mpurate < 1000) 511 mpurate *= 1000000; 512 513 return 1; 514 } 515 __setup("mpurate=", omap_clk_setup); 516 517 /** 518 * omap2_init_clk_hw_omap_clocks - initialize an OMAP clock 519 * @clk: struct clk * to initialize 520 * 521 * Add an OMAP clock @clk to the internal list of OMAP clocks. Used 522 * temporarily for autoidle handling, until this support can be 523 * integrated into the common clock framework code in some way. No 524 * return value. 525 */ 526 void omap2_init_clk_hw_omap_clocks(struct clk *clk) 527 { 528 struct clk_hw_omap *c; 529 530 if (__clk_get_flags(clk) & CLK_IS_BASIC) 531 return; 532 533 c = to_clk_hw_omap(__clk_get_hw(clk)); 534 list_add(&c->node, &clk_hw_omap_clocks); 535 } 536 537 /** 538 * omap2_clk_enable_autoidle_all - enable autoidle on all OMAP clocks that 539 * support it 540 * 541 * Enable clock autoidle on all OMAP clocks that have allow_idle 542 * function pointers associated with them. This function is intended 543 * to be temporary until support for this is added to the common clock 544 * code. Returns 0. 545 */ 546 int omap2_clk_enable_autoidle_all(void) 547 { 548 struct clk_hw_omap *c; 549 550 list_for_each_entry(c, &clk_hw_omap_clocks, node) 551 if (c->ops && c->ops->allow_idle) 552 c->ops->allow_idle(c); 553 554 of_ti_clk_allow_autoidle_all(); 555 556 return 0; 557 } 558 559 /** 560 * omap2_clk_disable_autoidle_all - disable autoidle on all OMAP clocks that 561 * support it 562 * 563 * Disable clock autoidle on all OMAP clocks that have allow_idle 564 * function pointers associated with them. This function is intended 565 * to be temporary until support for this is added to the common clock 566 * code. Returns 0. 567 */ 568 int omap2_clk_disable_autoidle_all(void) 569 { 570 struct clk_hw_omap *c; 571 572 list_for_each_entry(c, &clk_hw_omap_clocks, node) 573 if (c->ops && c->ops->deny_idle) 574 c->ops->deny_idle(c); 575 576 of_ti_clk_deny_autoidle_all(); 577 578 return 0; 579 } 580 581 /** 582 * omap2_clk_deny_idle - disable autoidle on an OMAP clock 583 * @clk: struct clk * to disable autoidle for 584 * 585 * Disable autoidle on an OMAP clock. 586 */ 587 int omap2_clk_deny_idle(struct clk *clk) 588 { 589 struct clk_hw_omap *c; 590 591 if (__clk_get_flags(clk) & CLK_IS_BASIC) 592 return -EINVAL; 593 594 c = to_clk_hw_omap(__clk_get_hw(clk)); 595 if (c->ops && c->ops->deny_idle) 596 c->ops->deny_idle(c); 597 return 0; 598 } 599 600 /** 601 * omap2_clk_allow_idle - enable autoidle on an OMAP clock 602 * @clk: struct clk * to enable autoidle for 603 * 604 * Enable autoidle on an OMAP clock. 605 */ 606 int omap2_clk_allow_idle(struct clk *clk) 607 { 608 struct clk_hw_omap *c; 609 610 if (__clk_get_flags(clk) & CLK_IS_BASIC) 611 return -EINVAL; 612 613 c = to_clk_hw_omap(__clk_get_hw(clk)); 614 if (c->ops && c->ops->allow_idle) 615 c->ops->allow_idle(c); 616 return 0; 617 } 618 619 /** 620 * omap2_clk_enable_init_clocks - prepare & enable a list of clocks 621 * @clk_names: ptr to an array of strings of clock names to enable 622 * @num_clocks: number of clock names in @clk_names 623 * 624 * Prepare and enable a list of clocks, named by @clk_names. No 625 * return value. XXX Deprecated; only needed until these clocks are 626 * properly claimed and enabled by the drivers or core code that uses 627 * them. XXX What code disables & calls clk_put on these clocks? 628 */ 629 void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks) 630 { 631 struct clk *init_clk; 632 int i; 633 634 for (i = 0; i < num_clocks; i++) { 635 init_clk = clk_get(NULL, clk_names[i]); 636 clk_prepare_enable(init_clk); 637 } 638 } 639 640 const struct clk_hw_omap_ops clkhwops_wait = { 641 .find_idlest = omap2_clk_dflt_find_idlest, 642 .find_companion = omap2_clk_dflt_find_companion, 643 }; 644 645 /** 646 * omap_clocks_register - register an array of omap_clk 647 * @ocs: pointer to an array of omap_clk to register 648 */ 649 void __init omap_clocks_register(struct omap_clk oclks[], int cnt) 650 { 651 struct omap_clk *c; 652 653 for (c = oclks; c < oclks + cnt; c++) { 654 clkdev_add(&c->lk); 655 if (!__clk_init(NULL, c->lk.clk)) 656 omap2_init_clk_hw_omap_clocks(c->lk.clk); 657 } 658 } 659 660 /** 661 * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument 662 * @mpurate_ck_name: clk name of the clock to change rate 663 * 664 * Change the ARM MPU clock rate to the rate specified on the command 665 * line, if one was specified. @mpurate_ck_name should be 666 * "virt_prcm_set" on OMAP2xxx and "dpll1_ck" on OMAP34xx/OMAP36xx. 667 * XXX Does not handle voltage scaling - on OMAP2xxx this is currently 668 * handled by the virt_prcm_set clock, but this should be handled by 669 * the OPP layer. XXX This is intended to be handled by the OPP layer 670 * code in the near future and should be removed from the clock code. 671 * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects 672 * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name 673 * cannot be found, or 0 upon success. 674 */ 675 int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name) 676 { 677 struct clk *mpurate_ck; 678 int r; 679 680 if (!mpurate) 681 return -EINVAL; 682 683 mpurate_ck = clk_get(NULL, mpurate_ck_name); 684 if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name)) 685 return -ENOENT; 686 687 r = clk_set_rate(mpurate_ck, mpurate); 688 if (r < 0) { 689 WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n", 690 mpurate_ck_name, mpurate, r); 691 clk_put(mpurate_ck); 692 return -EINVAL; 693 } 694 695 calibrate_delay(); 696 clk_put(mpurate_ck); 697 698 return 0; 699 } 700 701 /** 702 * omap2_clk_print_new_rates - print summary of current clock tree rates 703 * @hfclkin_ck_name: clk name for the off-chip HF oscillator 704 * @core_ck_name: clk name for the on-chip CORE_CLK 705 * @mpu_ck_name: clk name for the ARM MPU clock 706 * 707 * Prints a short message to the console with the HFCLKIN oscillator 708 * rate, the rate of the CORE clock, and the rate of the ARM MPU clock. 709 * Called by the boot-time MPU rate switching code. XXX This is intended 710 * to be handled by the OPP layer code in the near future and should be 711 * removed from the clock code. No return value. 712 */ 713 void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, 714 const char *core_ck_name, 715 const char *mpu_ck_name) 716 { 717 struct clk *hfclkin_ck, *core_ck, *mpu_ck; 718 unsigned long hfclkin_rate; 719 720 mpu_ck = clk_get(NULL, mpu_ck_name); 721 if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name)) 722 return; 723 724 core_ck = clk_get(NULL, core_ck_name); 725 if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name)) 726 return; 727 728 hfclkin_ck = clk_get(NULL, hfclkin_ck_name); 729 if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name)) 730 return; 731 732 hfclkin_rate = clk_get_rate(hfclkin_ck); 733 734 pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", 735 (hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10), 736 (clk_get_rate(core_ck) / 1000000), 737 (clk_get_rate(mpu_ck) / 1000000)); 738 } 739 740 /** 741 * ti_clk_init_features - init clock features struct for the SoC 742 * 743 * Initializes the clock features struct based on the SoC type. 744 */ 745 void __init ti_clk_init_features(void) 746 { 747 } 748