1 /* 2 * linux/arch/arm/mach-omap2/clock.c 3 * 4 * Copyright (C) 2005-2008 Texas Instruments, Inc. 5 * Copyright (C) 2004-2010 Nokia Corporation 6 * 7 * Contacts: 8 * Richard Woodruff <r-woodruff2@ti.com> 9 * Paul Walmsley 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 */ 15 #undef DEBUG 16 17 #include <linux/kernel.h> 18 #include <linux/list.h> 19 #include <linux/errno.h> 20 #include <linux/err.h> 21 #include <linux/delay.h> 22 #include <linux/clk.h> 23 #include <linux/io.h> 24 #include <linux/bitops.h> 25 #include <trace/events/power.h> 26 27 #include <asm/cpu.h> 28 #include <plat/clock.h> 29 #include "clockdomain.h" 30 #include <plat/cpu.h> 31 #include <plat/prcm.h> 32 33 #include "clock.h" 34 #include "cm2xxx_3xxx.h" 35 #include "cm-regbits-24xx.h" 36 #include "cm-regbits-34xx.h" 37 38 u8 cpu_mask; 39 40 /* 41 * clkdm_control: if true, then when a clock is enabled in the 42 * hardware, its clockdomain will first be enabled; and when a clock 43 * is disabled in the hardware, its clockdomain will be disabled 44 * afterwards. 45 */ 46 static bool clkdm_control = true; 47 48 /* 49 * OMAP2+ specific clock functions 50 */ 51 52 /* Private functions */ 53 54 /** 55 * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE 56 * @clk: struct clk * belonging to the module 57 * 58 * If the necessary clocks for the OMAP hardware IP block that 59 * corresponds to clock @clk are enabled, then wait for the module to 60 * indicate readiness (i.e., to leave IDLE). This code does not 61 * belong in the clock code and will be moved in the medium term to 62 * module-dependent code. No return value. 63 */ 64 static void _omap2_module_wait_ready(struct clk *clk) 65 { 66 void __iomem *companion_reg, *idlest_reg; 67 u8 other_bit, idlest_bit, idlest_val; 68 69 /* Not all modules have multiple clocks that their IDLEST depends on */ 70 if (clk->ops->find_companion) { 71 clk->ops->find_companion(clk, &companion_reg, &other_bit); 72 if (!(__raw_readl(companion_reg) & (1 << other_bit))) 73 return; 74 } 75 76 clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); 77 78 omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val, 79 clk->name); 80 } 81 82 /* Public functions */ 83 84 /** 85 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk 86 * @clk: OMAP clock struct ptr to use 87 * 88 * Convert a clockdomain name stored in a struct clk 'clk' into a 89 * clockdomain pointer, and save it into the struct clk. Intended to be 90 * called during clk_register(). No return value. 91 */ 92 void omap2_init_clk_clkdm(struct clk *clk) 93 { 94 struct clockdomain *clkdm; 95 96 if (!clk->clkdm_name) 97 return; 98 99 clkdm = clkdm_lookup(clk->clkdm_name); 100 if (clkdm) { 101 pr_debug("clock: associated clk %s to clkdm %s\n", 102 clk->name, clk->clkdm_name); 103 clk->clkdm = clkdm; 104 } else { 105 pr_debug("clock: could not associate clk %s to " 106 "clkdm %s\n", clk->name, clk->clkdm_name); 107 } 108 } 109 110 /** 111 * omap2_clk_disable_clkdm_control - disable clkdm control on clk enable/disable 112 * 113 * Prevent the OMAP clock code from calling into the clockdomain code 114 * when a hardware clock in that clockdomain is enabled or disabled. 115 * Intended to be called at init time from omap*_clk_init(). No 116 * return value. 117 */ 118 void __init omap2_clk_disable_clkdm_control(void) 119 { 120 clkdm_control = false; 121 } 122 123 /** 124 * omap2_clk_dflt_find_companion - find companion clock to @clk 125 * @clk: struct clk * to find the companion clock of 126 * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in 127 * @other_bit: u8 ** to return the companion clock bit shift in 128 * 129 * Note: We don't need special code here for INVERT_ENABLE for the 130 * time being since INVERT_ENABLE only applies to clocks enabled by 131 * CM_CLKEN_PLL 132 * 133 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's 134 * just a matter of XORing the bits. 135 * 136 * Some clocks don't have companion clocks. For example, modules with 137 * only an interface clock (such as MAILBOXES) don't have a companion 138 * clock. Right now, this code relies on the hardware exporting a bit 139 * in the correct companion register that indicates that the 140 * nonexistent 'companion clock' is active. Future patches will 141 * associate this type of code with per-module data structures to 142 * avoid this issue, and remove the casts. No return value. 143 */ 144 void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, 145 u8 *other_bit) 146 { 147 u32 r; 148 149 /* 150 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes 151 * it's just a matter of XORing the bits. 152 */ 153 r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN)); 154 155 *other_reg = (__force void __iomem *)r; 156 *other_bit = clk->enable_bit; 157 } 158 159 /** 160 * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk 161 * @clk: struct clk * to find IDLEST info for 162 * @idlest_reg: void __iomem ** to return the CM_IDLEST va in 163 * @idlest_bit: u8 * to return the CM_IDLEST bit shift in 164 * @idlest_val: u8 * to return the idle status indicator 165 * 166 * Return the CM_IDLEST register address and bit shift corresponding 167 * to the module that "owns" this clock. This default code assumes 168 * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that 169 * the IDLEST register address ID corresponds to the CM_*CLKEN 170 * register address ID (e.g., that CM_FCLKEN2 corresponds to 171 * CM_IDLEST2). This is not true for all modules. No return value. 172 */ 173 void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, 174 u8 *idlest_bit, u8 *idlest_val) 175 { 176 u32 r; 177 178 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); 179 *idlest_reg = (__force void __iomem *)r; 180 *idlest_bit = clk->enable_bit; 181 182 /* 183 * 24xx uses 0 to indicate not ready, and 1 to indicate ready. 184 * 34xx reverses this, just to keep us on our toes 185 * AM35xx uses both, depending on the module. 186 */ 187 if (cpu_is_omap24xx()) 188 *idlest_val = OMAP24XX_CM_IDLEST_VAL; 189 else if (cpu_is_omap34xx()) 190 *idlest_val = OMAP34XX_CM_IDLEST_VAL; 191 else 192 BUG(); 193 194 } 195 196 int omap2_dflt_clk_enable(struct clk *clk) 197 { 198 u32 v; 199 200 if (unlikely(clk->enable_reg == NULL)) { 201 pr_err("clock.c: Enable for %s without enable code\n", 202 clk->name); 203 return 0; /* REVISIT: -EINVAL */ 204 } 205 206 v = __raw_readl(clk->enable_reg); 207 if (clk->flags & INVERT_ENABLE) 208 v &= ~(1 << clk->enable_bit); 209 else 210 v |= (1 << clk->enable_bit); 211 __raw_writel(v, clk->enable_reg); 212 v = __raw_readl(clk->enable_reg); /* OCP barrier */ 213 214 if (clk->ops->find_idlest) 215 _omap2_module_wait_ready(clk); 216 217 return 0; 218 } 219 220 void omap2_dflt_clk_disable(struct clk *clk) 221 { 222 u32 v; 223 224 if (!clk->enable_reg) { 225 /* 226 * 'Independent' here refers to a clock which is not 227 * controlled by its parent. 228 */ 229 printk(KERN_ERR "clock: clk_disable called on independent " 230 "clock %s which has no enable_reg\n", clk->name); 231 return; 232 } 233 234 v = __raw_readl(clk->enable_reg); 235 if (clk->flags & INVERT_ENABLE) 236 v |= (1 << clk->enable_bit); 237 else 238 v &= ~(1 << clk->enable_bit); 239 __raw_writel(v, clk->enable_reg); 240 /* No OCP barrier needed here since it is a disable operation */ 241 } 242 243 const struct clkops clkops_omap2_dflt_wait = { 244 .enable = omap2_dflt_clk_enable, 245 .disable = omap2_dflt_clk_disable, 246 .find_companion = omap2_clk_dflt_find_companion, 247 .find_idlest = omap2_clk_dflt_find_idlest, 248 }; 249 250 const struct clkops clkops_omap2_dflt = { 251 .enable = omap2_dflt_clk_enable, 252 .disable = omap2_dflt_clk_disable, 253 }; 254 255 /** 256 * omap2_clk_disable - disable a clock, if the system is not using it 257 * @clk: struct clk * to disable 258 * 259 * Decrements the usecount on struct clk @clk. If there are no users 260 * left, call the clkops-specific clock disable function to disable it 261 * in hardware. If the clock is part of a clockdomain (which they all 262 * should be), request that the clockdomain be disabled. (It too has 263 * a usecount, and so will not be disabled in the hardware until it no 264 * longer has any users.) If the clock has a parent clock (most of 265 * them do), then call ourselves, recursing on the parent clock. This 266 * can cause an entire branch of the clock tree to be powered off by 267 * simply disabling one clock. Intended to be called with the clockfw_lock 268 * spinlock held. No return value. 269 */ 270 void omap2_clk_disable(struct clk *clk) 271 { 272 if (clk->usecount == 0) { 273 WARN(1, "clock: %s: omap2_clk_disable() called, but usecount " 274 "already 0?", clk->name); 275 return; 276 } 277 278 pr_debug("clock: %s: decrementing usecount\n", clk->name); 279 280 clk->usecount--; 281 282 if (clk->usecount > 0) 283 return; 284 285 pr_debug("clock: %s: disabling in hardware\n", clk->name); 286 287 if (clk->ops && clk->ops->disable) { 288 trace_clock_disable(clk->name, 0, smp_processor_id()); 289 clk->ops->disable(clk); 290 } 291 292 if (clkdm_control && clk->clkdm) 293 clkdm_clk_disable(clk->clkdm, clk); 294 295 if (clk->parent) 296 omap2_clk_disable(clk->parent); 297 } 298 299 /** 300 * omap2_clk_enable - request that the system enable a clock 301 * @clk: struct clk * to enable 302 * 303 * Increments the usecount on struct clk @clk. If there were no users 304 * previously, then recurse up the clock tree, enabling all of the 305 * clock's parents and all of the parent clockdomains, and finally, 306 * enabling @clk's clockdomain, and @clk itself. Intended to be 307 * called with the clockfw_lock spinlock held. Returns 0 upon success 308 * or a negative error code upon failure. 309 */ 310 int omap2_clk_enable(struct clk *clk) 311 { 312 int ret; 313 314 pr_debug("clock: %s: incrementing usecount\n", clk->name); 315 316 clk->usecount++; 317 318 if (clk->usecount > 1) 319 return 0; 320 321 pr_debug("clock: %s: enabling in hardware\n", clk->name); 322 323 if (clk->parent) { 324 ret = omap2_clk_enable(clk->parent); 325 if (ret) { 326 WARN(1, "clock: %s: could not enable parent %s: %d\n", 327 clk->name, clk->parent->name, ret); 328 goto oce_err1; 329 } 330 } 331 332 if (clkdm_control && clk->clkdm) { 333 ret = clkdm_clk_enable(clk->clkdm, clk); 334 if (ret) { 335 WARN(1, "clock: %s: could not enable clockdomain %s: " 336 "%d\n", clk->name, clk->clkdm->name, ret); 337 goto oce_err2; 338 } 339 } 340 341 if (clk->ops && clk->ops->enable) { 342 trace_clock_enable(clk->name, 1, smp_processor_id()); 343 ret = clk->ops->enable(clk); 344 if (ret) { 345 WARN(1, "clock: %s: could not enable: %d\n", 346 clk->name, ret); 347 goto oce_err3; 348 } 349 } 350 351 return 0; 352 353 oce_err3: 354 if (clkdm_control && clk->clkdm) 355 clkdm_clk_disable(clk->clkdm, clk); 356 oce_err2: 357 if (clk->parent) 358 omap2_clk_disable(clk->parent); 359 oce_err1: 360 clk->usecount--; 361 362 return ret; 363 } 364 365 /* Given a clock and a rate apply a clock specific rounding function */ 366 long omap2_clk_round_rate(struct clk *clk, unsigned long rate) 367 { 368 if (clk->round_rate) 369 return clk->round_rate(clk, rate); 370 371 return clk->rate; 372 } 373 374 /* Set the clock rate for a clock source */ 375 int omap2_clk_set_rate(struct clk *clk, unsigned long rate) 376 { 377 int ret = -EINVAL; 378 379 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate); 380 381 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ 382 if (clk->set_rate) { 383 trace_clock_set_rate(clk->name, rate, smp_processor_id()); 384 ret = clk->set_rate(clk, rate); 385 } 386 387 return ret; 388 } 389 390 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) 391 { 392 if (!clk->clksel) 393 return -EINVAL; 394 395 if (clk->parent == new_parent) 396 return 0; 397 398 return omap2_clksel_set_parent(clk, new_parent); 399 } 400 401 /* OMAP3/4 non-CORE DPLL clkops */ 402 403 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) 404 405 const struct clkops clkops_omap3_noncore_dpll_ops = { 406 .enable = omap3_noncore_dpll_enable, 407 .disable = omap3_noncore_dpll_disable, 408 .allow_idle = omap3_dpll_allow_idle, 409 .deny_idle = omap3_dpll_deny_idle, 410 }; 411 412 const struct clkops clkops_omap3_core_dpll_ops = { 413 .allow_idle = omap3_dpll_allow_idle, 414 .deny_idle = omap3_dpll_deny_idle, 415 }; 416 417 #endif 418 419 /* 420 * OMAP2+ clock reset and init functions 421 */ 422 423 #ifdef CONFIG_OMAP_RESET_CLOCKS 424 void omap2_clk_disable_unused(struct clk *clk) 425 { 426 u32 regval32, v; 427 428 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0; 429 430 regval32 = __raw_readl(clk->enable_reg); 431 if ((regval32 & (1 << clk->enable_bit)) == v) 432 return; 433 434 pr_debug("Disabling unused clock \"%s\"\n", clk->name); 435 if (cpu_is_omap34xx()) { 436 omap2_clk_enable(clk); 437 omap2_clk_disable(clk); 438 } else { 439 clk->ops->disable(clk); 440 } 441 if (clk->clkdm != NULL) 442 pwrdm_clkdm_state_switch(clk->clkdm); 443 } 444 #endif 445 446 /** 447 * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument 448 * @mpurate_ck_name: clk name of the clock to change rate 449 * 450 * Change the ARM MPU clock rate to the rate specified on the command 451 * line, if one was specified. @mpurate_ck_name should be 452 * "virt_prcm_set" on OMAP2xxx and "dpll1_ck" on OMAP34xx/OMAP36xx. 453 * XXX Does not handle voltage scaling - on OMAP2xxx this is currently 454 * handled by the virt_prcm_set clock, but this should be handled by 455 * the OPP layer. XXX This is intended to be handled by the OPP layer 456 * code in the near future and should be removed from the clock code. 457 * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects 458 * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name 459 * cannot be found, or 0 upon success. 460 */ 461 int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name) 462 { 463 struct clk *mpurate_ck; 464 int r; 465 466 if (!mpurate) 467 return -EINVAL; 468 469 mpurate_ck = clk_get(NULL, mpurate_ck_name); 470 if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name)) 471 return -ENOENT; 472 473 r = clk_set_rate(mpurate_ck, mpurate); 474 if (IS_ERR_VALUE(r)) { 475 WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n", 476 mpurate_ck->name, mpurate, r); 477 clk_put(mpurate_ck); 478 return -EINVAL; 479 } 480 481 calibrate_delay(); 482 recalculate_root_clocks(); 483 484 clk_put(mpurate_ck); 485 486 return 0; 487 } 488 489 /** 490 * omap2_clk_print_new_rates - print summary of current clock tree rates 491 * @hfclkin_ck_name: clk name for the off-chip HF oscillator 492 * @core_ck_name: clk name for the on-chip CORE_CLK 493 * @mpu_ck_name: clk name for the ARM MPU clock 494 * 495 * Prints a short message to the console with the HFCLKIN oscillator 496 * rate, the rate of the CORE clock, and the rate of the ARM MPU clock. 497 * Called by the boot-time MPU rate switching code. XXX This is intended 498 * to be handled by the OPP layer code in the near future and should be 499 * removed from the clock code. No return value. 500 */ 501 void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, 502 const char *core_ck_name, 503 const char *mpu_ck_name) 504 { 505 struct clk *hfclkin_ck, *core_ck, *mpu_ck; 506 unsigned long hfclkin_rate; 507 508 mpu_ck = clk_get(NULL, mpu_ck_name); 509 if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name)) 510 return; 511 512 core_ck = clk_get(NULL, core_ck_name); 513 if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name)) 514 return; 515 516 hfclkin_ck = clk_get(NULL, hfclkin_ck_name); 517 if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name)) 518 return; 519 520 hfclkin_rate = clk_get_rate(hfclkin_ck); 521 522 pr_info("Switched to new clocking rate (Crystal/Core/MPU): " 523 "%ld.%01ld/%ld/%ld MHz\n", 524 (hfclkin_rate / 1000000), 525 ((hfclkin_rate / 100000) % 10), 526 (clk_get_rate(core_ck) / 1000000), 527 (clk_get_rate(mpu_ck) / 1000000)); 528 } 529 530 /* Common data */ 531 532 struct clk_functions omap2_clk_functions = { 533 .clk_enable = omap2_clk_enable, 534 .clk_disable = omap2_clk_disable, 535 .clk_round_rate = omap2_clk_round_rate, 536 .clk_set_rate = omap2_clk_set_rate, 537 .clk_set_parent = omap2_clk_set_parent, 538 .clk_disable_unused = omap2_clk_disable_unused, 539 #ifdef CONFIG_CPU_FREQ 540 /* These will be removed when the OPP code is integrated */ 541 .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table, 542 .clk_exit_cpufreq_table = omap2_clk_exit_cpufreq_table, 543 #endif 544 }; 545 546